Remove obsolete CIMV and CTVM opcodes (#82)

FuelLabs · Jun 28, 2022 · c668e8e · c668e8e
1 parent 9e2be7d
commit c668e8e
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Showing 4 changed files with 31 additions and 56 deletions.
diff --git a/fuel-asm/src/instruction.rs b/fuel-asm/src/instruction.rs
@@ -234,7 +234,6 @@ impl From<Instruction> for u32 {
             | OpcodeRepr::SRL
             | OpcodeRepr::SUB
             | OpcodeRepr::XOR
-            | OpcodeRepr::CIMV
             | OpcodeRepr::MCP
             | OpcodeRepr::LDC
             | OpcodeRepr::TR
@@ -263,7 +262,6 @@ impl From<Instruction> for u32 {
 
             OpcodeRepr::MOVE
             | OpcodeRepr::NOT
-            | OpcodeRepr::CTMV
             | OpcodeRepr::RETD
             | OpcodeRepr::MCL
             | OpcodeRepr::BHSH

diff --git a/fuel-asm/src/opcode.rs b/fuel-asm/src/opcode.rs
@@ -132,12 +132,6 @@ pub enum Opcode {
     /// Bitwise XORs a register and an immediate value.
     XORI(RegisterId, RegisterId, Immediate12),
 
-    /// Check relative timelock.
-    CIMV(RegisterId, RegisterId, RegisterId),
-
-    /// Check absolute timelock.
-    CTMV(RegisterId, RegisterId),
-
     /// Jump.
     JI(Immediate24),
 
@@ -350,8 +344,6 @@ impl Opcode {
             OpcodeRepr::SUBI => Opcode::SUBI(ra, rb, imm12),
             OpcodeRepr::XOR => Opcode::XOR(ra, rb, rc),
             OpcodeRepr::XORI => Opcode::XORI(ra, rb, imm12),
-            OpcodeRepr::CIMV => Opcode::CIMV(ra, rb, rc),
-            OpcodeRepr::CTMV => Opcode::CTMV(ra, rb),
             OpcodeRepr::JI => Opcode::JI(imm24),
             OpcodeRepr::JNEI => Opcode::JNEI(ra, rb, imm12),
             OpcodeRepr::JNZI => Opcode::JNZI(ra, imm18),
@@ -462,8 +454,6 @@ impl Opcode {
             Self::SUBI(ra, rb, _) => [Some(*ra), Some(*rb), None, None],
             Self::XOR(ra, rb, rc) => [Some(*ra), Some(*rb), Some(*rc), None],
             Self::XORI(ra, rb, _) => [Some(*ra), Some(*rb), None, None],
-            Self::CIMV(ra, rb, rc) => [Some(*ra), Some(*rb), Some(*rc), None],
-            Self::CTMV(ra, rb) => [Some(*ra), Some(*rb), None, None],
             Self::JI(_) => [None; 4],
             Self::JNEI(ra, rb, _) => [Some(*ra), Some(*rb), None, None],
             Self::JNZI(ra, _) => [Some(*ra), None, None, None],
@@ -567,8 +557,6 @@ impl Opcode {
             | Self::SRL(_, _, _)
             | Self::SUB(_, _, _)
             | Self::XOR(_, _, _)
-            | Self::CIMV(_, _, _)
-            | Self::CTMV(_, _)
             | Self::RET(_)
             | Self::RETD(_, _)
             | Self::ALOC(_)
@@ -868,15 +856,6 @@ impl From<Opcode> for u32 {
                     | ((rb as u32) << 12)
                     | (imm12 as u32)
             }
-            Opcode::CIMV(ra, rb, rc) => {
-                ((OpcodeRepr::CIMV as u32) << 24)
-                    | ((ra as u32) << 18)
-                    | ((rb as u32) << 12)
-                    | ((rc as u32) << 6)
-            }
-            Opcode::CTMV(ra, rb) => {
-                ((OpcodeRepr::CTMV as u32) << 24) | ((ra as u32) << 18) | ((rb as u32) << 12)
-            }
             Opcode::JI(imm24) => ((OpcodeRepr::JI as u32) << 24) | (imm24 as u32),
             Opcode::JNEI(ra, rb, imm12) => {
                 ((OpcodeRepr::JNEI as u32) << 24)

diff --git a/fuel-asm/src/opcode/consts.rs b/fuel-asm/src/opcode/consts.rs
@@ -74,10 +74,10 @@ pub enum OpcodeRepr {
     SUB = 0x20,
     /// XOR
     XOR = 0x21,
-    /// CIMV
-    CIMV = 0x22,
-    /// CTMV
-    CTMV = 0x23,
+    /// RESERV22
+    RESERV22 = 0x22,
+    /// RESERV23
+    RESERV23 = 0x23,
     /// RET
     RET = 0x24,
     /// RETD
@@ -546,10 +546,10 @@ impl OpcodeRepr {
 
         match self {
             ADD | AND | DIV | EQ | EXP | GT | LT | MLOG | MROO | MOD | MOVE | MUL | NOT | OR
-            | SLL | SRL | SUB | XOR | CIMV | CTMV | RET | ALOC | MCL | MCP | MEQ | ECR | K256
-            | S256 | XIL | XIS | XOL | XOS | XWL | XWS | NOOP | FLAG | ADDI | ANDI | DIVI
-            | EXPI | MODI | MULI | ORI | SLLI | SRLI | SUBI | XORI | JNEI | LB | LW | SB | SW
-            | MCPI | MCLI | GM | MOVI | JNZI | JI | JMP | JNE | CFEI | CFSI | GTF => true,
+            | SLL | SRL | SUB | XOR | RET | ALOC | MCL | MCP | MEQ | ECR | K256 | S256 | XIL
+            | XIS | XOL | XOS | XWL | XWS | NOOP | FLAG | ADDI | ANDI | DIVI | EXPI | MODI
+            | MULI | ORI | SLLI | SRLI | SUBI | XORI | JNEI | LB | LW | SB | SW | MCPI | MCLI
+            | GM | MOVI | JNZI | JI | JMP | JNE | CFEI | CFSI | GTF => true,
 
             _ => false,
         }
@@ -570,29 +570,29 @@ fn check_predicate_allowed() {
 
             RESERV00 | RESERV01 | RESERV02 | RESERV03 | RESERV04 | RESERV05 | RESERV06
             | RESERV07 | RESERV08 | RESERV09 | RESERV0A | RESERV0B | RESERV0C | RESERV0D
-            | RESERV0E | RESERV0F | RESERV37 | RESERV4D | RESERV4E | RESERV4F | RESERV62
-            | RESERV63 | RESERV64 | RESERV65 | RESERV66 | RESERV67 | RESERV68 | RESERV69
-            | RESERV6A | RESERV6B | RESERV6C | RESERV6D | RESERV6E | RESERV6F | RESERV74
-            | RESERV75 | RESERV76 | RESERV77 | RESERV78 | RESERV79 | RESERV7A | RESERV7B
-            | RESERV7C | RESERV7D | RESERV7E | RESERV7F | RESERV80 | RESERV81 | RESERV82
-            | RESERV83 | RESERV84 | RESERV85 | RESERV86 | RESERV87 | RESERV88 | RESERV89
-            | RESERV8A | RESERV8B | RESERV8C | RESERV8D | RESERV8E | RESERV8F | RESERV93
-            | RESERV94 | RESERV95 | RESERV96 | RESERV97 | RESERV98 | RESERV99 | RESERV9A
-            | RESERV9B | RESERV9C | RESERV9D | RESERV9E | RESERV9F | RESERVA0 | RESERVA1
-            | RESERVA2 | RESERVA3 | RESERVA4 | RESERVA5 | RESERVA6 | RESERVA7 | RESERVA8
-            | RESERVA9 | RESERVAA | RESERVAB | RESERVAC | RESERVAD | RESERVAE | RESERVAF
-            | RESERVB0 | RESERVB1 | RESERVB2 | RESERVB3 | RESERVB4 | RESERVB5 | RESERVB6
-            | RESERVB7 | RESERVB8 | RESERVB9 | RESERVBA | RESERVBB | RESERVBC | RESERVBD
-            | RESERVBE | RESERVBF | RESERVC0 | RESERVC1 | RESERVC2 | RESERVC3 | RESERVC4
-            | RESERVC5 | RESERVC6 | RESERVC7 | RESERVC8 | RESERVC9 | RESERVCA | RESERVCB
-            | RESERVCC | RESERVCD | RESERVCE | RESERVCF | RESERVD0 | RESERVD1 | RESERVD2
-            | RESERVD3 | RESERVD4 | RESERVD5 | RESERVD6 | RESERVD7 | RESERVD8 | RESERVD9
-            | RESERVDA | RESERVDB | RESERVDC | RESERVDD | RESERVDE | RESERVDF | RESERVE0
-            | RESERVE1 | RESERVE2 | RESERVE3 | RESERVE4 | RESERVE5 | RESERVE6 | RESERVE7
-            | RESERVE8 | RESERVE9 | RESERVEA | RESERVEB | RESERVEC | RESERVED | RESERVEE
-            | RESERVEF | RESERVF0 | RESERVF1 | RESERVF2 | RESERVF3 | RESERVF4 | RESERVF5
-            | RESERVF6 | RESERVF7 | RESERVF8 | RESERVF9 | RESERVFA | RESERVFB | RESERVFC
-            | RESERVFD | RESERVFE | RESERVFF => false,
+            | RESERV0E | RESERV0F | RESERV22 | RESERV23 | RESERV37 | RESERV4D | RESERV4E
+            | RESERV4F | RESERV62 | RESERV63 | RESERV64 | RESERV65 | RESERV66 | RESERV67
+            | RESERV68 | RESERV69 | RESERV6A | RESERV6B | RESERV6C | RESERV6D | RESERV6E
+            | RESERV6F | RESERV74 | RESERV75 | RESERV76 | RESERV77 | RESERV78 | RESERV79
+            | RESERV7A | RESERV7B | RESERV7C | RESERV7D | RESERV7E | RESERV7F | RESERV80
+            | RESERV81 | RESERV82 | RESERV83 | RESERV84 | RESERV85 | RESERV86 | RESERV87
+            | RESERV88 | RESERV89 | RESERV8A | RESERV8B | RESERV8C | RESERV8D | RESERV8E
+            | RESERV8F | RESERV93 | RESERV94 | RESERV95 | RESERV96 | RESERV97 | RESERV98
+            | RESERV99 | RESERV9A | RESERV9B | RESERV9C | RESERV9D | RESERV9E | RESERV9F
+            | RESERVA0 | RESERVA1 | RESERVA2 | RESERVA3 | RESERVA4 | RESERVA5 | RESERVA6
+            | RESERVA7 | RESERVA8 | RESERVA9 | RESERVAA | RESERVAB | RESERVAC | RESERVAD
+            | RESERVAE | RESERVAF | RESERVB0 | RESERVB1 | RESERVB2 | RESERVB3 | RESERVB4
+            | RESERVB5 | RESERVB6 | RESERVB7 | RESERVB8 | RESERVB9 | RESERVBA | RESERVBB
+            | RESERVBC | RESERVBD | RESERVBE | RESERVBF | RESERVC0 | RESERVC1 | RESERVC2
+            | RESERVC3 | RESERVC4 | RESERVC5 | RESERVC6 | RESERVC7 | RESERVC8 | RESERVC9
+            | RESERVCA | RESERVCB | RESERVCC | RESERVCD | RESERVCE | RESERVCF | RESERVD0
+            | RESERVD1 | RESERVD2 | RESERVD3 | RESERVD4 | RESERVD5 | RESERVD6 | RESERVD7
+            | RESERVD8 | RESERVD9 | RESERVDA | RESERVDB | RESERVDC | RESERVDD | RESERVDE
+            | RESERVDF | RESERVE0 | RESERVE1 | RESERVE2 | RESERVE3 | RESERVE4 | RESERVE5
+            | RESERVE6 | RESERVE7 | RESERVE8 | RESERVE9 | RESERVEA | RESERVEB | RESERVEC
+            | RESERVED | RESERVEE | RESERVEF | RESERVF0 | RESERVF1 | RESERVF2 | RESERVF3
+            | RESERVF4 | RESERVF5 | RESERVF6 | RESERVF7 | RESERVF8 | RESERVF9 | RESERVFA
+            | RESERVFB | RESERVFC | RESERVFD | RESERVFE | RESERVFF => false,
 
             _ => true,
         };

diff --git a/fuel-asm/tests/encoding.rs b/fuel-asm/tests/encoding.rs
@@ -40,8 +40,6 @@ fn opcode() {
         Opcode::SUBI(r, r, imm12),
         Opcode::XOR(r, r, r),
         Opcode::XORI(r, r, imm12),
-        Opcode::CIMV(r, r, r),
-        Opcode::CTMV(r, r),
         Opcode::JI(imm24),
         Opcode::JNEI(r, r, imm12),
         Opcode::JNZI(r, imm18),