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Add Cortex-M35P fast-model blinky example #9

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Feb 28, 2023
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Add Cortex-M35P fast-model blinky example #9

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23 changes: 23 additions & 0 deletions CORTEX_M35P_FAST_MODEL_BLINKY_GCC/CMSIS/CMakeLists.txt
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# Copyright 2023 Arm Limited and/or its affiliates <[email protected]>
#
# SPDX-License-Identifier: MIT

cmake_minimum_required(VERSION 3.15)

add_library(cmsis_bsp INTERFACE)

target_include_directories(cmsis_bsp
INTERFACE
include
)

target_compile_definitions(cmsis_bsp
INTERFACE
ARMCM35P
)

target_sources(cmsis_bsp
INTERFACE
${CMAKE_CURRENT_SOURCE_DIR}/source/startup_ARMCM35P.c
${CMAKE_CURRENT_SOURCE_DIR}/source/system_ARMCM35P.c
)
130 changes: 130 additions & 0 deletions CORTEX_M35P_FAST_MODEL_BLINKY_GCC/CMSIS/include/ARMCM35P.h
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/**************************************************************************//**
* @file ARMCM35P.h
* @brief CMSIS Core Peripheral Access Layer Header File for
* ARMCM35P Device (configured for ARMCM35P without FPU, without DSP extension, without TrustZone)
* @version V1.0.0
* @date 03. September 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/

#ifndef ARMCM35P_H
#define ARMCM35P_H

#ifdef __cplusplus
extern "C" {
#endif


/* ------------------------- Interrupt Number Definition ------------------------ */

typedef enum IRQn
{
/* ------------------- Processor Exceptions Numbers ----------------------------- */
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /* 3 HardFault Interrupt */
MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */
SVCall_IRQn = -5, /* 11 SV Call Interrupt */
DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
SysTick_IRQn = -1, /* 15 System Tick Interrupt */

/* ------------------- Processor Interrupt Numbers ------------------------------ */
Interrupt0_IRQn = 0,
Interrupt1_IRQn = 1,
Interrupt2_IRQn = 2,
Interrupt3_IRQn = 3,
Interrupt4_IRQn = 4,
Interrupt5_IRQn = 5,
Interrupt6_IRQn = 6,
Interrupt7_IRQn = 7,
Interrupt8_IRQn = 8,
Interrupt9_IRQn = 9
/* Interrupts 10 .. 480 are left out */
} IRQn_Type;


/* ================================================================================ */
/* ================ Processor and Core Peripheral Section ================ */
/* ================================================================================ */

/* ------- Start of section using anonymous unions and disabling warnings ------- */
#if defined (__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined (__ICCARM__)
#pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wc11-extensions"
#pragma clang diagnostic ignored "-Wreserved-id-macro"
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif


/* -------- Configuration of Core Peripherals ----------------------------------- */
#define __CM35P_REV 0x0000U /* Core revision r0p0 */
#define __SAUREGION_PRESENT 0U /* SAU regions present */
#define __MPU_PRESENT 1U /* MPU present */
#define __VTOR_PRESENT 1U /* VTOR present */
#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 0U /* no FPU present */
#define __DSP_PRESENT 0U /* no DSP extension present */

#include "core_cm35p.h" /* Processor and core peripherals */
#include "system_ARMCM35P.h" /* System Header */


/* -------- End of section using anonymous unions and disabling warnings -------- */
#if defined (__CC_ARM)
#pragma pop
#elif defined (__ICCARM__)
/* leave anonymous unions enabled */
#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#pragma clang diagnostic pop
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning restore
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif


#ifdef __cplusplus
}
#endif

#endif /* ARMCM35P_H */
130 changes: 130 additions & 0 deletions CORTEX_M35P_FAST_MODEL_BLINKY_GCC/CMSIS/include/ARMCM35P_DSP_FP.h
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/**************************************************************************//**
* @file ARMCM35P_DSP_FP.h
* @brief CMSIS Core Peripheral Access Layer Header File for
* ARMCM35P Device (configured for ARMCM35P with FPU, with DSP extension)
* @version V1.0.0
* @date 03. September 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/

#ifndef ARMCM35P_DSP_FP_H
#define ARMCM35P_DSP_FP_H

#ifdef __cplusplus
extern "C" {
#endif


/* ------------------------- Interrupt Number Definition ------------------------ */

typedef enum IRQn
{
/* ------------------- Processor Exceptions Numbers ----------------------------- */
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /* 3 HardFault Interrupt */
MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
SecureFault_IRQn = -9, /* 7 Secure Fault Interrupt */
SVCall_IRQn = -5, /* 11 SV Call Interrupt */
DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
SysTick_IRQn = -1, /* 15 System Tick Interrupt */

/* ------------------- Processor Interrupt Numbers ------------------------------ */
Interrupt0_IRQn = 0,
Interrupt1_IRQn = 1,
Interrupt2_IRQn = 2,
Interrupt3_IRQn = 3,
Interrupt4_IRQn = 4,
Interrupt5_IRQn = 5,
Interrupt6_IRQn = 6,
Interrupt7_IRQn = 7,
Interrupt8_IRQn = 8,
Interrupt9_IRQn = 9
/* Interrupts 10 .. 480 are left out */
} IRQn_Type;


/* ================================================================================ */
/* ================ Processor and Core Peripheral Section ================ */
/* ================================================================================ */

/* ------- Start of section using anonymous unions and disabling warnings ------- */
#if defined (__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined (__ICCARM__)
#pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wc11-extensions"
#pragma clang diagnostic ignored "-Wreserved-id-macro"
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif


/* -------- Configuration of Core Peripherals ----------------------------------- */
#define __CM35P_REV 0x0000U /* Core revision r0p0 */
#define __SAUREGION_PRESENT 0U /* SAU regions present */
#define __MPU_PRESENT 1U /* MPU present */
#define __VTOR_PRESENT 1U /* VTOR present */
#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1U /* FPU present */
#define __DSP_PRESENT 1U /* DSP extension present */

#include "core_cm35p.h" /* Processor and core peripherals */
#include "system_ARMCM35P.h" /* System Header */


/* -------- End of section using anonymous unions and disabling warnings -------- */
#if defined (__CC_ARM)
#pragma pop
#elif defined (__ICCARM__)
/* leave anonymous unions enabled */
#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
#pragma clang diagnostic pop
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning restore
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif


#ifdef __cplusplus
}
#endif

#endif /* ARMCM35P_DSP_FP_H */
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