ARM CM0+ MPU Port #1005
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ARM CM0+ MPU Port #1005
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Skptak
commented
Mar 1, 2024
Codecov ReportAll modified and coverable lines are covered by tests ✅
Additional details and impacted files@@ Coverage Diff @@
## main #1005 +/- ##
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Coverage 93.00% 93.00%
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Files 6 6
Lines 3200 3200
Branches 879 879
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Hits 2976 2976
Misses 111 111
Partials 113 113
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| #define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x7UL << 16UL ) | ||
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| #define portMPU_REGION_VALID ( 0x10UL ) | ||
| #define portMPU_RASR_TEX_S_C_B_MASK ( 0x3FUL ) |
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Should this be 0x7 which is then shifted by 16 bits?
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aggarg
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Mar 26, 2024
joshzarr
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Mar 26, 2024
laroche
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Apr 18, 2024
The number of implemented priority bits for Armv8-M baseline implementation is defined by the architecture as 2. Therefore the config option `configPRIO_BITS` is updated to 2. In addition, in Armv8-M baseline implementation BASEPRI is RES0. Therefore, `configMAX_SYSCALL_INTERRUPT_PRIORITY` is not supported. Hence this config option is removed. Signed-off-by: Devaraj Ranganna <[email protected]> Co-authored-by: Gaurav-Aggarwal-AWS <[email protected]>
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Description
This pull request creates an ARM Cortex M0 Plus MPU Enabled Port
These changes have been overlayed onto the ARM_CM23_NTZ/non_secure port to create a minimal diff for the review
When the changes have been reviewed and approved this will then be moved into a separate directory.
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Checklist:
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