Remove __NVIC_PRIO_BITS and configPRIO_BITS check in port (#683)

* Remove __NVIC_PRIO_BITS and configPRIO_BITS check in CM3, CM4 and ARMv8. * Add hardware not implemented bits check. These bits should be zero. --------- Co-authored-by: Gaurav-Aggarwal-AWS <[email protected]>
FreeRTOS · Jun 8, 2023 · 4a35c97 · 4a35c97
1 parent d3c289f
commit 4a35c97
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Showing 37 changed files with 148 additions and 961 deletions.
diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c
@@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
         configASSERT( ucMaxSysCallPriority );
 
+        /* Check that the bits not implemented bits in hardware are zero in
+         * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
 
@@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
             ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
         }
 
-        /* The interrupt priority bits are not modelled in QEMU and the assert that
-         * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
-         * Therefore, this assert is not adding any value for QEMU targets. The config
-         * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
-         * `FreeRTOSConfig.h` for QEMU targets. */
-        #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
-        {
-            #ifdef __NVIC_PRIO_BITS
-            {
-                /*
-                 * Check that the number of implemented priority bits queried from
-                 * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
-                 */
-                configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
-            }
-            #endif /* __NVIC_PRIO_BITS */
-
-            #ifdef configPRIO_BITS
-            {
-                /*
-                 * Check that the number of implemented priority bits queried from
-                 * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
-                 */
-                configASSERT( ulImplementedPrioBits == configPRIO_BITS );
-            }
-            #endif /* configPRIO_BITS */
-        }
-        #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
-
         /* Shift the priority group value back to its position within the AIRCR
          * register. */
         ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

diff --git a/portable/CCS/ARM_CM3/port.c b/portable/CCS/ARM_CM3/port.c
@@ -249,6 +249,10 @@ BaseType_t xPortStartScheduler( void )
          * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
         configASSERT( ucMaxSysCallPriority );
 
+        /* Check that the bits not implemented bits in hardware are zero in
+         * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
 
@@ -285,28 +289,6 @@ BaseType_t xPortStartScheduler( void )
             ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
         }
 
-        #ifdef __NVIC_PRIO_BITS
-        {
-            /*
-             * Check that the number of implemented priority bits queried from
-             * hardware is at least as many as specified in the CMSIS
-             * __NVIC_PRIO_BITS configuration macro.
-             */
-            configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS );
-        }
-        #endif
-
-        #ifdef configPRIO_BITS
-        {
-            /*
-             * Check that the number of implemented priority bits queried from
-             * hardware is at least as many as specified in the FreeRTOS
-             * configPRIO_BITS configuration macro.
-             */
-            configASSERT( ulImplementedPrioBits >= configPRIO_BITS );
-        }
-        #endif
-
         /* Shift the priority group value back to its position within the AIRCR
          * register. */
         ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

diff --git a/portable/CCS/ARM_CM4F/port.c b/portable/CCS/ARM_CM4F/port.c
@@ -268,6 +268,10 @@ BaseType_t xPortStartScheduler( void )
          * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
         configASSERT( ucMaxSysCallPriority );
 
+        /* Check that the bits not implemented bits in hardware are zero in
+         * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
 
@@ -304,28 +308,6 @@ BaseType_t xPortStartScheduler( void )
             ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
         }
 
-        #ifdef __NVIC_PRIO_BITS
-        {
-            /*
-             * Check that the number of implemented priority bits queried from
-             * hardware is at least as many as specified in the CMSIS
-             * __NVIC_PRIO_BITS configuration macro.
-             */
-            configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS );
-        }
-        #endif
-
-        #ifdef configPRIO_BITS
-        {
-            /*
-             * Check that the number of implemented priority bits queried from
-             * hardware is at least as many as specified in the FreeRTOS
-             * configPRIO_BITS configuration macro.
-             */
-            configASSERT( ulImplementedPrioBits >= configPRIO_BITS );
-        }
-        #endif
-
         /* Shift the priority group value back to its position within the AIRCR
          * register. */
         ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

diff --git a/portable/GCC/ARM_CM23/non_secure/port.c b/portable/GCC/ARM_CM23/non_secure/port.c
@@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
         configASSERT( ucMaxSysCallPriority );
 
+        /* Check that the bits not implemented bits in hardware are zero in
+         * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
 
@@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
             ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
         }
 
-        /* The interrupt priority bits are not modelled in QEMU and the assert that
-         * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
-         * Therefore, this assert is not adding any value for QEMU targets. The config
-         * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
-         * `FreeRTOSConfig.h` for QEMU targets. */
-        #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
-        {
-            #ifdef __NVIC_PRIO_BITS
-            {
-                /*
-                 * Check that the number of implemented priority bits queried from
-                 * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
-                 */
-                configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
-            }
-            #endif /* __NVIC_PRIO_BITS */
-
-            #ifdef configPRIO_BITS
-            {
-                /*
-                 * Check that the number of implemented priority bits queried from
-                 * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
-                 */
-                configASSERT( ulImplementedPrioBits == configPRIO_BITS );
-            }
-            #endif /* configPRIO_BITS */
-        }
-        #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
-
         /* Shift the priority group value back to its position within the AIRCR
          * register. */
         ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
@@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
         configASSERT( ucMaxSysCallPriority );
 
+        /* Check that the bits not implemented bits in hardware are zero in
+         * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
 
@@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
             ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
         }
 
-        /* The interrupt priority bits are not modelled in QEMU and the assert that
-         * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
-         * Therefore, this assert is not adding any value for QEMU targets. The config
-         * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
-         * `FreeRTOSConfig.h` for QEMU targets. */
-        #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
-        {
-            #ifdef __NVIC_PRIO_BITS
-            {
-                /*
-                 * Check that the number of implemented priority bits queried from
-                 * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
-                 */
-                configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
-            }
-            #endif /* __NVIC_PRIO_BITS */
-
-            #ifdef configPRIO_BITS
-            {
-                /*
-                 * Check that the number of implemented priority bits queried from
-                 * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
-                 */
-                configASSERT( ulImplementedPrioBits == configPRIO_BITS );
-            }
-            #endif /* configPRIO_BITS */
-        }
-        #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
-
         /* Shift the priority group value back to its position within the AIRCR
          * register. */
         ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

diff --git a/portable/GCC/ARM_CM3/port.c b/portable/GCC/ARM_CM3/port.c
@@ -292,6 +292,10 @@ BaseType_t xPortStartScheduler( void )
          * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
         configASSERT( ucMaxSysCallPriority );
 
+        /* Check that the bits not implemented bits in hardware are zero in
+         * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
 
@@ -328,28 +332,6 @@ BaseType_t xPortStartScheduler( void )
             ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
         }
 
-        #ifdef __NVIC_PRIO_BITS
-        {
-            /*
-             * Check that the number of implemented priority bits queried from
-             * hardware is at least as many as specified in the CMSIS
-             * __NVIC_PRIO_BITS configuration macro.
-             */
-            configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS );
-        }
-        #endif
-
-        #ifdef configPRIO_BITS
-        {
-            /*
-             * Check that the number of implemented priority bits queried from
-             * hardware is at least as many as specified in the FreeRTOS
-             * configPRIO_BITS configuration macro.
-             */
-            configASSERT( ulImplementedPrioBits >= configPRIO_BITS );
-        }
-        #endif
-
         /* Shift the priority group value back to its position within the AIRCR
          * register. */
         ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c
@@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
         configASSERT( ucMaxSysCallPriority );
 
+        /* Check that the bits not implemented bits in hardware are zero in
+         * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
 
@@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
             ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
         }
 
-        /* The interrupt priority bits are not modelled in QEMU and the assert that
-         * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
-         * Therefore, this assert is not adding any value for QEMU targets. The config
-         * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
-         * `FreeRTOSConfig.h` for QEMU targets. */
-        #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
-        {
-            #ifdef __NVIC_PRIO_BITS
-            {
-                /*
-                 * Check that the number of implemented priority bits queried from
-                 * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
-                 */
-                configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
-            }
-            #endif /* __NVIC_PRIO_BITS */
-
-            #ifdef configPRIO_BITS
-            {
-                /*
-                 * Check that the number of implemented priority bits queried from
-                 * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
-                 */
-                configASSERT( ulImplementedPrioBits == configPRIO_BITS );
-            }
-            #endif /* configPRIO_BITS */
-        }
-        #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
-
         /* Shift the priority group value back to its position within the AIRCR
          * register. */
         ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
@@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
          * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
         configASSERT( ucMaxSysCallPriority );
 
+        /* Check that the bits not implemented bits in hardware are zero in
+         * configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
+
         /* Calculate the maximum acceptable priority group value for the number
          * of bits read back. */
 
@@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
             ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
         }
 
-        /* The interrupt priority bits are not modelled in QEMU and the assert that
-         * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
-         * Therefore, this assert is not adding any value for QEMU targets. The config
-         * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
-         * `FreeRTOSConfig.h` for QEMU targets. */
-        #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
-        {
-            #ifdef __NVIC_PRIO_BITS
-            {
-                /*
-                 * Check that the number of implemented priority bits queried from
-                 * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
-                 */
-                configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
-            }
-            #endif /* __NVIC_PRIO_BITS */
-
-            #ifdef configPRIO_BITS
-            {
-                /*
-                 * Check that the number of implemented priority bits queried from
-                 * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
-                 */
-                configASSERT( ulImplementedPrioBits == configPRIO_BITS );
-            }
-            #endif /* configPRIO_BITS */
-        }
-        #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
-
         /* Shift the priority group value back to its position within the AIRCR
          * register. */
         ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;