Merge pull request #281 from FPGAwars/up5k

Support for UP5K boards

CHANGELOG.md

@@ -2,6 +2,14 @@
 All notable changes to this project will be documented in this file.
 
 ## [Unreleased]
+### Support UP5K boards (#)
+- [iCEBreaker](https://github.com/icebreaker-fpga/icebreaker)
+- [iCEBreaker bitsy](https://github.com/icebreaker-fpga/icebreaker)
+- [UPDuino v1.0](http://gnarlygrey.atspace.cc/development-platform.html#upduino)
+- [UPDuino v2.0](http://gnarlygrey.atspace.cc/development-platform.html#upduino_v2l)
+- [FPGA 101 Workshop Badge Board](https://github.com/mmicko/workshop_badge)
+- [iCE40 UltraPlus Breakout Board](http://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/iCE40UltraPlusBreakoutBoard)
+
 ### General
 - Add cs_CZ translation (by nerakino)
 - Add nl_NL translation (by @elektor-labs)

README.md

@@ -37,6 +37,17 @@ Visual editor for open FPGA boards. Built on top of the [Icestorm project](http:
 | [TinyFPGA B2](https://tinyfpga.com/b-series-guide.html) | Serial |
 | [TinyFPGA BX](https://tinyfpga.com/bx/guide.html) | Serial |
 
+#### UP5K
+
+| Board name | Interface |
+|:-|:-:|
+| [iCEBreaker](https://github.com/icebreaker-fpga/icebreaker) | FTDI |
+| [iCEBreaker bitsy](https://github.com/icebreaker-fpga/icebreaker) | FTDI |
+| [UPDuino v1.0](http://gnarlygrey.atspace.cc/development-platform.html#upduino) | FTDI |
+| [UPDuino v2.0](http://gnarlygrey.atspace.cc/development-platform.html#upduino_v2l) | FTDI |
+| [FPGA 101 Workshop Badge Board](https://github.com/mmicko/workshop_badge) | FTDI |
+| [iCE40 UltraPlus Breakout Board](http://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/iCE40UltraPlusBreakoutBoard) | FTDI |
+
 ## Installation
 
 * **GNU/Linux**
@@ -165,6 +176,7 @@ There is a [Wishlist](https://github.com/FPGAwars/icestudio/wiki/Wishlist:-propo
 
 |Version | Contributors |
 |:-:|:-:|
+| 0.4 | [Elektor.Labs](https://github.com/elektor-labs), [Piotr Esden-Tempski](https://github.com/esden) |
 | 0.3 | [Lorea-Aldabaldetreku](https://github.com/Lorea-Aldabaldetreku), [Carlos Díaz](https://github.com/C47D), [Martoni](https://github.com/Martoni), [Xoan Sampaiño](https://github.com/xoan), [Unai](https://github.com/1138-4EB), [Francisco Sayas](https://github.com/fsayas), [Pascal Cotret](https://github.com/pcotret), [Juan Jose Luna Espinosa](https://github.com/yomboprime), [Salvador E. Tropea](https://github.com/set-soft), [redbeard](https://github.com/brianredbeard), [Eladio Delgado](https://github.com/EladioDM), [Philipp van Kempen](https://github.com/PhilippvK) |
 | 0.2 | [Tomás Calvo](https://github.com/tocalvo), [Juan González (Obijuan)](https://github.com/Obijuan), [Carlos Díaz](https://github.com/C47D), [Xoan Sampaiño](https://github.com/xoan), [Salvador E. Tropea](https://github.com/set-soft), [Democrito](https://github.com/Democrito), [Martoni](https://github.com/Martoni), [Pascal Cotret](https://github.com/pcotret) |
 | 0.1 | [Miguel Sánchez de León Peque](https://github.com/Peque) |

app/package.json

@@ -1,6 +1,6 @@
 {
   "name": "icestudio",
-  "version": "0.3.3",
+  "version": "0.4.0-dev",
   "description": "Visual editor for open FPGA boards",
   "author": "Jesús Arroyo Torrens <[email protected]>",
   "repository": "https://github.com/FPGAwars/icestudio",
@@ -18,8 +18,8 @@
     "icon": "resources/images/icestudio-logo.png"
   },
   "apio": {
-    "min": "0.3.6",
-    "max": "0.4.0",
+    "min": "0.4.0b5",
+    "max": "0.5.0",
     "extras": [
       "blackiceprog",
       "tinyfpgab",

app/resources/boards/TinyFPGA-B2/info.json

@@ -1,6 +1,6 @@
 {
   "label": "TinyFPGA B2",
-  "datasheet": "https://github.com/tinyfpga/TinyFPGA-B-Series",
+  "datasheet": "http://tinyfpga.com/b-series-guide.html",
   "interface": "Serial",
   "FPGAResources": {
     "ffs": 7680,

app/resources/boards/TinyFPGA-B2/pinout.pcf

@@ -3,11 +3,11 @@
 #- By Luke Valenty
 #- October - 2017
 #- GPL license
+#- TinyFPGA B-series information: https://github.com/tinyfpga/TinyFPGA-B-Series/
 # -----------------------------------------------------------------------------
-#
-# TinyFPGA B-series information: https://github.com/tinyfpga/TinyFPGA-B-Series/
 
-# -- Left side of board
+
+# ------------ Left side ------------------------------------------------------
 set_io --warn-no-port USB_DP A3
 set_io --warn-no-port USB_DM A4
 set_io --warn-no-port CLK    B4  # input
@@ -22,7 +22,8 @@ set_io --warn-no-port PIN_11 G1
 set_io --warn-no-port PIN_12 H1
 set_io --warn-no-port PIN_13 J1
 
-# -- Right side of board
+
+# ------------ Right side -----------------------------------------------------
 set_io --warn-no-port SDO    G6
 set_io --warn-no-port SDI    H7
 set_io --warn-no-port SCK    G7

app/resources/boards/TinyFPGA-BX/pinout.pcf

@@ -3,32 +3,35 @@
 #- By Luke Valenty
 #- May - 2018
 #- GPLv3 license
+#- Board information: https://github.com/tinyfpga/TinyFPGA-BX/
 # -----------------------------------------------------------------------------
-#
-# TinyFPGA BX information: https://github.com/tinyfpga/TinyFPGA-BX/
 
-# -- LED pin on bottom of board
-set_io --warn-no-port LED B3 # output
 
-# -- 16MHz clock pin on bottom of board
-set_io --warn-no-port CLK B2 # input
+# --- LED pin on bottom of board ----------------------------------------------
+set_io --warn-no-port LED B3  # output
 
-# -- Left side of board
-set_io --warn-no-port PIN_1 A2
-set_io --warn-no-port PIN_2 A1
-set_io --warn-no-port PIN_3 B1
-set_io --warn-no-port PIN_4 C2
-set_io --warn-no-port PIN_5 C1
-set_io --warn-no-port PIN_6 D2
-set_io --warn-no-port PIN_7 D1
-set_io --warn-no-port PIN_8 E2
-set_io --warn-no-port PIN_9 E1
+
+# --- 16MHz clock pin on bottom of board --------------------------------------
+set_io --warn-no-port CLK B2  # input
+
+
+# --- Left side of board ------------------------------------------------------
+set_io --warn-no-port PIN_1  A2
+set_io --warn-no-port PIN_2  A1
+set_io --warn-no-port PIN_3  B1
+set_io --warn-no-port PIN_4  C2
+set_io --warn-no-port PIN_5  C1
+set_io --warn-no-port PIN_6  D2
+set_io --warn-no-port PIN_7  D1
+set_io --warn-no-port PIN_8  E2
+set_io --warn-no-port PIN_9  E1
 set_io --warn-no-port PIN_10 G2
 set_io --warn-no-port PIN_11 H1
 set_io --warn-no-port PIN_12 J1
 set_io --warn-no-port PIN_13 H2
 
-# -- Right side of board
+
+# --- Right side of board -----------------------------------------------------
 set_io --warn-no-port PIN_14 H9
 set_io --warn-no-port PIN_15 D9
 set_io --warn-no-port PIN_16 D8
@@ -41,15 +44,17 @@ set_io --warn-no-port PIN_22 A7
 set_io --warn-no-port PIN_23 B6
 set_io --warn-no-port PIN_24 A6
 
-# -- SPI flash interface on bottom of board
-set_io --warn-no-port SPI_SS F7
+
+# --- SPI flash interface on bottom of board ----------------------------------
+set_io --warn-no-port SPI_SS  F7
 set_io --warn-no-port SPI_SCK G7
 set_io --warn-no-port SPI_IO0 G6
 set_io --warn-no-port SPI_IO1 H7
 set_io --warn-no-port SPI_IO2 H4
 set_io --warn-no-port SPI_IO3 J8
 
-# -- General purpose pins on bottom of board
+
+# --- General purpose pins on bottom of board ---------------------------------
 set_io --warn-no-port PIN_25 G1
 set_io --warn-no-port PIN_26 J3
 set_io --warn-no-port PIN_27 J4
@@ -58,7 +63,8 @@ set_io --warn-no-port PIN_29 J9
 set_io --warn-no-port PIN_30 E8
 set_io --warn-no-port PIN_31 J2
 
-# -- USB pins on bottom of board
-set_io --warn-no-port USBP B4
-set_io --warn-no-port USBN A4
+
+# --- USB pins on bottom of board ---------------------------------------------
+set_io --warn-no-port USBP  B4
+set_io --warn-no-port USBN  A4
 set_io --warn-no-port USBPU A3

app/resources/boards/alhambra-ii/pinout.pcf

@@ -3,22 +3,23 @@
 #- By Juan Gonzalez (Obijuan) and Jesus Arroyo Torrens
 #- May - 2018
 #- GPL license
+#- Repo: https://github.com/FPGAwars/Alhambra-II-FPGA
 # -----------------------------------------------------------------------------
-# --  Repo: https://github.com/FPGAwars/Alhambra-II-FPGA
+
 
 # ------------ User Leds ------------------------------------------------------
-set_io --warn-no-port LED0  45  # output
-set_io --warn-no-port LED1  44  # output
-set_io --warn-no-port LED2  43  # output
-set_io --warn-no-port LED3  42  # output
-set_io --warn-no-port LED4  41  # output
-set_io --warn-no-port LED5  39  # output
-set_io --warn-no-port LED6  38  # output
-set_io --warn-no-port LED7  37  # output
+set_io --warn-no-port LED0 45  # output
+set_io --warn-no-port LED1 44  # output
+set_io --warn-no-port LED2 43  # output
+set_io --warn-no-port LED3 42  # output
+set_io --warn-no-port LED4 41  # output
+set_io --warn-no-port LED5 39  # output
+set_io --warn-no-port LED6 38  # output
+set_io --warn-no-port LED7 37  # output
 
 # ------------ User push buttons ----------------------------------------------
-set_io --warn-no-port SW1  34  # input
-set_io --warn-no-port SW2  33  # input
+set_io --warn-no-port SW1 34  # input
+set_io --warn-no-port SW2 33  # input
 
 # ------------ 5v Digital I/O -------------------------------------------------
 
@@ -44,14 +45,14 @@ set_io --warn-no-port SW2  33  # input
 #               -------------------------------     -------------------------
 
 # -- In top female header
-set_io --warn-no-port D13  64
-set_io --warn-no-port D12  63
-set_io --warn-no-port D11  21
-set_io --warn-no-port D10  22
-set_io --warn-no-port D9   19
-set_io --warn-no-port D8   20
+set_io --warn-no-port D13 64
+set_io --warn-no-port D12 63
+set_io --warn-no-port D11 21
+set_io --warn-no-port D10 22
+set_io --warn-no-port D9  19
+set_io --warn-no-port D8  20
 set_io --warn-no-port D7   9
-set_io --warn-no-port D6   10
+set_io --warn-no-port D6  10
 set_io --warn-no-port D5   7
 set_io --warn-no-port D4   8
 set_io --warn-no-port D3   3
@@ -60,38 +61,38 @@ set_io --warn-no-port D1   1
 set_io --warn-no-port D0   2
 
 # -- In Bottom female header
-set_io --warn-no-port DD0  114
-set_io --warn-no-port DD1  115
-set_io --warn-no-port DD2  116
-set_io --warn-no-port DD3  117
-set_io --warn-no-port DD4  118
-set_io --warn-no-port DD5  119
+set_io --warn-no-port DD0 114
+set_io --warn-no-port DD1 115
+set_io --warn-no-port DD2 116
+set_io --warn-no-port DD3 117
+set_io --warn-no-port DD4 118
+set_io --warn-no-port DD5 119
 
-set_io --warn-no-port SDA  118
-set_io --warn-no-port SCL  119
+set_io --warn-no-port SDA 118
+set_io --warn-no-port SCL 119
 
 # -------------------------- I2C ADC ------------------------------------------
-set_io --warn-no-port ADC_SCL  84  # output
-set_io --warn-no-port ADC_SDA  83
-set_io --warn-no-port ADC_INT  90  # input
+set_io --warn-no-port ADC_SCL 84  # output
+set_io --warn-no-port ADC_SDA 83
+set_io --warn-no-port ADC_INT 90  # input
 
 # -------------------------- SYSTEM CLOCK -------------------------------------
-set_io --warn-no-port CLK  49  # input
+set_io --warn-no-port CLK 49  # input
 
 # -------------------------- FTDI ---------------------------------------------
 # --- FTDI 0:
-set_io --warn-no-port RES   66  # input
-set_io --warn-no-port DONE  65  # output
-set_io --warn-no-port SS    71  # output
-set_io --warn-no-port MISO  68  # input
-set_io --warn-no-port MOSI  67  # output
-set_io --warn-no-port SCK   70  # output
+set_io --warn-no-port RES  66  # input
+set_io --warn-no-port DONE 65  # output
+set_io --warn-no-port SS   71  # output
+set_io --warn-no-port MISO 68  # input
+set_io --warn-no-port MOSI 67  # output
+set_io --warn-no-port SCK  70  # output
 #
 # --- FTDI 1: (Serial port)
-set_io --warn-no-port DCD  47  # output
-set_io --warn-no-port DSR  48  # output
-set_io --warn-no-port DTR  52  # input
-set_io --warn-no-port CTS  56  # output
-set_io --warn-no-port RTS  60  # input
-set_io --warn-no-port TX   61  # output
-set_io --warn-no-port RX   62  # input
+set_io --warn-no-port DCD 47  # output
+set_io --warn-no-port DSR 48  # output
+set_io --warn-no-port DTR 52  # input
+set_io --warn-no-port CTS 56  # output
+set_io --warn-no-port RTS 60  # input
+set_io --warn-no-port TX  61  # output
+set_io --warn-no-port RX  62  # input

app/resources/boards/blackice-ii/info.json

@@ -1,6 +1,6 @@
 {
   "label": "BlackIce II",
-  "datasheet": "https://mystorm.uk/",
+  "datasheet": "https://github.com/mystorm-org/BlackIce-II",
   "interface": "Serial",
   "FPGAResources": {
     "ffs": 7680,