Apio Time

Contents

• Usage
• Description
• Options
• Examples

Usage

apio time [OPTIONS]

Description

Bitstream timing analysis: generates a rpt file with a topological timing analysis report, from a verilog and constraints files

Required package: oss-cad-suite

Options

Flag	Long Flag	Description
-b	--board	Select a specific board
	--fpga	Select a specific FPGA
	--size --type --pack	Select a specific FPGA size, type and pack
-p	--project-dir	Set the target directory for the project.
-v	--verbose	Show the entire output of the command
	--verbose-yosys	Show the yosys output of the command
	--verbose-pnr	Show the pnr output of the command
	--top-module str	Set the top level module (w/o .v ending) for build

Note

All available boards, FPGAs, sizes, types and packs are showed in apio boards

Examples

1. Timing analysis for the leds example

apio time

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