Added the 'apio graph' command which generates a svg graph of the verilog code. #356
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…e.svg file with a visual representation of the verilog code. The graphs are not perfect but useful and educating. Can be improve down the road by auto launching a graphical viewer or by encouraning the yosys team to improve the graphs. E.g. YosysHQ/yosys#4236, or having also a graph of the design after optimization to help with timing improvements.
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Added a new 'apio graph' command which uses yosys to generate, a hardware.svg file with a visual representation of a verilog module. By default it shows the top module and this can be changed with the --top-module flag.
This is the yosys command that generates the graph
https://yosyshq.readthedocs.io/projects/yosys/en/manual-rewrite/cmd/show.html
Caveats
The command requires the graphviz dot command to be in the path. Ideally this can auto installed in future versions of apio.
The command generates the hardware.svg file but doesn't launch automatically a viewer (any web browser would do). Need to find a cross platform way to do that.
The graphs are not perfect, but hopefully will be improved over time. For example per this feature request Please add a flag to generate a simplified graphviz diagram. YosysHQ/yosys#4236 or with additions of post optimization graphs.