Merge pull request #395 from zapta/develop

First installment of consolidating and sharing the command options.

apio/commands/build.py

@@ -8,87 +8,37 @@
 """Main implementation of APIO BUILD command"""
 
 
-from pathlib import Path
 import click
 from apio.managers.scons import SCons
 from apio import util
+from apio.commands import options
 
-# R0801: Similar lines in 2 files
-# pylint: disable=R0801
-# ------------------
-# -- CONSTANTS
-# ------------------
-CMD = "build"  # -- Comand name
-BOARD = "board"  # -- Option
-FPGA = "fpga"  # -- Option
-PACK = "pack"  # -- Option
-TYPE = "type"  # -- Option
-SIZE = "size"  # -- Option
-PROJECT_DIR = "project_dir"  # -- Option
-VERBOSE = "verbose"  # -- Option
-VERBOSE_YOSYS = "verbose_yosys"  # -- Option
-VERBOSE_PNR = "verbose_pnr"  # -- Option
-TOP_MODULE = "top_module"  # -- Option
 
-
-# pylint: disable=R0801
-# R0801: Similar lines in 2 files
-@click.command(CMD, context_settings=util.context_settings())
+@click.command("build", context_settings=util.context_settings())
 @click.pass_context
-@click.option(
-    "-b", f"--{BOARD}", type=str, metavar="str", help="Set the board."
-)
-@click.option(f"--{FPGA}", type=str, metavar="str", help="Set the FPGA.")
-@click.option(
-    f"--{SIZE}", type=str, metavar="str", help="Set the FPGA type (1k/8k)."
-)
-@click.option(
-    f"--{TYPE}", type=str, metavar="str", help="Set the FPGA type (hx/lp)."
-)
-@click.option(
-    f"--{PACK}", type=str, metavar="str", help="Set the FPGA package."
-)
-@click.option(
-    "-p",
-    "--project-dir",
-    type=Path,
-    metavar="str",
-    help="Set the target directory for the project.",
-)
-@click.option(
-    "-v",
-    f"--{VERBOSE}",
-    is_flag=True,
-    help="Show the entire output of the command.",
-)
-@click.option(
-    "--verbose-yosys",
-    is_flag=True,
-    help="Show the yosys output of the command.",
-)
-@click.option(
-    "--verbose-pnr", is_flag=True, help="Show the pnr output of the command."
-)
-@click.option(
-    "--top-module",
-    type=str,
-    metavar="str",
-    help="Set the top level module (w/o .v ending) for build.",
-)
+@options.board
+@options.fpga
+@options.size
+@options.type_
+@options.pack
+@options.project_dir
+@options.verbose
+@options.verbose_yosys
+@options.verbose_pnr
+@options.top_module
 def cli(ctx, **kwargs):
     """Synthesize the bitstream."""
-
     # -- Extract the arguments
-    project_dir = kwargs[PROJECT_DIR]
-    board = kwargs[BOARD]
-    fpga = kwargs[FPGA]
-    pack = kwargs[PACK]
-    _type = kwargs[TYPE]
-    size = kwargs[SIZE]
-    verbose = kwargs[VERBOSE]
-    verbose_yosys = kwargs[VERBOSE_YOSYS]
-    verbose_pnr = kwargs[VERBOSE_PNR]
-    top_module = kwargs[TOP_MODULE]
+    project_dir = kwargs[options.PROJECT_DIR]
+    board = kwargs[options.BOARD]
+    fpga = kwargs[options.FPGA]
+    pack = kwargs[options.PACK]
+    _type = kwargs[options.TYPE]
+    size = kwargs[options.SIZE]
+    verbose = kwargs[options.VERBOSE]
+    verbose_yosys = kwargs[options.VERBOSE_YOSYS]
+    verbose_pnr = kwargs[options.VERBOSE_PNR]
+    top_module = kwargs[options.TOP_MODULE]
 
     # The bitstream is generated from the source files (verilog)
     # by means of the scons tool
@@ -97,6 +47,8 @@ def cli(ctx, **kwargs):
     # -- Create the scons object
     scons = SCons(project_dir)
 
+    # R0801: Similar lines in 2 files
+    # pylint: disable=R0801
     # -- Build the project with the given parameters
     exit_code = scons.build(
         {

apio/commands/options.py

@@ -0,0 +1,102 @@
+# -*- coding: utf-8 -*-
+# -- This file is part of the Apio project
+# -- (C) 2016-2024 FPGAwars
+# -- Authors
+# --  * Jesús Arroyo (2016-2019)
+# --  * Juan Gonzalez (obijuan) (2019-2024)
+# -- Licence GPLv2
+"""Common APIO command options"""
+
+from pathlib import Path
+import click
+
+# APIO command options in alphabetial order.
+# The design is based on the idea here https://stackoverflow.com/a/77732441.
+#
+# Each option is defined by two values:
+# 1. (UPPER CASE) The python key for the option value.
+# 2. (lower_case) The click decoration that defines the option.
+
+# -- Board
+BOARD = "board"
+board = click.option(
+    "-b",
+    "--board",
+    BOARD,
+    type=str,
+    metavar="str",
+    help="Set the board.",
+)
+
+# -- FPGA model.
+FPGA = "fpga"
+fpga = click.option(
+    "--fpga", FPGA, type=str, metavar="str", help="Set the FPGA."
+)
+
+# -- FPGA package.
+PACK = "pack"
+pack = click.option(
+    "--pack", PACK, type=str, metavar="str", help="Set the FPGA package."
+)
+
+# -- Project dir
+PROJECT_DIR = "project_dir"
+project_dir = click.option(
+    "-p",
+    "--project-dir",
+    PROJECT_DIR,
+    type=Path,
+    metavar="str",
+    help="Set the target directory for the project.",
+)
+
+# -- FPGA size.
+SIZE = "size"
+size = click.option(
+    "--size", SIZE, type=str, metavar="str", help="Set the FPGA type (1k/8k)."
+)
+
+# -- Top Verilog module.
+TOP_MODULE = "top_module"
+top_module = click.option(
+    "--top-module",
+    TOP_MODULE,
+    type=str,
+    metavar="str",
+    help="Set the top level module (w/o .v ending) for build.",
+)
+
+# -- FPGA type.
+TYPE = "type"
+type_ = click.option(
+    "--type", TYPE, type=str, metavar="str", help="Set the FPGA type (hx/lp)."
+)
+
+# -- Verbose.
+VERBOSE = "verbose"
+verbose = click.option(
+    "-v",
+    "--verbose",
+    VERBOSE,
+    is_flag=True,
+    help="Show the entire output of the command.",
+)
+
+# -- Verbose place and route.
+VERBOSE_PNR = "verbose_pnr"
+verbose_pnr = click.option(
+    "--verbose-pnr",
+    VERBOSE_PNR,
+    is_flag=True,
+    help="Show the pnr output of the command.",
+)
+
+# -- Verbose Yosys.
+VERBOSE_YOSYS = "verbose_yosys"
+verbose_yosys = click.option(
+    "--verbose-yosys",
+    VERBOSE_YOSYS,
+    is_flag=True,
+    help="Show the yosys output of the command.",
+)