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Merge pull request #405 from zapta/develop
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Fixed extra_args issue with dfu-util programmer
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Obijuan authored Sep 4, 2024
2 parents 094ba00 + 6f3a31e commit 5a598f4
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Showing 5 changed files with 27 additions and 9 deletions.
5 changes: 3 additions & 2 deletions DEVELOPER.md
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Expand Up @@ -12,12 +12,13 @@ make tox

## Running an individual APIO test

Run from the repo root. Replace with the path to the desire test.
Run from the repo root. Replace with the path to the desire test. Running ``pytest`` alone runs all the tests.

```shell
test/code_commands/test_build.py
pytest test/code_commands/test_build.py
```


## Running APIO in a debugger

Set the debugger to run the ``apio_run.py`` main with the regular ``apio`` arguments. Set the project directory ot the project file or use the ``--project_dir`` apio argument to point to the project directory.
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19 changes: 15 additions & 4 deletions apio/managers/scons.py
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Expand Up @@ -254,7 +254,8 @@ def get_programmer(self, board: str, prog: dict) -> str:
* sram: Perform SRAM programming
* flash: Perform Flash programming
* OUTPUT: A string with the command+args to execute
* OUTPUT: A string with the command+args to execute and a ${SOURCE}
placeholder for the bitstream file name.
"""

# -- Return string to create
Expand Down Expand Up @@ -306,9 +307,12 @@ def get_programmer(self, board: str, prog: dict) -> str:
# -- * "${PID}" (optional): USB Product id
# -- * "${FTDI_ID}" (optional): FTDI id
# -- * "${SERIAL_PORT}" (optional): Serial port name
# -- * "${SOURCE}" (required): Bitstream file name.
programmer = self.serialize_programmer(
board_data, prog[SRAM], prog[FLASH]
)
# -- The placeholder for the bitstream file name should always exist.
assert "${SOURCE}" in programmer, programmer

# -- Assign the parameters in the Template string

Expand Down Expand Up @@ -358,7 +362,9 @@ def get_programmer(self, board: str, prog: dict) -> str:
programmer = programmer.replace("${SERIAL_PORT}", device)

# -- Return the Command to execute for uploading the circuit
# -- to the given board
# -- to the given board. Scons will replace ${SOURCE} with the
# -- bitstream file name before executing the command.
assert "${SOURCE}" in programmer, programmer
return programmer

@staticmethod
Expand Down Expand Up @@ -508,8 +514,8 @@ def serialize_programmer(
* "${SERIAL_PORT}" (optional): Serial port name
Example of output strings:
"'tinyprog --pyserial -c ${SERIAL_PORT} --program'"
"'iceprog -d i:0x${VID}:0x${PID}:${FTDI_ID}'"
"'tinyprog --pyserial -c ${SERIAL_PORT} --program ${SOURCE}'"
"'iceprog -d i:0x${VID}:0x${PID}:${FTDI_ID} ${SOURCE}'"
"""

# -- Get the programmer type
Expand All @@ -534,6 +540,11 @@ def serialize_programmer(
if content.get("args"):
programmer += f" {content['args']}"

# -- Mark the expected location of the bitstream file name, before
# -- we appened any arg to the command. Some programmers such as
# -- dfu-util require it immediatly after the "args" string.
programmer += " ${SOURCE}"

# -- Some tools need extra arguments
# -- (like dfu-util for example)
if prog_info.get("extra_args"):
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4 changes: 3 additions & 1 deletion apio/resources/ecp5/SConstruct
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Expand Up @@ -170,7 +170,9 @@ build_target = env.Alias('build', bitstream_target)
AlwaysBuild(build_target)

# -- Upload the bitstream into FPGA
upload_target = env.Alias('upload', bitstream_target, '{0} $SOURCE'.format(PROG))
assert "${SOURCE}" in PROG
programmer = PROG.replace("${SOURCE}", "$SOURCE")
upload_target = env.Alias('upload', bitstream_target)
AlwaysBuild(upload_target)

# -- Target time: calculate the time
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4 changes: 3 additions & 1 deletion apio/resources/gowin/SConstruct
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Expand Up @@ -178,7 +178,9 @@ if(VERBOSE_ALL or VERBOSE_PNR):
AlwaysBuild(asc_target)

# -- Upload the bitstream into FPGA
upload_target = env.Alias('upload', bitstream_target, '{0} $SOURCE'.format(PROG))
assert "${SOURCE}" in PROG
programmer = PROG.replace("${SOURCE}", "$SOURCE")
upload_target = env.Alias('upload', bitstream_target, programmer)
AlwaysBuild(upload_target)

# -- Target time: calculate the time
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4 changes: 3 additions & 1 deletion apio/resources/ice40/SConstruct
Original file line number Diff line number Diff line change
Expand Up @@ -175,7 +175,9 @@ if(VERBOSE_ALL or VERBOSE_PNR):
AlwaysBuild(asc_target)

# -- Upload the bitstream into FPGA
upload_target = env.Alias('upload', bitstream_target, '{0} $SOURCE'.format(PROG))
assert "${SOURCE}" in PROG
programmer = PROG.replace("${SOURCE}", "$SOURCE")
upload_target = env.Alias('upload', bitstream_target, programmer)
AlwaysBuild(upload_target)

# -- Target time: calculate the time
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