Merge branch 'develop' of https://github.com/FPGAwars/apio into develop

FPGAwars · Feb 22, 2024 · 44acbd4 · 44acbd4
2 parents b644a31 + 7c069f7
commit 44acbd4
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Showing 2 changed files with 4 additions and 4 deletions.
diff --git a/apio/resources/ecp5/SConstruct b/apio/resources/ecp5/SConstruct
@@ -199,8 +199,8 @@ AlwaysBuild(upload)
 
 # -- Target time: calculate the time
 rpt = env.Time(config_out)
+AlwaysBuild(rpt)
 t = env.Alias('time', rpt)
-AlwaysBuild(t)
 
 # -- Icarus Verilog builders
 iverilog = Builder(
@@ -231,7 +231,7 @@ AlwaysBuild(verify)
 if 'sim' in COMMAND_LINE_TARGETS: 
     sout = env.IVerilog(SIMULNAME, src_sim)
     vcd_file = env.VCD(sout)
-    waves = env.Alias('sim', vcd_file, 'gtkwave {0} {1}.gtkw'.format(
+    waves = env.Alias('sim', vcd_file, 'gtkwave --rcvar "splash_disable on" {0} {1}.gtkw'.format(
         vcd_file[0], SIMULNAME))
     AlwaysBuild(waves)
 

diff --git a/apio/resources/ice40/SConstruct b/apio/resources/ice40/SConstruct
@@ -204,8 +204,8 @@ AlwaysBuild(upload)
 
 # -- Target time: calculate the time
 rpt = env.Time(asc)
+AlwaysBuild(rpt) 
 t = env.Alias('time', rpt)
-AlwaysBuild(t)
 
 # -- Icarus Verilog builders
 iverilog = Builder(
@@ -236,7 +236,7 @@ AlwaysBuild(verify)
 if 'sim' in COMMAND_LINE_TARGETS: 
     sout = env.IVerilog(SIMULNAME, src_sim)
     vcd_file = env.VCD(sout)
-    waves = env.Alias('sim', vcd_file, 'gtkwave {0} {1}.gtkw'.format(
+    waves = env.Alias('sim', vcd_file, 'gtkwave --rcvar "splash_disable on" {0} {1}.gtkw'.format(
         vcd_file[0], SIMULNAME))
     AlwaysBuild(waves)