Added experimental support for system-verilog. It's still hidden (not…

… mentioned in the documentation) and has a known issue with 'apio graph'. If the user has .sv files in the project, apio prints a warning saying that system-verilog support is still experimetnal.

apio/scons/scons_util.py

@@ -87,11 +87,16 @@ def basename(env: SConsEnvironment, file_name: str) -> str:
     return result
 
 
-def is_verilog_src(env: SConsEnvironment, file_name: str) -> str:
+def is_verilog_src(
+    env: SConsEnvironment, file_name: str, *, include_sv: bool = True
+) -> bool:
     """Given a file name, determine by its extension if it's a verilog source
-    file (testbenches included)."""
+    file (testbenches included).  If include_sv is True, include also
+    system verilog files."""
     _, ext = os.path.splitext(file_name)
-    return ext == ".v"
+    if include_sv:
+        return ext in [".v", ".sv"]
+    return ext in [".v"]
 
 
 def has_testbench_name(env: SConsEnvironment, file_name: str) -> bool:
@@ -506,8 +511,15 @@ def get_source_files(env: SConsEnvironment) -> Tuple[List[str], List[str]]:
     If a .v file has the suffix _tb.v it's is classified st a testbench,
     otherwise as a synthesis file.
     """
-    # -- Get a list of all *.v files in the project dir.
-    files: List[File] = env.Glob("*.v")
+    # -- Get a list of all *.v and .sv files in the project dir.
+    files: List[File] = env.Glob("*.sv")
+    if files:
+        click.secho(
+            "Warning: project contains .sv files, system-verilog support "
+            "is experimental.",
+            fg="yellow",
+        )
+    files = files + env.Glob("*.v")
 
     # Split file names to synth files and testbench file lists
     synth_srcs = []
@@ -654,8 +666,10 @@ def make_iverilog_action(
     escaped_vcd_output_name = vcd_output_name.replace("\\", "\\\\")
 
     # -- Construct the action string.
+    # -- The -g2012 is for system-verilog support and we use it here as an
+    # -- experimental feature.
     action = (
-        "iverilog {0} {1} -o $TARGET {2} {3} {4} {5} {6} $SOURCES"
+        "iverilog -g2012 {0} {1} -o $TARGET {2} {3} {4} {5} {6} $SOURCES"
     ).format(
         ivl_path_param,
         "-v" if verbose else "",

test/scons/test_scons_util.py

@@ -171,18 +171,36 @@ def test_is_verilog_src():
 
     env = _make_test_scons_env()
 
-    # -- Verilog source names
+    # -- Verilog and system-verilog source names, system-verilog included.
     assert is_verilog_src(env, "aaa.v")
     assert is_verilog_src(env, "bbb/aaa.v")
     assert is_verilog_src(env, "bbb\\aaa.v")
     assert is_verilog_src(env, "aaatb.v")
     assert is_verilog_src(env, "aaa_tb.v")
-
-    # -- Non verilog source names.
+    assert is_verilog_src(env, "aaa.sv")
+    assert is_verilog_src(env, "bbb\\aaa.sv")
+    assert is_verilog_src(env, "aaa_tb.sv")
+
+    # -- Verilog and system-verilog source names, system-verilog excluded.
+    assert is_verilog_src(env, "aaa.v", include_sv=False)
+    assert is_verilog_src(env, "bbb/aaa.v", include_sv=False)
+    assert is_verilog_src(env, "bbb\\aaa.v", include_sv=False)
+    assert is_verilog_src(env, "aaatb.v", include_sv=False)
+    assert is_verilog_src(env, "aaa_tb.v", include_sv=False)
+    assert not is_verilog_src(env, "aaa.sv", include_sv=False)
+    assert not is_verilog_src(env, "bbb\\aaa.sv", include_sv=False)
+    assert not is_verilog_src(env, "aaa_tb.sv", include_sv=False)
+
+    # -- Non verilog source names, system-verilog included.
     assert not is_verilog_src(env, "aaatb.vv")
     assert not is_verilog_src(env, "aaatb.V")
     assert not is_verilog_src(env, "aaa_tb.vh")
 
+    # -- Non verilog source names, system-verilog excluded.
+    assert not is_verilog_src(env, "aaatb.vv", include_sv=False)
+    assert not is_verilog_src(env, "aaatb.V", include_sv=False)
+    assert not is_verilog_src(env, "aaa_tb.vh", include_sv=False)
+
 
 def test_env_args():
     """Tests the scons env args retrieval."""