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OpcodeDispatcher: Implement rdpid #3495

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Mar 15, 2024
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OpcodeDispatcher: Implement rdpid #3495

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2 changes: 1 addition & 1 deletion FEXCore/Source/Interface/Core/CPUID.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -694,7 +694,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_07h(uint32_t Leaf) const {
(0 << 19) | // MPX MAWAU
(0 << 20) | // MPX MAWAU
(0 << 21) | // MPX MAWAU
(0 << 22) | // RDPID Read Processor ID
(1 << 22) | // RDPID Read Processor ID
(0 << 23) | // Reserved
(0 << 24) | // Reserved
(0 << 25) | // CLDEMOTE
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6 changes: 6 additions & 0 deletions FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
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Expand Up @@ -5426,6 +5426,10 @@ void OpDispatchBuilder::RDTSCPOp(OpcodeArgs) {
StoreGPRRegister(X86State::REG_RDX, Counter.CounterHigh);
}

void OpDispatchBuilder::RDPIDOp(OpcodeArgs) {
StoreResult(GPRClass, Op, _ProcessorID(), -1);
}

void OpDispatchBuilder::CRC32(OpcodeArgs) {
const uint8_t GPRSize = CTX->GetGPRSize();

Expand Down Expand Up @@ -6573,6 +6577,8 @@ constexpr uint16_t PF_F2 = 3;
{OPD(FEXCore::X86Tables::TYPE_GROUP_9, PF_66, 1), 1, &OpDispatchBuilder::CMPXCHGPairOp},
{OPD(FEXCore::X86Tables::TYPE_GROUP_9, PF_F2, 1), 1, &OpDispatchBuilder::CMPXCHGPairOp},

{OPD(FEXCore::X86Tables::TYPE_GROUP_9, PF_F3, 7), 1, &OpDispatchBuilder::RDPIDOp},

// GROUP 12
{OPD(FEXCore::X86Tables::TYPE_GROUP_12, PF_NONE, 2), 1, &OpDispatchBuilder::PSRLI<2>},
{OPD(FEXCore::X86Tables::TYPE_GROUP_12, PF_NONE, 4), 1, &OpDispatchBuilder::PSRAIOp<2>},
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1 change: 1 addition & 0 deletions FEXCore/Source/Interface/Core/OpcodeDispatcher.h
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Expand Up @@ -867,6 +867,7 @@ friend class FEXCore::IR::PassManager;
void StoreFenceOrCLFlush(OpcodeArgs);
void CLZeroOp(OpcodeArgs);
void RDTSCPOp(OpcodeArgs);
void RDPIDOp(OpcodeArgs);

void PSADBW(OpcodeArgs);

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2 changes: 1 addition & 1 deletion FEXCore/Source/Interface/Core/X86Tables/SecondaryGroupTables.cpp
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Expand Up @@ -162,7 +162,7 @@ std::array<X86InstInfo, MAX_INST_SECOND_GROUP_TABLE_SIZE> SecondInstGroupOps = [
{OPD(TYPE_GROUP_9, PF_F3, 4), 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
{OPD(TYPE_GROUP_9, PF_F3, 5), 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
{OPD(TYPE_GROUP_9, PF_F3, 6), 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
{OPD(TYPE_GROUP_9, PF_F3, 7), 1, X86InstInfo{"RDPID", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
{OPD(TYPE_GROUP_9, PF_F3, 7), 1, X86InstInfo{"RDPID", TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SF_MOD_REG_ONLY, 0, nullptr}},

{OPD(TYPE_GROUP_9, PF_66, 0), 1, X86InstInfo{"", TYPE_INVALID, FLAGS_NONE, 0, nullptr}},
{OPD(TYPE_GROUP_9, PF_66, 1), 1, X86InstInfo{"CMPXCHG8B/16B", TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_SF_MOD_MEM_ONLY, 0, nullptr}},
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3 changes: 3 additions & 0 deletions unittests/ASM/Disabled_Tests_Simulator
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Expand Up @@ -86,3 +86,6 @@ Test_VEX/vroundss.asm

# Simulator doesn't support cycle counter reading
Test_TwoByte/0F_31.asm

# Simulator doesn't support executing a syscall
Test_Secondary/09_F3_07.asm
17 changes: 17 additions & 0 deletions unittests/ASM/Secondary/09_F3_07.asm
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@@ -0,0 +1,17 @@
%ifdef CONFIG
{
"RegData": {
"RAX": "1"
}
}
%endif

mov rax, 0
mov rbx, 0x4142434445464748
mov rcx, 0x4142434445464748
rdpid ebx

cmp rbx, rcx
setne al

hlt
48 changes: 48 additions & 0 deletions unittests/InstructionCountCI/SecondaryGroup.json
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Expand Up @@ -921,6 +921,54 @@
"msr nzcv, x20"
]
},
"rdpid eax": {
"ExpectedInstructionCount": 18,
"Comment": "GROUP9 0xF3 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
"mrs x0, nzcv",
"str w0, [x28, #728]",
"str x8, [x28, #40]",
"mov w0, #0x100",
"str x0, [x28, #1056]",
"sub sp, sp, #0x10 (16)",
"mov w8, #0xa8",
"mov x0, sp",
"add x1, sp, #0x4 (4)",
"svc #0x0",
"ldp w0, w1, [sp]",
"sub sp, sp, #0x10 (16)",
"ldr w8, [x28, #728]",
"msr nzcv, x8",
"ldr x8, [x28, #40]",
"str xzr, [x28, #1056]",
"orr x20, x0, x1, lsl #12",
"mov w4, w20"
]
},
"rdpid rax": {
"ExpectedInstructionCount": 18,
"Comment": "GROUP9 0xF3 0x0F 0xC7 /7",
"ExpectedArm64ASM": [
"mrs x0, nzcv",
"str w0, [x28, #728]",
"str x8, [x28, #40]",
"mov w0, #0x100",
"str x0, [x28, #1056]",
"sub sp, sp, #0x10 (16)",
"mov w8, #0xa8",
"mov x0, sp",
"add x1, sp, #0x4 (4)",
"svc #0x0",
"ldp w0, w1, [sp]",
"sub sp, sp, #0x10 (16)",
"ldr w8, [x28, #728]",
"msr nzcv, x8",
"ldr x8, [x28, #40]",
"str xzr, [x28, #1056]",
"orr x20, x0, x1, lsl #12",
"mov w4, w20"
]
},
"psrlw mm0, 0": {
"ExpectedInstructionCount": 0,
"Type": "MMX",
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