Skip to content

Commit

Permalink
Merge pull request #1304 from Sonicadvance1/explicit_x87_abi
Browse files Browse the repository at this point in the history 
Arm64: Be more explicit about x87 ABI usage
  • Loading branch information
@Sonicadvance1
Sonicadvance1 authored Oct 12, 2021
2 parents 6cd73a6 + cffd10d commit bdc66a3
Showing 1 changed file with 17 additions and 12 deletions.
29 changes: 17 additions & 12 deletions External/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -55,7 +55,7 @@ void Arm64JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {

PushDynamicRegsAndLR();

mov(w0, GetReg<RA_32>(IROp->Args[0].ID()));
uxtw(w0, GetReg<RA_32>(IROp->Args[0].ID()));
LoadConstant(x1, (uintptr_t)Info.fn);

blr(x1);
Expand Down Expand Up @@ -112,7 +112,12 @@ void Arm64JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {

PushDynamicRegsAndLR();

mov(w0, GetReg<RA_32>(IROp->Args[0].ID()));
if (Info.ABI == FABI_F80_I16) {
uxtw(w0, GetReg<RA_32>(IROp->Args[0].ID()));
}
else {
mov(w0, GetReg<RA_32>(IROp->Args[0].ID()));
}
LoadConstant(x1, (uintptr_t)Info.fn);

blr(x1);
Expand All @@ -133,7 +138,7 @@ void Arm64JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
PushDynamicRegsAndLR();

umov(x0, GetSrc(IROp->Args[0].ID()).V2D(), 0);
umov(x1, GetSrc(IROp->Args[0].ID()).V2D(), 1);
umov(x1, GetSrc(IROp->Args[0].ID()).V8H(), 4);

LoadConstant(x2, (uintptr_t)Info.fn);

Expand All @@ -153,7 +158,7 @@ void Arm64JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
PushDynamicRegsAndLR();

umov(x0, GetSrc(IROp->Args[0].ID()).V2D(), 0);
umov(x1, GetSrc(IROp->Args[0].ID()).V2D(), 1);
umov(x1, GetSrc(IROp->Args[0].ID()).V8H(), 4);

LoadConstant(x2, (uintptr_t)Info.fn);

Expand All @@ -173,7 +178,7 @@ void Arm64JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
PushDynamicRegsAndLR();

umov(x0, GetSrc(IROp->Args[0].ID()).V2D(), 0);
umov(x1, GetSrc(IROp->Args[0].ID()).V2D(), 1);
umov(x1, GetSrc(IROp->Args[0].ID()).V8H(), 4);

LoadConstant(x2, (uintptr_t)Info.fn);

Expand All @@ -192,7 +197,7 @@ void Arm64JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
PushDynamicRegsAndLR();

umov(x0, GetSrc(IROp->Args[0].ID()).V2D(), 0);
umov(x1, GetSrc(IROp->Args[0].ID()).V2D(), 1);
umov(x1, GetSrc(IROp->Args[0].ID()).V8H(), 4);

LoadConstant(x2, (uintptr_t)Info.fn);

Expand All @@ -211,7 +216,7 @@ void Arm64JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
PushDynamicRegsAndLR();

umov(x0, GetSrc(IROp->Args[0].ID()).V2D(), 0);
umov(x1, GetSrc(IROp->Args[0].ID()).V2D(), 1);
umov(x1, GetSrc(IROp->Args[0].ID()).V8H(), 4);

LoadConstant(x2, (uintptr_t)Info.fn);

Expand All @@ -230,10 +235,10 @@ void Arm64JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
PushDynamicRegsAndLR();

umov(x0, GetSrc(IROp->Args[0].ID()).V2D(), 0);
umov(x1, GetSrc(IROp->Args[0].ID()).V2D(), 1);
umov(x1, GetSrc(IROp->Args[0].ID()).V8H(), 4);

umov(x2, GetSrc(IROp->Args[1].ID()).V2D(), 0);
umov(x3, GetSrc(IROp->Args[1].ID()).V2D(), 1);
umov(x3, GetSrc(IROp->Args[1].ID()).V8H(), 4);

LoadConstant(x4, (uintptr_t)Info.fn);

Expand All @@ -252,7 +257,7 @@ void Arm64JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
PushDynamicRegsAndLR();

umov(x0, GetSrc(IROp->Args[0].ID()).V2D(), 0);
umov(x1, GetSrc(IROp->Args[0].ID()).V2D(), 1);
umov(x1, GetSrc(IROp->Args[0].ID()).V8H(), 4);

LoadConstant(x2, (uintptr_t)Info.fn);

Expand All @@ -273,10 +278,10 @@ void Arm64JITCore::Op_Unhandled(FEXCore::IR::IROp_Header *IROp, uint32_t Node) {
PushDynamicRegsAndLR();

umov(x0, GetSrc(IROp->Args[0].ID()).V2D(), 0);
umov(x1, GetSrc(IROp->Args[0].ID()).V2D(), 1);
umov(x1, GetSrc(IROp->Args[0].ID()).V8H(), 4);

umov(x2, GetSrc(IROp->Args[1].ID()).V2D(), 0);
umov(x3, GetSrc(IROp->Args[1].ID()).V2D(), 1);
umov(x3, GetSrc(IROp->Args[1].ID()).V8H(), 4);

LoadConstant(x4, (uintptr_t)Info.fn);

Expand Down

0 comments on commit bdc66a3

Please sign in to comment.