Merge pull request #1210 from Sonicadvance1/proton_6.3_fixes

Proton 6.3 32-bit fixes
FEX-Emu · Aug 23, 2021 · 8099dfc · 8099dfc
2 parents 926ddab + 02c10b9
commit 8099dfc
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Showing 6 changed files with 591 additions and 11 deletions.
diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
@@ -1549,7 +1549,14 @@ void OpDispatchBuilder::MOVSegOp(OpcodeArgs) {
         DecodeFailure = true;
         return;
     }
-    StoreResult(GPRClass, Op, Segment, -1);
+    if (DestIsMem(Op)) {
+      // If the destination is memory then we always store 16-bits only
+      StoreResult_WithOpSize(GPRClass, Op, Op->Dest, Segment, 2, -1);
+    }
+    else {
+      // If the destination is a GPR then we follow register storing rules
+      StoreResult(GPRClass, Op, Segment, -1);
+    }
   }
 }
 

diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
@@ -1303,14 +1303,14 @@ void OpDispatchBuilder::FXSaveOp(OpcodeArgs) {
   //  240 | XMM5
   //  256 | XMM6
   //  272 | XMM7
-  //  288 | XMM8
-  //  304 | XMM9
-  //  320 | XMM10
-  //  336 | XMM11
-  //  352 | XMM12
-  //  368 | XMM13
-  //  384 | XMM14
-  //  400 | XMM15
+  //  288 | 64BitMode ? <R> : XMM8
+  //  304 | 64BitMode ? <R> : XMM9
+  //  320 | 64BitMode ? <R> : XMM10
+  //  336 | 64BitMode ? <R> : XMM11
+  //  352 | 64BitMode ? <R> : XMM12
+  //  368 | 64BitMode ? <R> : XMM13
+  //  384 | 64BitMode ? <R> : XMM14
+  //  400 | 64BitMode ? <R> : XMM15
   //  416 | <R>
   //  432 | <R>
   //  448 | <R>
@@ -1335,7 +1335,9 @@ void OpDispatchBuilder::FXSaveOp(OpcodeArgs) {
 
     _StoreMem(FPRClass, 16, MemLocation, MMReg, 16);
   }
-  for (unsigned i = 0; i < 16; ++i) {
+  unsigned NumRegs = CTX->Config.Is64BitMode ? 16 : 8;
+
+  for (unsigned i = 0; i < NumRegs; ++i) {
     OrderedNode *XMMReg = _LoadContext(16, offsetof(FEXCore::Core::CPUState, xmm[i]), FPRClass);
     OrderedNode *MemLocation = _Add(Mem, _Constant(i * 16 + 160));
 
@@ -1382,7 +1384,9 @@ void OpDispatchBuilder::FXRStoreOp(OpcodeArgs) {
     auto MMReg = _LoadMem(FPRClass, 16, MemLocation, 16);
     _StoreContext(FPRClass, 16, offsetof(FEXCore::Core::CPUState, mm[i]), MMReg);
   }
-  for (unsigned i = 0; i < 16; ++i) {
+  unsigned NumRegs = CTX->Config.Is64BitMode ? 16 : 8;
+
+  for (unsigned i = 0; i < NumRegs; ++i) {
     OrderedNode *MemLocation = _Add(Mem, _Constant(i * 16 + 160));
     auto XMMReg = _LoadMem(FPRClass, 16, MemLocation, 16);
     _StoreContext(FPRClass, 16, offsetof(FEXCore::Core::CPUState, xmm[i]), XMMReg);

diff --git a/unittests/32Bit_ASM/Primary/Primary_8C.asm b/unittests/32Bit_ASM/Primary/Primary_8C.asm
@@ -0,0 +1,37 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0xFFFF0033",
+    "RBX": "0xFFFF0033",
+    "RCX": "0xFFFF0033"
+  },
+  "Mode": "32BIT"
+}
+%endif
+
+mov eax, 0x33
+mov gs, ax
+mov fs, ax
+mov es, ax
+
+mov eax, 0xFFFFFFFF
+mov ebp, 0xe0000000
+
+; Store 32bits of data
+mov dword [ebp + 0], eax
+mov dword [ebp + 4], eax
+mov dword [ebp + 8], eax
+
+; Ensure that the segment store only writes 16-bits
+mov word [ebp + 0], gs
+mov word [ebp + 4], fs
+mov word [ebp + 8], es
+
+mov eax, 0
+mov ebx, 0
+mov ecx, 0
+mov eax, dword [ebp + 0]
+mov ebx, dword [ebp + 4]
+mov ecx, dword [ebp + 8]
+
+hlt
diff --git a/unittests/32Bit_ASM/Primary/Primary_8C_2.asm b/unittests/32Bit_ASM/Primary/Primary_8C_2.asm
@@ -0,0 +1,27 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0xFFFF0033",
+    "RBX": "0x33",
+    "RCX": "0x33"
+  },
+  "Mode": "32BIT"
+}
+%endif
+
+mov eax, 0x33
+mov gs, ax
+mov fs, ax
+mov es, ax
+
+mov eax, 0xFFFFFFFF
+mov ebx, 0xFFFFFFFF
+mov ecx, 0xFFFFFFFF
+
+; 16-bit insert
+mov ax, gs
+; 32-bit zext
+mov ebx, fs
+mov ecx, es
+
+hlt