Merge pull request #3764 from Sonicadvance1/rorx_masking

BMI2: Ensure rorx immediate masks by operation size correctly.
FEX-Emu · Jun 26, 2024 · 54a1f7d · 54a1f7d
2 parents 7d939a3 + a515061
commit 54a1f7d
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Showing 2 changed files with 11 additions and 2 deletions.
diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
@@ -1883,9 +1883,9 @@ void OpDispatchBuilder::BZHI(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::RORX(OpcodeArgs) {
-  const auto Amount = Op->Src[1].Literal();
   const auto SrcSize = GetSrcSize(Op);
   const auto SrcSizeBits = SrcSize * 8;
+  const auto Amount = Op->Src[1].Literal() & (SrcSizeBits - 1);
   const auto GPRSize = CTX->GetGPRSize();
 
   const auto DoRotation = Amount != 0 && Amount < SrcSizeBits;

diff --git a/unittests/ASM/VEX/rorx.asm b/unittests/ASM/VEX/rorx.asm
@@ -7,7 +7,10 @@
       "RDX": "0x80000000",
       "RSI": "0xFF",
       "RDI": "0xF000000F",
-      "R8":  "0"
+      "R8":  "0",
+      "R9": "0x0000000045464748",
+      "R10": "0x0000000022a323a4"
+
   },
   "HostFeatures": ["BMI2"]
 }
@@ -41,4 +44,10 @@ rorx edi, edi, 32
 mov r8, 0xFFFFFFFF00000000
 rorx r8d, r8d, 0
 
+mov r9, 0x4142434445464748
+rorx r9d, r9d, 0xE0
+
+mov r10, 0x4142434445464748
+rorx r10d, r10d, 0xE1
+
 hlt