Passes: Make use of NodeID alias where applicable

Unifies the passes so that they're using the NodeID alias as well.

External/FEXCore/Source/Interface/IR/IRDumper.cpp

@@ -199,9 +199,9 @@ void Dump(std::stringstream *out, IRListView const* IR, IR::RegisterAllocationDa
 
     ++CurrentIndent;
     for (auto [CodeNode, IROp] : IR->GetCode(BlockNode)) {
-      uint32_t ID = IR->GetID(CodeNode);
+      const auto ID = IR->GetID(CodeNode);
+      const auto Name = FEXCore::IR::GetName(IROp->Op);
 
-      auto Name = FEXCore::IR::GetName(IROp->Op);
       bool Skip{};
       switch (IROp->Op) {
         case IR::OP_PHIVALUE:

External/FEXCore/Source/Interface/IR/Passes/DeadContextStoreElimination.cpp

@@ -337,7 +337,7 @@ class RCLSE final : public FEXCore::IR::Pass {
   std::unique_ptr<FEXCore::IR::Pass> DCE;
 
   ContextInfo ClassifiedStruct;
-  std::unordered_map<FEXCore::IR::OrderedNodeWrapper::NodeOffsetType, BlockInfo> OffsetToBlockMap;
+  std::unordered_map<FEXCore::IR::NodeID, BlockInfo> OffsetToBlockMap;
 
   ContextMemberInfo *FindMemberInfo(ContextInfo *ClassifiedInfo, uint32_t Offset, uint8_t Size);
   ContextMemberInfo *RecordAccess(ContextMemberInfo *Info, FEXCore::IR::RegisterClassType RegClass, uint32_t Offset, uint8_t Size, LastAccessType AccessType, FEXCore::IR::OrderedNode *Node, FEXCore::IR::OrderedNode *StoreNode = nullptr);

External/FEXCore/Source/Interface/IR/Passes/IRCompaction.cpp

@@ -24,7 +24,7 @@ namespace FEXCore::IR {
 
 // struct to avoid zero-initialization
 struct RemapNode {
-  IR::OrderedNodeWrapper::NodeOffsetType NodeID;
+  IR::NodeID NodeID;
 };
 
 static_assert(sizeof(RemapNode) == 4);
@@ -172,9 +172,9 @@ bool IRCompaction::Run(IREmitter *IREmit) {
         // Now that we have the op copied over, we need to modify SSA values to point to the new correct locations
         // This doesn't use IR::GetArgs(Op) because we need to remap all SSA nodes
         // Including ones that we don't RA
-        uint8_t NumArgs = LocalIROp->NumArgs;
+        const uint8_t NumArgs = LocalIROp->NumArgs;
         for (uint8_t i = 0; i < NumArgs; ++i) {
-          uint32_t OldArg = LocalIROp->Args[i].ID();
+          const auto OldArg = LocalIROp->Args[i].ID();
           #ifndef NDEBUG
             LOGMAN_THROW_A_FMT(OldToNewRemap[OldArg].NodeID != ~0U, "Tried remapping unfound node %ssa{}", OldArg);
           #endif

External/FEXCore/Source/Interface/IR/Passes/IRValidation.cpp

@@ -69,15 +69,12 @@ bool IRValidation::Run(IREmitter *IREmit) {
       EntryBlock = BlockNode;
     }
 
-    uint32_t BlockID = CurrentIR.GetID(BlockNode);
-
+    const auto BlockID = CurrentIR.GetID(BlockNode);
     BlockInfo *CurrentBlock = &OffsetToBlockMap.try_emplace(BlockID).first->second;
 
-
     for (auto [CodeNode, IROp] : CurrentIR.GetCode(BlockNode)) {
-      uint32_t ID = CurrentIR.GetID(CodeNode);
-
-      uint8_t OpSize = IROp->Size;
+      const auto ID = CurrentIR.GetID(CodeNode);
+      const uint8_t OpSize = IROp->Size;
 
       if (IROp->HasDest) {
         HadError |= OpSize == 0;

External/FEXCore/Source/Interface/IR/Passes/IRValidation.h

@@ -24,7 +24,7 @@ class IRValidation final : public FEXCore::IR::Pass {
 
   BitSet<uint64_t> NodeIsLive;
   OrderedNode *EntryBlock;
-  std::unordered_map<IR::OrderedNodeWrapper::NodeOffsetType, BlockInfo> OffsetToBlockMap;
+  std::unordered_map<IR::NodeID, BlockInfo> OffsetToBlockMap;
   size_t MaxNodes{};
 
   friend class RAValidation;

External/FEXCore/Source/Interface/IR/Passes/RAValidation.cpp

@@ -31,7 +31,7 @@ struct RegState {
   // These assumptions were all true for the state of the arm64 and x86 jits at the time this was written
 
   // Mark a physical register as containing a SSA id
-  bool Set(PhysicalRegister Reg, uint32_t ssa) {
+  bool Set(PhysicalRegister Reg, IR::NodeID ssa) {
     LOGMAN_THROW_A_FMT(ssa != 0, "RegState assumes ssa0 will be the block header and never assigned to a register");
 
     // PhyscialRegisters aren't fully mapped until assembly emission
@@ -96,12 +96,12 @@ struct RegState {
 
 
   // Mark a spill slot as containing a SSA id
-  void Spill(uint32_t SpillSlot, uint32_t ssa) {
+  void Spill(uint32_t SpillSlot, IR::NodeID ssa) {
     Spills[SpillSlot] = ssa;
   }
 
   // Consume (and return) the SSA id currently in a spill slot
-  uint32_t Unspill(uint32_t SpillSlot) {
+  IR::NodeID Unspill(uint32_t SpillSlot) {
     if (Spills.contains(SpillSlot)) {
       uint32_t Value = Spills[SpillSlot];
       Spills.erase(SpillSlot);
@@ -165,10 +165,10 @@ struct RegState {
   }
 
 private:
-  std::array<uint32_t, 32> GPRs = {};
-  std::array<uint32_t, 32> FPRs = {};
+  std::array<IR::NodeID, 32> GPRs = {};
+  std::array<IR::NodeID, 32> FPRs = {};
 
-  std::unordered_map<uint32_t, uint32_t> Spills;
+  std::unordered_map<uint32_t, IR::NodeID> Spills;
 
 public:
   uint32_t Version{}; // Used to force regeneration of RegStates after following backward edges
@@ -181,7 +181,7 @@ class RAValidation final : public FEXCore::IR::Pass {
 
 private:
   // Holds the calculated RegState at the exit of each block
-  std::unordered_map<uint32_t, RegState> BlockExitState;
+  std::unordered_map<IR::NodeID, RegState> BlockExitState;
 
   // A queue of blocks we need to visit (or revisit)
   std::deque<OrderedNode*> BlocksToVisit;
@@ -213,10 +213,10 @@ bool RAValidation::Run(IREmitter *IREmit) {
   while (!BlocksToVisit.empty())
   {
     auto BlockNode = BlocksToVisit.front();
-    uint32_t BlockID = CurrentIR.GetID(BlockNode);
+    const auto BlockID = CurrentIR.GetID(BlockNode);
     auto& BlockInfo = OffsetToBlockMap[BlockID];
 
-    auto IsFowardsEdge = [&] (uint32_t PredecessorID) {
+    const auto IsFowardsEdge = [&](IR::NodeID PredecessorID) {
       // Blocks are sorted in FEXes IR, so backwards edges always go to a lower (or equal) Block ID
       return PredecessorID < BlockID;
     };
@@ -226,8 +226,8 @@ bool RAValidation::Run(IREmitter *IREmit) {
     bool MissingPredecessor = false;
 
     for (auto Predecessor : BlockInfo.Predecessors) {
-      auto PredecessorID = CurrentIR.GetID(Predecessor);
-      bool HaveState = BlockExitState.contains(PredecessorID) && BlockExitState[PredecessorID].Version == CurrentVersion;
+      const auto PredecessorID = CurrentIR.GetID(Predecessor);
+      const bool HaveState = BlockExitState.contains(PredecessorID) && BlockExitState[PredecessorID].Version == CurrentVersion;
 
       if (IsFowardsEdge(PredecessorID) && !HaveState) {
         // We are probably about to visit this node anyway, remove it
@@ -252,7 +252,7 @@ bool RAValidation::Run(IREmitter *IREmit) {
 
     // Second, we need to determine the register status as of Block entry
     auto BlockOp = CurrentIR.GetOp<IROp_CodeBlock>(BlockNode);
-    uint32_t FirstSSA = BlockOp->Begin.ID();
+    const auto FirstSSA = BlockOp->Begin.ID();
 
     auto& BlockRegState = BlockExitState.try_emplace(BlockID).first->second;
     bool EmptyRegState = true;
@@ -281,9 +281,9 @@ bool RAValidation::Run(IREmitter *IREmit) {
     // Thrid, we need to iterate over all IR ops in the block
 
     for (auto [CodeNode, IROp] : CurrentIR.GetCode(BlockNode)) {
-      uint32_t ID = CurrentIR.GetID(CodeNode);
+      const auto ID = CurrentIR.GetID(CodeNode);
 
-      auto CheckArg = [&] (uint32_t i, OrderedNodeWrapper Arg) {
+      const auto CheckArg = [&](uint32_t i, OrderedNodeWrapper Arg) {
         const auto PhyReg = RAData->GetNodeRegister(Arg.ID());
 
         if (PhyReg.IsInvalid())
@@ -330,8 +330,8 @@ bool RAValidation::Run(IREmitter *IREmit) {
 
       case OP_FILLREGISTER: {
         auto FillRegister = IROp->C<IROp_FillRegister>();
-        uint32_t ExpectedValue = FillRegister->OriginalValue.ID();
-        uint32_t Value = BlockRegState.Unspill(FillRegister->Slot);
+        const auto ExpectedValue = FillRegister->OriginalValue.ID();
+        const auto Value = BlockRegState.Unspill(FillRegister->Slot);
 
         // TODO: This only proves that the Spill has a consistent SSA value
         //       In the future we need to prove it contains the correct SSA value
@@ -400,14 +400,14 @@ bool RAValidation::Run(IREmitter *IREmit) {
       HadError |= true;
 
       for (auto [BlockNode, BlockHeader] : CurrentIR.GetBlocks()) {
-        uint32_t BlockID = CurrentIR.GetID(BlockNode);
-        auto& BlockInfo = OffsetToBlockMap[BlockID];
+        const auto BlockID = CurrentIR.GetID(BlockNode);
+        const auto& BlockInfo = OffsetToBlockMap[BlockID];
 
         Errors << fmt::format("Block {}\n\tPredecessors: ", BlockID);
 
         for (auto Predecessor : BlockInfo.Predecessors) {
-          auto PredecessorID = CurrentIR.GetID(Predecessor);
-          bool FowardsEdge = PredecessorID < BlockID;
+          const auto PredecessorID = CurrentIR.GetID(Predecessor);
+          const bool FowardsEdge = PredecessorID < BlockID;
           if (!FowardsEdge) {
             Errors << "(Backwards): ";
           }
@@ -417,8 +417,8 @@ bool RAValidation::Run(IREmitter *IREmit) {
         Errors << "\n\tSuccessors: ";
 
         for (auto Successor : BlockInfo.Successors) {
-          auto SuccessorID = CurrentIR.GetID(Successor);
-          bool FowardsEdge = SuccessorID > BlockID;
+          const auto SuccessorID = CurrentIR.GetID(Successor);
+          const bool FowardsEdge = SuccessorID > BlockID;
 
           if (!FowardsEdge) {
             Errors << "(Backwards): ";