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EmJunaid/README.md
  • 👋 Hi, I’m Muhammad Junaid.
  • 👀 I’m interested in Machine Learning, ASIC Design and SoC.
  • 🌱 I’m a final year student of EE doing specialization in embedded systems and mainly focusing on RISC-V ISA and VLSI.
  • 💞️ I have recently worked on some computer vision related tasks such as object detection and person Identification and have also worked on 5 stage pipellined processor and working on it to integrate different modules with it such as UART, SPI, Ram etc.
  • 📫 You can reach me through writing an email to me at: [email protected] or [email protected]

Popular repositories Loading

  1. RISC-V-32I-5-stage-Pipeline-Processor RISC-V-32I-5-stage-Pipeline-Processor Public

    5 stage pipeline implementation of RISC-V 32I Processor.

    Verilog 7 2

  2. Risc-V-32I-Single-Cycle-Processor Risc-V-32I-Single-Cycle-Processor Public

    Implementation of RiscV single cycle architecture consisting of six base instructions (R, I, B, S, J, U).

    Verilog 2

  3. EmJunaid EmJunaid Public

    Config files for my GitHub profile.

  4. CSRs_Implementation CSRs_Implementation Public

    Verilog

  5. Database Database Public

  6. Matrix-Multiplier-FSM Matrix-Multiplier-FSM Public

    Takes two 10x10 matrices stored in two different 1rw memories and calculate result through repetitive addition and store resultant matrix C back in 1r1w memory.

    Verilog