i#2626 AArch64: Add missing MSR variants

Extends INSTR_CREATE_msr to be able to encode the immediate variant of the MSR instruction: MSR <pstatefield>, #<imm> Adds codec support for some missing pstatefields, and adds missing IR and disassembly tests for MSR. Issue: #2626
DynamoRIO · Jun 6, 2024 · d19fb7b · d19fb7b
1 parent d7955d5
commit d19fb7b
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Showing 5 changed files with 237 additions and 130 deletions.
diff --git a/core/ir/aarch64/codec.c b/core/ir/aarch64/codec.c
@@ -3752,18 +3752,25 @@ encode_opnd_z3_s_16(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_o
 
 /* pstate: decode pstate from 5-7 and 16-18 */
 
+#define PSTATE_FIELDS(S)     \
+    S(UAO, 0b000, 0b011)     \
+    S(PAN, 0b000, 0b100)     \
+    S(SPSEL, 0b000, 0b101)   \
+    S(SSBS, 0b011, 0b001)    \
+    S(DIT, 0b011, 0b010)     \
+    S(TCO, 0b011, 0b100)     \
+    S(DAIFSET, 0b011, 0b110) \
+    S(DAIFCLR, 0b011, 0b111)
+
 static inline bool
 decode_opnd_pstate(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
 {
-    int lower = enc >> 5 & 0b111;
-    int upper = enc >> 16 & 0b111;
-    int both = lower | upper << 3;
-
     reg_t pstate;
-    switch (both) {
-    case 0b000101: pstate = DR_REG_SPSEL; break;
-    case 0b011110: pstate = DR_REG_DAIFSET; break;
-    case 0b011111: pstate = DR_REG_DAIFCLR; break;
+    switch (enc) {
+#define CASE(name, op1, op2) \
+    case (op1 << 16) | (op2 << 5): pstate = DR_REG_##name; break;
+        PSTATE_FIELDS(CASE)
+#undef CASE
     default: return false;
     }
 
@@ -3774,29 +3781,16 @@ decode_opnd_pstate(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
 static inline bool
 encode_opnd_pstate(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_out)
 {
-    int upper, lower;
     if (!opnd_is_reg(opnd))
         return false;
 
     switch (opnd_get_reg(opnd)) {
-    case DR_REG_SPSEL:
-        upper = 0b000;
-        lower = 0b101;
-        break;
-    case DR_REG_DAIFSET:
-        upper = 0b011;
-        lower = 0b110;
-        break;
-    case DR_REG_DAIFCLR:
-        upper = 0b011;
-        lower = 0b111;
-        break;
-    default: return false;
+#define CASE(name, op1, op2) \
+    case DR_REG_##name: *enc_out = (op1) << 16 | (op2) << 5; return true;
+        PSTATE_FIELDS(CASE)
+#undef CASE
     }
-
-    *enc_out = upper << 16 | lower << 5;
-
-    return true;
+    return false;
 }
 
 /* fpimm8: immediate operand for SIMD fmov */

diff --git a/core/ir/aarch64/codec_v80.txt b/core/ir/aarch64/codec_v80.txt
@@ -1,5 +1,5 @@
 # **********************************************************
-# Copyright (c) 2016-2022 ARM Limited. All rights reserved.
+# Copyright (c) 2016-2024 ARM Limited. All rights reserved.
 # **********************************************************
 
 # Redistribution and use in source and binary forms, with or without
@@ -690,9 +690,13 @@ x0011011000xxxxx0xxxxxxxxxxxxxxx  n   311  BASE       madd            wx0 : wx5
 110100101xxxxxxxxxxxxxxxxxxxxxxx  n   317  BASE       movz             x0 : imm16 lsl imm16sh
 110101010011xxxxxxxxxxxxxxxxxxxx  er  318  BASE        mrs             x0 : sysreg
 110101010001xxxxxxxxxxxxxxxxxxxx  ew  319  BASE        msr            msr
+11010101000000000100xxxx01111111  ew  319  BASE        msr                : pstate imm4
+11010101000000000100xxxx10011111  ew  319  BASE        msr                : pstate imm4
 11010101000000000100xxxx10111111  ew  319  BASE        msr                : pstate imm4
-11010101000000110100xxxx11011111  ew  319  BASE        msr                : pstate imm4
-11010101000000110100xxxx11111111  ew  319  BASE        msr                : pstate imm4
+11010101000000110100xxxx00011111  ew  319  BASE        msr                : pstate imm4
+11010101000000110100xxxx00111111  ew  319  BASE        msr                : pstate imm4
+11010101000000110100xxxx01011111  ew  319  BASE        msr                : pstate imm4
+11010101000000110100xxxx1xx11111  ew  319  BASE        msr                : pstate imm4
 x0011011000xxxxx1xxxxxxxxxxxxxxx  n   320  BASE       msub            wx0 : wx5 wx16 wx10
 0x001110xx1xxxxx100111xxxxxxxxxx  n   321  BASE        mul            dq0 : dq5 dq16 bhs_sz
 0x001111xxxxxxxx1000x0xxxxxxxxxx  n   321  BASE        mul            dq0 : dq5 dq16_h_sz vindex_H hs_sz

diff --git a/core/ir/aarch64/instr_create_api.h b/core/ir/aarch64/instr_create_api.h
@@ -1,6 +1,6 @@
 /* **********************************************************
  * Copyright (c) 2011-2023 Google, Inc. All rights reserved.
- * Copyright (c) 2016-2023 ARM Limited. All rights reserved.
+ * Copyright (c) 2016-2024 ARM Limited. All rights reserved.
  * Copyright (c) 2002-2010 VMware, Inc. All rights reserved.
  * **********************************************************/
 
@@ -670,8 +670,10 @@
     instr_create_1dst_3src(dc, OP_movz, rt, imm16, OPND_CREATE_LSL(), lsl)
 #define INSTR_CREATE_mrs(dc, Xt, sysreg) \
     instr_create_1dst_1src((dc), OP_mrs, (Xt), (sysreg))
-#define INSTR_CREATE_msr(dc, sysreg, Xt) \
-    instr_create_1dst_1src((dc), OP_msr, (sysreg), (Xt))
+#define INSTR_CREATE_msr(dc, sysreg, Xt_or_imm) \
+    opnd_is_immed(Xt_or_imm)?  \
+    instr_create_0dst_2src((dc), OP_msr, (sysreg), (Xt_or_imm)) : \
+    instr_create_1dst_1src((dc), OP_msr, (sysreg), (Xt_or_imm))
 #define INSTR_CREATE_nop(dc) instr_create_0dst_0src((dc), OP_nop)
 #define INSTR_CREATE_ret(dc, Rn) instr_create_0dst_1src((dc), OP_ret, (Rn))
 #define INSTR_CREATE_stp(dc, mem, rt1, rt2) \

diff --git a/suite/tests/api/dis-a64.txt b/suite/tests/api/dis-a64.txt
@@ -1,5 +1,5 @@
 # **********************************************************
-# Copyright (c) 2016-2022 ARM Limited. All rights reserved.
+# Copyright (c) 2016-2024 ARM Limited. All rights reserved.
 # **********************************************************
 
 # Redistribution and use in source and binary forms, with or without
@@ -31756,6 +31756,16 @@ d5034bff : msr DAIFClr, #0xb                         : msr    %daifclr $0x0b
 d5034cff : msr DAIFClr, #0xc                         : msr    %daifclr $0x0c
 d5034dff : msr DAIFClr, #0xd                         : msr    %daifclr $0x0d
 d5034fff : msr DAIFClr, #0xf                         : msr    %daifclr $0x0f
+d500407f : msr UAO, #0x0                             : msr    %uao $0x00
+d500417f : msr UAO, #0x1                             : msr    %uao $0x01
+d500409f : msr PAN, #0x0                             : msr    %pan $0x00
+d500419f : msr PAN, #0x1                             : msr    %pan $0x01
+d503403f : msr SSBS, #0x0                            : msr    %ssbs $0x00
+d503413f : msr SSBS, #0x1                            : msr    %ssbs $0x01
+d503405f : msr DIT, #0x0                             : msr    %dit $0x00
+d503415f : msr DIT, #0x1                             : msr    %dit $0x01
+d503409f : msr TCO, #0x0                             : msr    %tco $0x00
+d503419f : msr TCO, #0x1                             : msr    %tco $0x01
 
 d5100000 : msr    s2_0_c0_c0_0, x0        : msr    %x0 $0x0000
 d51b4201 : msr    nzcv, x1                : msr    %x1 -> %nzcv