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i#3044: Split out SVE instruction test files
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This patch creates a new file for SVE disassembly tests
and another ir_aarch64 test file. Also included is a small
bug fix for the disassembly test sorter that could remove
a test if the file did not end in a new line.

issues: #3044

Change-Id: I8b2ded8cd8d48d160132e96d712d502d30cfd05f
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@joshua-warburton
joshua-warburton committed Oct 7, 2022
1 parent a001557 commit c92f8fb
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Showing 7 changed files with 302 additions and 90 deletions.
111 changes: 58 additions & 53 deletions core/ir/aarch64/instr_create_api.h
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Original file line number Diff line number Diff line change
Expand Up @@ -3730,59 +3730,6 @@
*/
#define INSTR_CREATE_st1_multi_1(dc, r, q, s) instr_create_1dst_2src(dc, OP_st1, r, q, s)

/* -------- SVE bitwise logical operations (predicated) ---------------- */

/**
* Creates an ORR scalable vector instruction.
* \param dc The void * dcontext used to allocate memory for the instr_t.
* \param Zd The output SVE vector register.
* \param Pg Predicate register for predicated instruction, P0-P7.
* \param Zd_ The first input SVE vector register. Must match Zd.
* \param Zm The second input SVE vector register.
* \param width The vector element width. Use either OPND_CREATE_BYTE(),
* OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
*/
#define INSTR_CREATE_orr_sve_pred(dc, Zd, Pg, Zd_, Zm, width) \
instr_create_1dst_4src(dc, OP_orr, Zd, Pg, Zd_, Zm, width)

/**
* Creates an EOR scalable vector instruction.
* \param dc The void * dcontext used to allocate memory for the instr_t.
* \param Zd The output SVE vector register.
* \param Pg Predicate register for predicated instruction, P0-P7.
* \param Zd_ The first input SVE vector register. Must match Zd.
* \param Zm The second input SVE vector register.
* \param width The vector element width. Use either OPND_CREATE_BYTE(),
* OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
*/
#define INSTR_CREATE_eor_sve_pred(dc, Zd, Pg, Zd_, Zm, width) \
instr_create_1dst_4src(dc, OP_eor, Zd, Pg, Zd_, Zm, width)

/**
* Creates an AND scalable vector instruction.
* \param dc The void * dcontext used to allocate memory for the instr_t.
* \param Zd The output SVE vector register.
* \param Pg Predicate register for predicated instruction, P0-P7.
* \param Zd_ The first input SVE vector register. Must match Zd.
* \param Zm The second input SVE vector register.
* \param width The vector element width. Use either OPND_CREATE_BYTE(),
* OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
*/
#define INSTR_CREATE_and_sve_pred(dc, Zd, Pg, Zd_, Zm, width) \
instr_create_1dst_4src(dc, OP_and, Zd, Pg, Zd_, Zm, width)

/**
* Creates a BIC scalable vector instruction.
* \param dc The void * dcontext used to allocate memory for the instr_t.
* \param Zd The output SVE vector register.
* \param Pg Predicate register for predicated instruction, P0-P7.
* \param Zd_ The first input SVE vector register. Must match Zd.
* \param Zm The second input SVE vector register.
* \param width The vector element width. Use either OPND_CREATE_BYTE(),
* OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
*/
#define INSTR_CREATE_bic_sve_pred(dc, Zd, Pg, Zd_, Zm, width) \
instr_create_1dst_4src(dc, OP_bic, Zd, Pg, Zd_, Zm, width)

/* -------- Advanced SIMD three different ------------------------------ */

Expand Down Expand Up @@ -4924,4 +4871,62 @@
*/
#define INSTR_CREATE_xpaci(dc, Rd) instr_create_0dst_1src((dc), OP_xpaci, (Rd))

/****************************************************************************
* SVE Instructions *
****************************************************************************/

/* -------- SVE bitwise logical operations (predicated) ---------------- */

/**
* Creates an ORR scalable vector instruction.
* \param dc The void * dcontext used to allocate memory for the instr_t.
* \param Zd The output SVE vector register.
* \param Pg Predicate register for predicated instruction, P0-P7.
* \param Zd_ The first input SVE vector register. Must match Zd.
* \param Zm The second input SVE vector register.
* \param width The vector element width. Use either OPND_CREATE_BYTE(),
* OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
*/
#define INSTR_CREATE_orr_sve_pred(dc, Zd, Pg, Zd_, Zm, width) \
instr_create_1dst_4src(dc, OP_orr, Zd, Pg, Zd_, Zm, width)

/**
* Creates an EOR scalable vector instruction.
* \param dc The void * dcontext used to allocate memory for the instr_t.
* \param Zd The output SVE vector register.
* \param Pg Predicate register for predicated instruction, P0-P7.
* \param Zd_ The first input SVE vector register. Must match Zd.
* \param Zm The second input SVE vector register.
* \param width The vector element width. Use either OPND_CREATE_BYTE(),
* OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
*/
#define INSTR_CREATE_eor_sve_pred(dc, Zd, Pg, Zd_, Zm, width) \
instr_create_1dst_4src(dc, OP_eor, Zd, Pg, Zd_, Zm, width)

/**
* Creates an AND scalable vector instruction.
* \param dc The void * dcontext used to allocate memory for the instr_t.
* \param Zd The output SVE vector register.
* \param Pg Predicate register for predicated instruction, P0-P7.
* \param Zd_ The first input SVE vector register. Must match Zd.
* \param Zm The second input SVE vector register.
* \param width The vector element width. Use either OPND_CREATE_BYTE(),
* OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
*/
#define INSTR_CREATE_and_sve_pred(dc, Zd, Pg, Zd_, Zm, width) \
instr_create_1dst_4src(dc, OP_and, Zd, Pg, Zd_, Zm, width)

/**
* Creates a BIC scalable vector instruction.
* \param dc The void * dcontext used to allocate memory for the instr_t.
* \param Zd The output SVE vector register.
* \param Pg Predicate register for predicated instruction, P0-P7.
* \param Zd_ The first input SVE vector register. Must match Zd.
* \param Zm The second input SVE vector register.
* \param width The vector element width. Use either OPND_CREATE_BYTE(),
* OPND_CREATE_HALF(), OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
*/
#define INSTR_CREATE_bic_sve_pred(dc, Zd, Pg, Zd_, Zm, width) \
instr_create_1dst_4src(dc, OP_bic, Zd, Pg, Zd_, Zm, width)

#endif /* DR_IR_MACROS_AARCH64_H */
3 changes: 3 additions & 0 deletions suite/tests/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -1862,6 +1862,7 @@ if (NOT ANDROID)
tobuild_api(api.ir_negative api/ir_aarch64_negative.c "" "" OFF OFF OFF)
tobuild_api(api.ir_v81 api/ir_aarch64_v81.c "" "" OFF OFF OFF)
tobuild_api(api.ir_v82 api/ir_aarch64_v82.c "" "" OFF OFF OFF)
tobuild_api(api.ir_sve api/ir_aarch64_sve.c "" "" OFF OFF OFF)
endif (AARCH64)
endif ()

Expand Down Expand Up @@ -2931,6 +2932,8 @@ elseif (AARCH64)
add_api_exe(api.dis-a64 api/dis-a64.c OFF OFF)
torunonly_api(api.dis-a64 api.dis-a64 api/dis-a64.c ""
"-q;${CMAKE_CURRENT_SOURCE_DIR}/api/dis-a64.txt" OFF OFF)
torunonly_api(api.dis-a64-sve api.dis-a64 api/dis-a64.c ""
"-q;${CMAKE_CURRENT_SOURCE_DIR}/api/dis-a64-sve.txt" OFF OFF)
add_api_exe(api.reenc-a64 api/reenc-a64.c OFF OFF)
tobuild_api(api.opnd api/opnd-a64.c "" "" OFF OFF OFF)
elseif (X86)
Expand Down
95 changes: 95 additions & 0 deletions suite/tests/api/dis-a64-sve.txt
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Original file line number Diff line number Diff line change
@@ -0,0 +1,95 @@
# **********************************************************
# Copyright (c) 2022 ARM Limited. All rights reserved.
# **********************************************************

# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# * Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# * Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution.
#
# * Neither the name of ARM Limited nor the names of its contributors may be
# used to endorse or promote products derived from this software without
# specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL ARM LIMITED OR CONTRIBUTORS BE LIABLE
# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
# DAMAGE.

# Test data for DynamoRIO's AArch64 SVE encoder, decoder and disassembler.

# This file contains colon-separated fields that are used to
# test the decoder.

# The first field contains the hex encoding of the instruction and
# its operands.

# The second field is the disassembly of the first field and is not
# used by testing.

# The optional third field is the expected encoding of the instruction if the
# re-encoding differs from the initial encoding in the first field. This
# is usually set if the instruction has "soft bits" which are required
# to be ignored.

# The fourth field (or third if no expected encoding is present) is the
# disassembly that is expected to be produced by DynamoRIO. It is both case
# and white-space sensitive.

# Tests:
043e0362 : add z2.b, z27.b, z30.b : add %z27 %z30 $0x00 -> %z2
047e0362 : add z2.h, z27.h, z30.h : add %z27 %z30 $0x01 -> %z2
04be0362 : add z2.s, z27.s, z30.s : add %z27 %z30 $0x02 -> %z2
04fe0362 : add z2.d, z27.d, z30.d : add %z27 %z30 $0x03 -> %z2

041a06ff : and z31.b, p1/m, z31.b, z23.b : and %p1 %z31 %z23 $0x00 -> %z31
045a06ff : and z31.h, p1/m, z31.h, z23.h : and %p1 %z31 %z23 $0x01 -> %z31
049a06ff : and z31.s, p1/m, z31.s, z23.s : and %p1 %z31 %z23 $0x02 -> %z31
04da06ff : and z31.d, p1/m, z31.d, z23.d : and %p1 %z31 %z23 $0x03 -> %z31

041b0b02 : bic z2.b, p2/m, z2.b, z24.b : bic %p2 %z2 %z24 $0x00 -> %z2
045b0b02 : bic z2.h, p2/m, z2.h, z24.h : bic %p2 %z2 %z24 $0x01 -> %z2
049b0b02 : bic z2.s, p2/m, z2.s, z24.s : bic %p2 %z2 %z24 $0x02 -> %z2
04db0b02 : bic z2.d, p2/m, z2.d, z24.d : bic %p2 %z2 %z24 $0x03 -> %z2

0419105d : eor z29.b, p4/m, z29.b, z2.b : eor %p4 %z29 %z2 $0x00 -> %z29
0459105d : eor z29.h, p4/m, z29.h, z2.h : eor %p4 %z29 %z2 $0x01 -> %z29
0499105d : eor z29.s, p4/m, z29.s, z2.s : eor %p4 %z29 %z2 $0x02 -> %z29
04d9105d : eor z29.d, p4/m, z29.d, z2.d : eor %p4 %z29 %z2 $0x03 -> %z29

04181da2 : orr z2.b, p7/m, z2.b, z13.b : orr %p7 %z2 %z13 $0x00 -> %z2
04581da2 : orr z2.h, p7/m, z2.h, z13.h : orr %p7 %z2 %z13 $0x01 -> %z2
04981da2 : orr z2.s, p7/m, z2.s, z13.s : orr %p7 %z2 %z13 $0x02 -> %z2
04d81da2 : orr z2.d, p7/m, z2.d, z13.d : orr %p7 %z2 %z13 $0x03 -> %z2

043719e4 : sqsub z4.b, z15.b, z23.b : sqsub %z15 %z23 $0x00 -> %z4
047719e4 : sqsub z4.h, z15.h, z23.h : sqsub %z15 %z23 $0x01 -> %z4
04b719e4 : sqsub z4.s, z15.s, z23.s : sqsub %z15 %z23 $0x02 -> %z4
04f719e4 : sqsub z4.d, z15.d, z23.d : sqsub %z15 %z23 $0x03 -> %z4

043d05a0 : sub z0.b, z13.b, z29.b : sub %z13 %z29 $0x00 -> %z0
047d05a0 : sub z0.h, z13.h, z29.h : sub %z13 %z29 $0x01 -> %z0
04bd05a0 : sub z0.s, z13.s, z29.s : sub %z13 %z29 $0x02 -> %z0
04fd05a0 : sub z0.d, z13.d, z29.d : sub %z13 %z29 $0x03 -> %z0

043417e2 : uqadd z2.b, z31.b, z20.b : uqadd %z31 %z20 $0x00 -> %z2
047417e2 : uqadd z2.h, z31.h, z20.h : uqadd %z31 %z20 $0x01 -> %z2
04b417e2 : uqadd z2.s, z31.s, z20.s : uqadd %z31 %z20 $0x02 -> %z2
04f417e2 : uqadd z2.d, z31.d, z20.d : uqadd %z31 %z20 $0x03 -> %z2

04281f42 : uqsub z2.b, z26.b, z8.b : uqsub %z26 %z8 $0x00 -> %z2
04681f42 : uqsub z2.h, z26.h, z8.h : uqsub %z26 %z8 $0x01 -> %z2
04a81f42 : uqsub z2.s, z26.s, z8.s : uqsub %z26 %z8 $0x02 -> %z2
04e81f42 : uqsub z2.d, z26.d, z8.d : uqsub %z26 %z8 $0x03 -> %z2
36 changes: 0 additions & 36 deletions suite/tests/api/dis-a64.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -274,10 +274,6 @@ ba01001e : adcs x30, x0, x1 : adcs %x0 %x1 -> %x30
4efa8738 : add v24.2d, v25.2d, v26.2d : add %q25 %q26 $0x03 -> %q24
4efd879b : add v27.2d, v28.2d, v29.2d : add %q28 %q29 $0x03 -> %q27
4ee087fe : add v30.2d, v31.2d, v0.2d : add %q31 %q0 $0x03 -> %q30
043e0362 : add z2.b, z27.b, z30.b : add %z27 %z30 $0x00 -> %z2
047e0362 : add z2.h, z27.h, z30.h : add %z27 %z30 $0x01 -> %z2
04be0362 : add z2.s, z27.s, z30.s : add %z27 %z30 $0x02 -> %z2
04fe0362 : add z2.d, z27.d, z30.d : add %z27 %z30 $0x03 -> %z2

# ADD <V><d>, <V><n>, <V><m>
5ee28420 : add d0, d1, d2 : add %d1 %d2 -> %d0
Expand Down Expand Up @@ -1314,10 +1310,6 @@ f07ffffe : adrp x30, ( . + 0xfffff000) : adrp <rel> 0x000000010f
92400441 : and x1, x2, #0x3 : and %x2 $0x0000000000000003 -> %x1
0e2a1f3c : and v28.8b, v25.8b, v10.8b : and %d25 %d10 -> %d28
4e2a1f3c : and v28.16b, v25.16b, v10.16b : and %q25 %q10 -> %q28
041a06ff : and z31.b, p1/m, z31.b, z23.b : and %p1 %z31 %z23 $0x00 -> %z31
045a06ff : and z31.h, p1/m, z31.h, z23.h : and %p1 %z31 %z23 $0x01 -> %z31
049a06ff : and z31.s, p1/m, z31.s, z23.s : and %p1 %z31 %z23 $0x02 -> %z31
04da06ff : and z31.d, p1/m, z31.d, z23.d : and %p1 %z31 %z23 $0x03 -> %z31

# AND <Xd>, <Xn>, <Xm>, <extend> #<imm> (AND-R.RRI-64_log_shift)
8a020020 : and x0, x1, x2, LSL #0 : and %x1 %x2 lsl $0x00 -> %x0
Expand Down Expand Up @@ -1824,10 +1816,6 @@ b37fffff : bfxil xzr, xzr, #63, #1 : bfm %xzr %xzr $0x3f $0x3f -> %xzr
8aff13ff : bic xzr, xzr, xzr, ror #4 : bic %xzr %xzr ror $0x04 -> %xzr
0e6f1ff8 : bic v24.8b, v31.8b, v15.8b : bic %d31 %d15 -> %d24
4e6f1ff8 : bic v24.16b, v31.16b, v15.16b : bic %q31 %q15 -> %q24
041b0b02 : bic z2.b, p2/m, z2.b, z24.b : bic %p2 %z2 %z24 $0x00 -> %z2
045b0b02 : bic z2.h, p2/m, z2.h, z24.h : bic %p2 %z2 %z24 $0x01 -> %z2
049b0b02 : bic z2.s, p2/m, z2.s, z24.s : bic %p2 %z2 %z24 $0x02 -> %z2
04db0b02 : bic z2.d, p2/m, z2.d, z24.d : bic %p2 %z2 %z24 $0x03 -> %z2

# BIC <Vd>.<T>, #<imm8>{, LSL #<amount>}
2f009400 : bic v0.4h, #0, lsl #0 : bic $0x00 $0x0000001000000000 -> %d0
Expand Down Expand Up @@ -8642,10 +8630,6 @@ cadf13ff : eor xzr, xzr, xzr, ror #4 : eor %xzr %xzr ror $0x04 -> %xzr
d2400441 : eor x1, x2, #0x3 : eor %x2 $0x0000000000000003 -> %x1
2e341c33 : eor v19.8b, v1.8b, v20.8b : eor %d1 %d20 -> %d19
6e341c33 : eor v19.16b, v1.16b, v20.16b : eor %q1 %q20 -> %q19
0419105d : eor z29.b, p4/m, z29.b, z2.b : eor %p4 %z29 %z2 $0x00 -> %z29
0459105d : eor z29.h, p4/m, z29.h, z2.h : eor %p4 %z29 %z2 $0x01 -> %z29
0499105d : eor z29.s, p4/m, z29.s, z2.s : eor %p4 %z29 %z2 $0x02 -> %z29
04d9105d : eor z29.d, p4/m, z29.d, z2.d : eor %p4 %z29 %z2 $0x03 -> %z29

# EOR <Wd>, <Wn>, <Wm>, <extend> #<imm> (EOR-R.RRI-32_log_shift)
4a020020 : eor w0, w1, w2, LSL #0 : eor %w1 %w2 lsl $0x00 -> %w0
Expand Down Expand Up @@ -32256,10 +32240,6 @@ aa431041 : orr x1, x2, x3, lsr #4 : orr %x2 %x3 lsr $0x04 -
b2400441 : orr x1, x2, #0x3 : orr %x2 $0x0000000000000003 -> %x1
0ea01c5a : orr v26.8b, v2.8b, v0.8b : orr %d2 %d0 -> %d26
4ea01c5a : orr v26.16b, v2.16b, v0.16b : orr %q2 %q0 -> %q26
04181da2 : orr z2.b, p7/m, z2.b, z13.b : orr %p7 %z2 %z13 $0x00 -> %z2
04581da2 : orr z2.h, p7/m, z2.h, z13.h : orr %p7 %z2 %z13 $0x01 -> %z2
04981da2 : orr z2.s, p7/m, z2.s, z13.s : orr %p7 %z2 %z13 $0x02 -> %z2
04d81da2 : orr z2.d, p7/m, z2.d, z13.d : orr %p7 %z2 %z13 $0x03 -> %z2

# ORR (vector, immediate): <Vd>.4h, #<imm8>{, LSL #0}
0f009400 : orr v0.4h, #0, lsl #0 : orr $0x00 $0x0000001000000000 -> %d0
Expand Down Expand Up @@ -37609,10 +37589,6 @@ d41fffe3 : smc #0xffff : smc $0xffff
0eb72de4 : sqsub v4.2s, v15.2s, v23.2s : sqsub %d15 %d23 $0x02 -> %d4
4eb72de4 : sqsub v4.4s, v15.4s, v23.4s : sqsub %q15 %q23 $0x02 -> %q4
4ef72de4 : sqsub v4.2d, v15.2d, v23.2d : sqsub %q15 %q23 $0x03 -> %q4
043719e4 : sqsub z4.b, z15.b, z23.b : sqsub %z15 %z23 $0x00 -> %z4
047719e4 : sqsub z4.h, z15.h, z23.h : sqsub %z15 %z23 $0x01 -> %z4
04b719e4 : sqsub z4.s, z15.s, z23.s : sqsub %z15 %z23 $0x02 -> %z4
04f719e4 : sqsub z4.d, z15.d, z23.d : sqsub %z15 %z23 $0x03 -> %z4

# SQSUB <V><d>, <V><n>, <V><m>
5e222c20 : sqsub b0, b1, b2 : sqsub %b1 %b2 -> %b0
Expand Down Expand Up @@ -47771,10 +47747,6 @@ d13fffff : sub sp, sp, #0xfff : sub %sp $0x0fff lsl $0x00 -> %sp
2ebc877d : sub v29.2s, v27.2s, v28.2s : sub %d27 %d28 $0x02 -> %d29
6ebc877d : sub v29.4s, v27.4s, v28.4s : sub %q27 %q28 $0x02 -> %q29
6efc877d : sub v29.2d, v27.2d, v28.2d : sub %q27 %q28 $0x03 -> %q29
043d05a0 : sub z0.b, z13.b, z29.b : sub %z13 %z29 $0x00 -> %z0
047d05a0 : sub z0.h, z13.h, z29.h : sub %z13 %z29 $0x01 -> %z0
04bd05a0 : sub z0.s, z13.s, z29.s : sub %z13 %z29 $0x02 -> %z0
04fd05a0 : sub z0.d, z13.d, z29.d : sub %z13 %z29 $0x03 -> %z0

# SUB <Dd>, <Dn>, <Dm>
7ee28420 : sub d0, d1, d2 : sub %d1 %d2 -> %d0
Expand Down Expand Up @@ -50805,10 +50777,6 @@ d3431041 : ubfx x1, x2, #3, #2 : ubfm %x2 $0x03 $0x04 -> %x1
2ebf0fa6 : uqadd v6.2s, v29.2s, v31.2s : uqadd %d29 %d31 $0x02 -> %d6
6ebf0fa6 : uqadd v6.4s, v29.4s, v31.4s : uqadd %q29 %q31 $0x02 -> %q6
6eff0fa6 : uqadd v6.2d, v29.2d, v31.2d : uqadd %q29 %q31 $0x03 -> %q6
043417e2 : uqadd z2.b, z31.b, z20.b : uqadd %z31 %z20 $0x00 -> %z2
047417e2 : uqadd z2.h, z31.h, z20.h : uqadd %z31 %z20 $0x01 -> %z2
04b417e2 : uqadd z2.s, z31.s, z20.s : uqadd %z31 %z20 $0x02 -> %z2
04f417e2 : uqadd z2.d, z31.d, z20.d : uqadd %z31 %z20 $0x03 -> %z2

# UQADD <V><d>, <V><n>, <V><m>
7e220c20 : uqadd b0, b1, b2 : uqadd %b1 %b2 -> %b0
Expand Down Expand Up @@ -51457,10 +51425,6 @@ d3431041 : ubfx x1, x2, #3, #2 : ubfm %x2 $0x03 $0x04 -> %x1
2eb52f7d : uqsub v29.2s, v27.2s, v21.2s : uqsub %d27 %d21 $0x02 -> %d29
6eb52f7d : uqsub v29.4s, v27.4s, v21.4s : uqsub %q27 %q21 $0x02 -> %q29
6ef52f7d : uqsub v29.2d, v27.2d, v21.2d : uqsub %q27 %q21 $0x03 -> %q29
04281f42 : uqsub z2.b, z26.b, z8.b : uqsub %z26 %z8 $0x00 -> %z2
04681f42 : uqsub z2.h, z26.h, z8.h : uqsub %z26 %z8 $0x01 -> %z2
04a81f42 : uqsub z2.s, z26.s, z8.s : uqsub %z26 %z8 $0x02 -> %z2
04e81f42 : uqsub z2.d, z26.d, z8.d : uqsub %z26 %z8 $0x03 -> %z2

# UQSUB <V><d>, <V><n>, <V><m>
7e222c20 : uqsub b0, b1, b2 : uqsub %b1 %b2 -> %b0
Expand Down
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