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i#3044 AArch64 SVE2 codec: Add misc predicate instructions (#6191)
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This patch adds the appropriate macros, tests and codec entries to
encode and decode the following variants:
```
MATCH   <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts>
NMATCH  <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts>
URECPE  <Zd>.S, <Pg>/M, <Zn>.S
URSQRTE <Zd>.S, <Pg>/M, <Zn>.S
WHILEGE <Pd>.<Ts>, <R><n>, <R><m>
WHILEGT <Pd>.<Ts>, <R><n>, <R><m>
WHILEHI <Pd>.<Ts>, <R><n>, <R><m>
WHILEHS <Pd>.<Ts>, <R><n>, <R><m>
WHILERW <Pd>.<Ts>, <Xn>, <Xm>
WHILEWR <Pd>.<Ts>, <Xn>, <Xm>
```
Issue: #3044
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@joshua-warburton
joshua-warburton authored Jul 10, 2023
1 parent 4e71995 commit 85a35f3
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Showing 6 changed files with 1,453 additions and 1 deletion.
36 changes: 36 additions & 0 deletions core/ir/aarch64/codec.c
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Original file line number Diff line number Diff line change
Expand Up @@ -6762,6 +6762,18 @@ encode_opnd_p_size_bhs_0(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *
return encode_sized_p(0, 22, BYTE_REG, SINGLE_REG, opnd, enc_out);
}

static inline bool
decode_opnd_p_size_bh_0(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
{
return decode_sized_p(0, 22, BYTE_REG, HALF_REG, enc, pc, opnd);
}

static inline bool
encode_opnd_p_size_bh_0(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_out)
{
return encode_sized_p(0, 22, BYTE_REG, HALF_REG, opnd, enc_out);
}

static inline bool
decode_opnd_p_size_hsd_0(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
{
Expand Down Expand Up @@ -6972,6 +6984,18 @@ encode_opnd_z_size_bhs_5(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *
return encode_sized_z(5, 22, BYTE_REG, SINGLE_REG, 0, 0, opnd, enc_out);
}

static inline bool
decode_opnd_z_size_bh_5(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
{
return decode_sized_z(5, 22, BYTE_REG, HALF_REG, 0, 0, enc, pc, opnd);
}

static inline bool
encode_opnd_z_size_bh_5(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_out)
{
return encode_sized_z(5, 22, BYTE_REG, HALF_REG, 0, 0, opnd, enc_out);
}

static inline bool
decode_opnd_z_sizep1_bhs_5(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
{
Expand Down Expand Up @@ -7225,6 +7249,18 @@ encode_opnd_z_size_bhsd_16(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint
return encode_sized_z(16, 22, BYTE_REG, DOUBLE_REG, 0, 0, opnd, enc_out);
}

static inline bool
decode_opnd_z_size_bh_16(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
{
return decode_sized_z(16, 22, BYTE_REG, HALF_REG, 0, 0, enc, pc, opnd);
}

static inline bool
encode_opnd_z_size_bh_16(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_out)
{
return encode_sized_z(16, 22, BYTE_REG, HALF_REG, 0, 0, opnd, enc_out);
}

static inline bool
decode_opnd_z_size_sd_16(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
{
Expand Down
14 changes: 14 additions & 0 deletions core/ir/aarch64/codec_sve2.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -91,7 +91,9 @@
11000100100xxxxx100xxxxxxxxxxxxx n 1187 SVE2 ldnt1sh z_d_0 : svemem_vec_sd_gpr16 p10_zer_lo
10000100100xxxxx100xxxxxxxxxxxxx n 1187 SVE2 ldnt1sh z_s_0 : svemem_vec_sd_gpr16 p10_zer_lo
11000101000xxxxx100xxxxxxxxxxxxx n 1188 SVE2 ldnt1sw z_d_0 : svemem_vec_sd_gpr16 p10_zer_lo
01000101xx1xxxxx100xxxxxxxx0xxxx w 1189 SVE2 match p_size_bh_0 : p10_zer_lo z_size_bh_5 z_size_bh_16
00000100111xxxxx001111xxxxxxxxxx n 1072 SVE2 nbsl z_d_0 : z_d_0 z_d_16 z_d_5
01000101xx1xxxxx100xxxxxxxx1xxxx w 1190 SVE2 nmatch p_size_bh_0 : p10_zer_lo z_size_bh_5 z_size_bh_16
00000100001xxxxx011001xxxxxxxxxx n 328 SVE2 pmul z_msz_bhsd_0 : z_msz_bhsd_5 z_msz_bhsd_16
01000101xx0xxxxx011010xxxxxxxxxx n 1084 SVE2 pmullb z_size_hd_0 : z_sizep1_bs_5 z_sizep1_bs_16
01000101xx0xxxxx011011xxxxxxxxxx n 1085 SVE2 pmullt z_size_hd_0 : z_sizep1_bs_5 z_sizep1_bs_16
Expand Down Expand Up @@ -270,10 +272,12 @@
01000100xx011111100xxxxxxxxxxxxx n 1154 SVE2 uqsubr z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5
010001010x1xx000010010xxxxxxxxxx n 1143 SVE2 uqxtnb z_wtszl19_bhsd_0 : z_wtszl19p1_bhsd_5
010001010x1xx000010011xxxxxxxxxx n 1144 SVE2 uqxtnt z_wtszl19_bhsd_0 : z_wtszl19_bhsd_0 z_wtszl19p1_bhsd_5
0100010010000000101xxxxxxxxxxxxx n 541 SVE2 urecpe z_s_0 : p10_mrg_lo z_s_5
01000100xx010101100xxxxxxxxxxxxx n 542 SVE2 urhadd z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5
01000100xx000011100xxxxxxxxxxxxx n 543 SVE2 urshl z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5
01000100xx000111100xxxxxxxxxxxxx n 1155 SVE2 urshlr z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5
00000100xx001101100xxxxxxxxxxxxx n 544 SVE2 urshr z_tszl8_bhsd_0 : p10_mrg_lo z_tszl8_bhsd_0 tszl8_imm3_5p1
0100010010000001101xxxxxxxxxxxxx n 545 SVE2 ursqrte z_s_0 : p10_mrg_lo z_s_5
01000101xx0xxxxx111011xxxxxxxxxx n 546 SVE2 ursra z_tszl19_bhsd_0 : z_tszl19_bhsd_0 z_tszl19_bhsd_5 tszl19_imm3_16p1
010001010x0xxxxx101010xxxxxxxxxx n 1184 SVE2 ushllb z_tszl19p1_hsd_0 : z_tszl19_bhs_5 tszl19lo_imm3_16
010001010x0xxxxx101011xxxxxxxxxx n 1185 SVE2 ushllt z_tszl19p1_hsd_0 : z_tszl19_bhs_5 tszl19lo_imm3_16
Expand All @@ -283,4 +287,14 @@
01000101xx0xxxxx000111xxxxxxxxxx n 1136 SVE2 usublt z_size_hsd_0 : z_sizep1_bhs_5 z_sizep1_bhs_16
01000101xx0xxxxx010110xxxxxxxxxx n 1137 SVE2 usubwb z_size_hsd_0 : z_size_hsd_5 z_sizep1_bhs_16
01000101xx0xxxxx010111xxxxxxxxxx n 1138 SVE2 usubwt z_size_hsd_0 : z_size_hsd_5 z_sizep1_bhs_16
00100101xx1xxxxx000000xxxxx0xxxx w 1191 SVE2 whilege p_size_bhsd_0 : w5 w16
00100101xx1xxxxx000100xxxxx0xxxx w 1191 SVE2 whilege p_size_bhsd_0 : x5 x16
00100101xx1xxxxx000000xxxxx1xxxx w 1192 SVE2 whilegt p_size_bhsd_0 : w5 w16
00100101xx1xxxxx000100xxxxx1xxxx w 1192 SVE2 whilegt p_size_bhsd_0 : x5 x16
00100101xx1xxxxx000010xxxxx1xxxx w 1193 SVE2 whilehi p_size_bhsd_0 : w5 w16
00100101xx1xxxxx000110xxxxx1xxxx w 1193 SVE2 whilehi p_size_bhsd_0 : x5 x16
00100101xx1xxxxx000010xxxxx0xxxx w 1194 SVE2 whilehs p_size_bhsd_0 : w5 w16
00100101xx1xxxxx000110xxxxx0xxxx w 1194 SVE2 whilehs p_size_bhsd_0 : x5 x16
00100101xx1xxxxx001100xxxxx1xxxx w 1195 SVE2 whilerw p_size_bhsd_0 : x5 x16
00100101xx1xxxxx001100xxxxx0xxxx w 1196 SVE2 whilewr p_size_bhsd_0 : x5 x16
00000100xx1xxxxx001101xxxxxxxxxx n 604 SVE2 xar z_tszl19_bhsd_0 : z_tszl19_bhsd_0 z_tszl19_bhsd_5 tszl19_imm3_16p1
159 changes: 159 additions & 0 deletions core/ir/aarch64/instr_create_api.h
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Original file line number Diff line number Diff line change
Expand Up @@ -17483,4 +17483,163 @@
#define INSTR_CREATE_sqrdcmlah_sve_idx_imm_vector(dc, Zda, Zn, Zm, i1, rot) \
instr_create_1dst_5src(dc, OP_sqrdcmlah, Zda, Zda, Zn, Zm, i1, rot)

/**
* Creates a MATCH instruction.
*
* This macro is used to encode the forms:
\verbatim
MATCH <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts>
\endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Pd The destination predicate register. Can be P.b or P.h.
* \param Pg The governing predicate register, P (Predicate).
* \param Zn The first source vector register. Can be Z.b or Z.h.
* \param Zm The second source vector register. Can be Z.b or Z.h.
*/
#define INSTR_CREATE_match_sve_pred(dc, Pd, Pg, Zn, Zm) \
instr_create_1dst_3src(dc, OP_match, Pd, Pg, Zn, Zm)

/**
* Creates a NMATCH instruction.
*
* This macro is used to encode the forms:
\verbatim
NMATCH <Pd>.<Ts>, <Pg>/Z, <Zn>.<Ts>, <Zm>.<Ts>
\endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Pd The destination predicate register. Can be P.b or P.h.
* \param Pg The governing predicate register, P (Predicate).
* \param Zn The first source vector register. Can be Z.b or Z.h.
* \param Zm The second source vector register. Can be Z.b or Z.h.
*/
#define INSTR_CREATE_nmatch_sve_pred(dc, Pd, Pg, Zn, Zm) \
instr_create_1dst_3src(dc, OP_nmatch, Pd, Pg, Zn, Zm)

/**
* Creates an URECPE instruction.
*
* This macro is used to encode the forms:
\verbatim
URECPE <Zd>.S, <Pg>/M, <Zn>.S
\endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Zd The destination vector register, Z.s.
* \param Pg The governing predicate register, P (Predicate).
* \param Zn The source vector register, Z.s.
*/
#define INSTR_CREATE_urecpe_sve_pred(dc, Zd, Pg, Zn) \
instr_create_1dst_2src(dc, OP_urecpe, Zd, Pg, Zn)

/**
* Creates an URSQRTE instruction.
*
* This macro is used to encode the forms:
\verbatim
URSQRTE <Zd>.S, <Pg>/M, <Zn>.S
\endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Zd The destination vector register, Z.s.
* \param Pg The governing predicate register, P (Predicate).
* \param Zn The source vector register, Z.s.
*/
#define INSTR_CREATE_ursqrte_sve_pred(dc, Zd, Pg, Zn) \
instr_create_1dst_2src(dc, OP_ursqrte, Zd, Pg, Zn)

/**
* Creates a WHILEGE instruction.
*
* This macro is used to encode the forms:
\verbatim
WHILEGE <Pd>.<Ts>, <R><n>, <R><m>
\endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Pd The destination predicate register. Can be P.b, P.h, P.s or P.d.
* \param Rn The first source register. Can be W (Word, 32 bits) or X
* (Extended, 64 bits).
* \param Rm The second source register. Can be W (Word, 32 bits) or X
* (Extended, 64 bits).
*/
#define INSTR_CREATE_whilege_sve(dc, Pd, Rn, Rm) \
instr_create_1dst_2src(dc, OP_whilege, Pd, Rn, Rm)

/**
* Creates a WHILEGT instruction.
*
* This macro is used to encode the forms:
\verbatim
WHILEGT <Pd>.<Ts>, <R><n>, <R><m>
\endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Pd The destination predicate register. Can be P.b, P.h, P.s or P.d.
* \param Rn The first source register. Can be W (Word, 32 bits) or X
* (Extended, 64 bits).
* \param Rm The second source register. Can be W (Word, 32 bits) or X
* (Extended, 64 bits).
*/
#define INSTR_CREATE_whilegt_sve(dc, Pd, Rn, Rm) \
instr_create_1dst_2src(dc, OP_whilegt, Pd, Rn, Rm)

/**
* Creates a WHILEHI instruction.
*
* This macro is used to encode the forms:
\verbatim
WHILEHI <Pd>.<Ts>, <R><n>, <R><m>
\endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Pd The destination predicate register. Can be P.b, P.h, P.s or P.d.
* \param Rn The first source register. Can be W (Word, 32 bits) or X
* (Extended, 64 bits).
* \param Rm The second source register. Can be W (Word, 32 bits) or X
* (Extended, 64 bits).
*/
#define INSTR_CREATE_whilehi_sve(dc, Pd, Rn, Rm) \
instr_create_1dst_2src(dc, OP_whilehi, Pd, Rn, Rm)

/**
* Creates a WHILEHS instruction.
*
* This macro is used to encode the forms:
\verbatim
WHILEHS <Pd>.<Ts>, <R><n>, <R><m>
\endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Pd The destination predicate register. Can be P.b, P.h, P.s or P.d.
* \param Rn The first source register. Can be W (Word, 32 bits) or X
* (Extended, 64 bits).
* \param Rm The second source register. Can be W (Word, 32 bits) or X
* (Extended, 64 bits).
*/
#define INSTR_CREATE_whilehs_sve(dc, Pd, Rn, Rm) \
instr_create_1dst_2src(dc, OP_whilehs, Pd, Rn, Rm)

/**
* Creates a WHILERW instruction.
*
* This macro is used to encode the forms:
\verbatim
WHILERW <Pd>.<Ts>, <Xn>, <Xm>
\endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Pd The destination predicate register. Can be P.b, P.h, P.s or P.d.
* \param Rn The first source register, X (Extended, 64 bits).
* \param Rm The second source register, X (Extended, 64 bits).
*/
#define INSTR_CREATE_whilerw_sve(dc, Pd, Rn, Rm) \
instr_create_1dst_2src(dc, OP_whilerw, Pd, Rn, Rm)

/**
* Creates a WHILEWR instruction.
*
* This macro is used to encode the forms:
\verbatim
WHILEWR <Pd>.<Ts>, <Xn>, <Xm>
\endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Pd The destination predicate register. Can be P.b, P.h, P.s or P.d.
* \param Rn The first source register, X (Extended, 64 bits).
* \param Rm The second source register, X (Extended, 64 bits).
*/
#define INSTR_CREATE_whilewr_sve(dc, Pd, Rn, Rm) \
instr_create_1dst_2src(dc, OP_whilewr, Pd, Rn, Rm)
#endif /* DR_IR_MACROS_AARCH64_H */
5 changes: 4 additions & 1 deletion core/ir/aarch64/opnd_defs.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -302,13 +302,14 @@
--------xx---------------------- shift4 # shift type for logical (shifted register)
--------xx------------------xxxx p_size_bhsd_0 # sve predicate vector reg, elsz depending on size
--------xx------------------xxxx p_size_bhs_0 # sve predicate vector reg, elsz depending on size
--------xx------------------xxxx p_size_bh_0 # sve predicate vector reg, elsz depending on size
--------xx------------------xxxx p_size_hsd_0 # sve predicate vector reg, elsz depending on size
--------xx-----------------xxxxx float_reg0 # H, S or D register
--------xx-----------------xxxxx hsd_size_reg0 # hsd register, depending on size opcode
--------xx-----------------xxxxx bhsd_size_reg0 # bhsd register, depending on size opcode
--------xx-----------------xxxxx z_size_bhsd_0 # sve vector reg, elsz depending on size
--------xx-----------------xxxxx z_size_bhs_0 # sve vector reg, elsz depending on size
--------xx-----------------xxxxx z_sizep1_bhs_0 # sve vector reg, elsz depending on size, plus one
--------xx-----------------xxxxx z_sizep1_bhs_0 # sve vector reg, elsz depending on size, plus one
--------xx-----------------xxxxx z_size_hsd_0 # sve vector reg, elsz depending on size
--------xx-----------------xxxxx z_size_sd_0 # sve vector reg, elsz depending on size
--------xx-----------------xxxxx z_size_hd_0 # sve vector reg, elsz depending on size
Expand All @@ -319,6 +320,7 @@
--------xx------------xxxxx----- p_size_hsd_5 # sve predicate vector reg, elsz depending on size
--------xx------------xxxxx----- z_size_bhsd_5 # sve vector reg, elsz depending on size
--------xx------------xxxxx----- z_size_bhs_5 # sve vector reg, elsz depending on size
--------xx------------xxxxx----- z_size_bh_5 # sve vector reg, elsz depending on size
--------xx------------xxxxx----- z_sizep1_bhs_5 # sve vector reg, elsz depending on size, plus 1
--------xx------------xxxxx----- z_sizep2_bh_5 # sve vector reg, elsz depending on size, plus 2
--------xx------------xxxxx----- z_sizep1_bs_5 # sve vector reg, elsz depending on size, plus 1
Expand All @@ -334,6 +336,7 @@
--------xx-xxxxx---------------- bhsd_size_reg16 # bhsd register, depending on size opcode
--------xx-xxxxx---------------- p_size_bhsd_16 # sve vector reg, elsz depending on size
--------xx-xxxxx---------------- z_size_bhsd_16 # sve vector reg, elsz depending on size
--------xx-xxxxx---------------- z_size_bh_16 # sve vector reg, elsz depending on size
--------xx-xxxxx---------------- z_size_sd_16 # sve vector reg, elsz depending on size
--------xx-xxxxx---------------- z_sizep1_bhs_16 # sve vector reg, elsz depending on size plus 1
--------xx-xxxxx---------------- z_sizep2_bh_16 # sve vector reg, elsz depending on size plus 2
Expand Down
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