i#1569 AArch64: Implement encode and decode of SVC instruction.

The SVC instruction is used for system calls.

Review-URL: https://codereview.appspot.com/296130043

core/arch/aarch64/decode.c

@@ -174,7 +174,11 @@ decode_common(dcontext_t *dcontext, byte *pc, byte *orig_pc, instr_t *instr)
         instr_set_num_opnds(dcontext, instr, 0, 1);
         instr->src0 = opnd_create_reg(DR_REG_X0 + (enc & 31));
     }
-    else {
+    else if ((enc & 0xffe0001f) == 0xd4000001) {
+        instr_set_opcode(instr, OP_svc);
+        instr_set_num_opnds(dcontext, instr, 0, 1);
+        instr->src0 = OPND_CREATE_INT16(enc >> 5 & 0xffff);
+    } else {
         /* We use OP_xx for instructions not yet handled by the decoder.
          * If an A64 instruction accesses a general-purpose register
          * (except X30) then the number of that register appears in one

core/arch/aarch64/encode.c

@@ -187,6 +187,10 @@ static uint encode_common(byte *pc, instr_t *i)
                 (i->dsts[0].value.base_disp.base_reg - DR_REG_X0) << 5 |
                 i->dsts[0].value.base_disp.disp >>
                 (i->dsts[0].size == OPSZ_8 ? 3 : 2 ) << 10);
+    case OP_svc:
+        ASSERT(i->num_dsts == 0 && i->num_srcs == 1 &&
+               i->src0.kind == IMMED_INTEGER_kind);
+        return (0xd4000001 | (i->src0.value.immed_int & 0xffff) << 5);
     case OP_tbnz:
     case OP_tbz:
         ASSERT(i->num_dsts == 0 && i->num_srcs == 3 &&
@@ -205,7 +209,6 @@ static uint encode_common(byte *pc, instr_t *i)
     default:
         ASSERT_NOT_IMPLEMENTED(false); /* FIXME i#1569 */
     case OP_add:
-    case OP_svc:
         /* FIXME i#1569: These are encoded but never executed. */
         return i->opcode;
     }