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i#3044 AArch64 SVE codec: Add scalar memory with shift instructions
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This patch adds the appropriate macros, tests and codec entries
to encode the following variants:
LD1D    { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]
LD1H    { <Zt>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
LD1H    { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
LD1H    { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
LD1SH   { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
LD1SH   { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
LD1SW   { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
LD1W    { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
LD1W    { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
LD2D    { <Zt1>.D, <Zt2>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]
LD2H    { <Zt1>.H, <Zt2>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
LD2W    { <Zt1>.S, <Zt2>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
LD3D    { <Zt1>.D, <Zt2>.D, <Zt3>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]
LD3H    { <Zt1>.H, <Zt2>.H, <Zt3>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
LD3W    { <Zt1>.S, <Zt2>.S, <Zt3>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
LD4D    { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]
LD4H    { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
LD4W    { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
LDNT1D  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]
LDNT1H  { <Zt>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
LDNT1W  { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
ST1D    { <Zt>.D }, <Pg>, [<Xn|SP>, <Xm>, LSL #3]
ST1H    { <Zt>.<Ts> }, <Pg>, [<Xn|SP>, <Xm>, LSL #1]
ST1W    { <Zt>.<Ts> }, <Pg>, [<Xn|SP>, <Xm>, LSL #2]
ST2D    { <Zt1>.D, <Zt2>.D }, <Pg>, [<Xn|SP>, <Xm>, LSL #3]
ST2H    { <Zt1>.H, <Zt2>.H }, <Pg>, [<Xn|SP>, <Xm>, LSL #1]
ST2W    { <Zt1>.S, <Zt2>.S }, <Pg>, [<Xn|SP>, <Xm>, LSL #2]
ST3D    { <Zt1>.D, <Zt2>.D, <Zt3>.D }, <Pg>, [<Xn|SP>, <Xm>, LSL #3]
ST3H    { <Zt1>.H, <Zt2>.H, <Zt3>.H }, <Pg>, [<Xn|SP>, <Xm>, LSL #1]
ST3W    { <Zt1>.S, <Zt2>.S, <Zt3>.S }, <Pg>, [<Xn|SP>, <Xm>, LSL #2]
ST4D    { <Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <Pg>, [<Xn|SP>, <Xm>, LSL #3]
ST4H    { <Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <Pg>, [<Xn|SP>, <Xm>, LSL #1]
ST4W    { <Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <Pg>, [<Xn|SP>, <Xm>, LSL #2]
STNT1D  { <Zt>.D }, <Pg>, [<Xn|SP>, <Xm>, LSL #3]
STNT1H  { <Zt>.H }, <Pg>, [<Xn|SP>, <Xm>, LSL #1]
STNT1W  { <Zt>.S }, <Pg>, [<Xn|SP>, <Xm>, LSL #2]

issues: #3044

Change-Id: Ic9d21cd27f8b2a52bd8bc2ced76ba79f5deae69a
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@joshua-warburton
joshua-warburton committed Mar 10, 2023
1 parent d3f88ee commit 7d49009
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Showing 7 changed files with 2,214 additions and 116 deletions.
105 changes: 97 additions & 8 deletions core/ir/aarch64/codec.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4450,6 +4450,12 @@ svemem_gprs_per_element_encode(uint bytes_per_element, aarch64_reg_offset elemen
if (!opnd_is_base_disp(opnd) || opnd_get_size(opnd) != mem_transfer ||
opnd_get_disp(opnd) != 0)
return false;
uint given_shift;
dr_extend_type_t shift_type = opnd_get_index_extend(opnd, NULL, &given_shift);
if (shift_type != DR_EXTEND_UXTX)
return false;
if (shift_amount != given_shift)
return false;

uint rn, rm;
bool is_x_register;
Expand Down Expand Up @@ -5551,6 +5557,18 @@ encode_opnd_wx_sz_16(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_
return encode_opnd_rn(false, 16, 22, opnd, enc_out);
}

static inline bool
decode_opnd_z_size21_hsd_0(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
{
return decode_sized_z(0, 21, HALF_REG, DOUBLE_REG, 0, enc, pc, opnd);
}

static inline bool
encode_opnd_z_size21_hsd_0(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_out)
{
return encode_sized_z(0, 21, HALF_REG, DOUBLE_REG, 0, opnd, enc_out);
}

static inline bool
decode_opnd_z_size21_bhsd_0(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
{
Expand Down Expand Up @@ -6802,21 +6820,80 @@ dtype_is_signed(uint dtype)
/* svemem_gpr: GPR offset and base reg for SVE ld/st */

static inline void
sizes_from_dtype(const uint enc, aarch64_reg_offset *insz, aarch64_reg_offset *elsz)
sizes_from_dtype(const uint enc, aarch64_reg_offset *insz, aarch64_reg_offset *elsz,
bool check_signed)
{
uint dtype = extract_uint(enc, 21, 4);
if (dtype_is_signed(dtype))
if (check_signed && dtype_is_signed(dtype))
dtype = ~dtype;

*insz = BITS(dtype, 3, 2);
*elsz = BITS(dtype, 1, 0);
if (insz != NULL)
*insz = BITS(dtype, 3, 2);
if (elsz != NULL)
*elsz = BITS(dtype, 1, 0);
}

static inline bool
decode_opnd_svemem_msz_gpr_shf(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
{
aarch64_reg_offset elsz, dests;
sizes_from_dtype(enc, &elsz, &dests, false);

const uint shift_amount = elsz;

return svemem_gprs_per_element_decode((1 << elsz) * (dests + 1), elsz, shift_amount,
enc, opcode, pc, opnd);
}

static inline bool
encode_opnd_svemem_msz_gpr_shf(uint enc, int opcode, byte *pc, opnd_t opnd,
OUT uint *enc_out)
{
aarch64_reg_offset elsz, dests;
sizes_from_dtype(enc, &elsz, &dests, false);

const uint shift_amount = elsz;

return svemem_gprs_per_element_encode((1 << elsz) * (dests + 1), elsz, shift_amount,
enc, opcode, pc, opnd, enc_out);
}

static inline bool
decode_opnd_svemem_msz_stgpr_shf(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
{
aarch64_reg_offset elsz, dests;
sizes_from_dtype(enc, &elsz, &dests, false);
if (BITS(enc, 20, 16) == 0b11111)
return false;

const uint shift_amount = elsz;

return svemem_gprs_per_element_decode((1 << elsz) * (dests + 1), elsz, shift_amount,
enc, opcode, pc, opnd);
}

static inline bool
encode_opnd_svemem_msz_stgpr_shf(uint enc, int opcode, byte *pc, opnd_t opnd,
OUT uint *enc_out)
{
aarch64_reg_offset elsz, dests;
sizes_from_dtype(enc, &elsz, &dests, false);

const uint shift_amount = elsz;

bool success = svemem_gprs_per_element_encode(
(1 << elsz) * (dests + 1), elsz, shift_amount, enc, opcode, pc, opnd, enc_out);

if (BITS(enc, 20, 16) == 0b11111)
return false;
return success;
}

static inline bool
decode_opnd_svemem_gpr_shf(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
{
aarch64_reg_offset insz, elsz;
sizes_from_dtype(enc, &insz, &elsz);
sizes_from_dtype(enc, &insz, &elsz, true);

const uint shift_amount = opnd_size_to_shift_amount(get_opnd_size_from_offset(insz));

Expand All @@ -6828,7 +6905,7 @@ static inline bool
encode_opnd_svemem_gpr_shf(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_out)
{
aarch64_reg_offset insz, elsz;
sizes_from_dtype(enc, &insz, &elsz);
sizes_from_dtype(enc, &insz, &elsz, true);

const uint shift_amount = opnd_size_to_shift_amount(get_opnd_size_from_offset(insz));

Expand All @@ -6840,7 +6917,7 @@ static inline bool
decode_opnd_svemem_gprs_bhsdx(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
{
aarch64_reg_offset insz, elsz;
sizes_from_dtype(enc, &elsz, &insz);
sizes_from_dtype(enc, &elsz, &insz, true);

return svemem_gprs_per_element_decode(insz + 1, elsz, 0, enc, opcode, pc, opnd);
}
Expand All @@ -6850,7 +6927,7 @@ encode_opnd_svemem_gprs_bhsdx(uint enc, int opcode, byte *pc, opnd_t opnd,
OUT uint *enc_out)
{
aarch64_reg_offset insz, elsz;
sizes_from_dtype(enc, &elsz, &insz);
sizes_from_dtype(enc, &elsz, &insz, true);

return svemem_gprs_per_element_encode(insz + 1, elsz, 0, enc, opcode, pc, opnd,
enc_out);
Expand Down Expand Up @@ -6898,6 +6975,18 @@ encode_opnd_svemem_gpr_vec32_st(uint enc, int opcode, byte *pc, opnd_t opnd,
encode_svemem_gpr_vec_xs(enc, 14, opnd, enc_out);
}

static inline bool
decode_opnd_z_msz_bhsd_0(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
{
return decode_sized_z(0, 23, BYTE_REG, DOUBLE_REG, 0, enc, pc, opnd);
}

static inline bool
encode_opnd_z_msz_bhsd_0(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_out)
{
return encode_sized_z(0, 23, BYTE_REG, DOUBLE_REG, 0, opnd, enc_out);
}

static inline bool
decode_opnd_z_msz_bhsd_0p1(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
{
Expand Down
44 changes: 44 additions & 0 deletions core/ir/aarch64/codec_sve.txt
View file
Original file line number Diff line number Diff line change
Expand Up @@ -311,6 +311,7 @@
11000101110xxxxx110xxxxxxxxxxxxx n 975 SVE ld1d z_d_0 : svemem_gpr_vec64 p10_zer_lo
110001011x1xxxxx010xxxxxxxxxxxxx n 975 SVE ld1d z_d_0 : svemem_gpr_vec32_ld p10_zer_lo
110001011x0xxxxx010xxxxxxxxxxxxx n 975 SVE ld1d z_d_0 : svemem_gpr_vec32_ld p10_zer_lo
10100101111xxxxx010xxxxxxxxxxxxx n 975 SVE ld1d z_msz_bhsd_0 : svemem_gpr_shf p10_zer_lo
10000100101xxxxx110xxxxxxxxxxxxx n 976 SVE ld1h z_s_0 : svemem_vec_s_imm5 p10_zer_lo
11000100101xxxxx110xxxxxxxxxxxxx n 976 SVE ld1h z_d_0 : svemem_vec_d_imm5 p10_zer_lo
11000100111xxxxx110xxxxxxxxxxxxx n 976 SVE ld1h z_d_0 : svemem_gpr_vec64 p10_zer_lo
Expand All @@ -319,6 +320,9 @@
110001001x0xxxxx010xxxxxxxxxxxxx n 976 SVE ld1h z_d_0 : svemem_gpr_vec32_ld p10_zer_lo
100001001x1xxxxx010xxxxxxxxxxxxx n 976 SVE ld1h z_s_0 : svemem_gpr_vec32_ld p10_zer_lo
100001001x0xxxxx010xxxxxxxxxxxxx n 976 SVE ld1h z_s_0 : svemem_gpr_vec32_ld p10_zer_lo
10100100101xxxxx010xxxxxxxxxxxxx n 976 SVE ld1h z_msz_bhsd_0 : svemem_gpr_shf p10_zer_lo
10100100110xxxxx010xxxxxxxxxxxxx n 976 SVE ld1h z_s_0 : svemem_gpr_shf p10_zer_lo
10100100111xxxxx010xxxxxxxxxxxxx n 976 SVE ld1h z_d_0 : svemem_gpr_shf p10_zer_lo
1000010001xxxxxx101xxxxxxxxxxxxx n 908 SVE ld1rb z_h_0 : svememx6_b_5 p10_zer_lo
1000010001xxxxxx110xxxxxxxxxxxxx n 908 SVE ld1rb z_s_0 : svememx6_b_5 p10_zer_lo
1000010001xxxxxx111xxxxxxxxxxxxx n 908 SVE ld1rb z_d_0 : svememx6_b_5 p10_zer_lo
Expand Down Expand Up @@ -353,11 +357,15 @@
110001001x0xxxxx000xxxxxxxxxxxxx n 977 SVE ld1sh z_d_0 : svemem_gpr_vec32_ld p10_zer_lo
100001001x1xxxxx000xxxxxxxxxxxxx n 977 SVE ld1sh z_s_0 : svemem_gpr_vec32_ld p10_zer_lo
100001001x0xxxxx000xxxxxxxxxxxxx n 977 SVE ld1sh z_s_0 : svemem_gpr_vec32_ld p10_zer_lo
10100101001xxxxx010xxxxxxxxxxxxx n 977 SVE ld1sh z_msz_bhsd_0 : svemem_gpr_shf p10_zer_lo
10100101000xxxxx010xxxxxxxxxxxxx n 977 SVE ld1sh z_d_0 : svemem_gpr_shf p10_zer_lo
11000101001xxxxx100xxxxxxxxxxxxx n 978 SVE ld1sw z_d_0 : svemem_vec_d_imm5 p10_zer_lo
11000101011xxxxx100xxxxxxxxxxxxx n 978 SVE ld1sw z_d_0 : svemem_gpr_vec64 p10_zer_lo
11000101010xxxxx100xxxxxxxxxxxxx n 978 SVE ld1sw z_d_0 : svemem_gpr_vec64 p10_zer_lo
110001010x1xxxxx000xxxxxxxxxxxxx n 978 SVE ld1sw z_d_0 : svemem_gpr_vec32_ld p10_zer_lo
110001010x0xxxxx000xxxxxxxxxxxxx n 978 SVE ld1sw z_d_0 : svemem_gpr_vec32_ld p10_zer_lo
11000101001xxxxx100xxxxxxxxxxxxx n 978 SVE ld1sw z_d_0 : svemem_vec_d_imm5 p10_zer_lo
10100100100xxxxx010xxxxxxxxxxxxx n 978 SVE ld1sw z_d_0 : svemem_gpr_shf p10_zer_lo
10000101001xxxxx110xxxxxxxxxxxxx n 979 SVE ld1w z_s_0 : svemem_vec_s_imm5 p10_zer_lo
11000101001xxxxx110xxxxxxxxxxxxx n 979 SVE ld1w z_d_0 : svemem_vec_d_imm5 p10_zer_lo
11000101011xxxxx110xxxxxxxxxxxxx n 979 SVE ld1w z_d_0 : svemem_gpr_vec64 p10_zer_lo
Expand All @@ -366,9 +374,22 @@
110001010x0xxxxx010xxxxxxxxxxxxx n 979 SVE ld1w z_d_0 : svemem_gpr_vec32_ld p10_zer_lo
100001010x1xxxxx010xxxxxxxxxxxxx n 979 SVE ld1w z_s_0 : svemem_gpr_vec32_ld p10_zer_lo
100001010x0xxxxx010xxxxxxxxxxxxx n 979 SVE ld1w z_s_0 : svemem_gpr_vec32_ld p10_zer_lo
10000101001xxxxx110xxxxxxxxxxxxx n 979 SVE ld1w z_s_0 : svemem_vec_s_imm5 p10_zer_lo
11000101001xxxxx110xxxxxxxxxxxxx n 979 SVE ld1w z_d_0 : svemem_vec_d_imm5 p10_zer_lo
10100101010xxxxx010xxxxxxxxxxxxx n 979 SVE ld1w z_msz_bhsd_0 : svemem_gpr_shf p10_zer_lo
10100101011xxxxx010xxxxxxxxxxxxx n 979 SVE ld1w z_d_0 : svemem_gpr_shf p10_zer_lo
10100100001xxxxx110xxxxxxxxxxxxx n 967 SVE ld2b z_b_0 z_msz_bhsd_0p1 : svemem_gprs_bhsdx p10_zer_lo
10100101101xxxxx110xxxxxxxxxxxxx n 983 SVE ld2d z_msz_bhsd_0 z_msz_bhsd_0p1 : svemem_msz_gpr_shf p10_zer_lo
10100100101xxxxx110xxxxxxxxxxxxx n 984 SVE ld2h z_msz_bhsd_0 z_msz_bhsd_0p1 : svemem_msz_gpr_shf p10_zer_lo
10100101001xxxxx110xxxxxxxxxxxxx n 985 SVE ld2w z_msz_bhsd_0 z_msz_bhsd_0p1 : svemem_msz_gpr_shf p10_zer_lo
10100100010xxxxx110xxxxxxxxxxxxx n 968 SVE ld3b z_b_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 : svemem_gprs_bhsdx p10_zer_lo
10100101110xxxxx110xxxxxxxxxxxxx n 986 SVE ld3d z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 : svemem_msz_gpr_shf p10_zer_lo
10100100110xxxxx110xxxxxxxxxxxxx n 987 SVE ld3h z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 : svemem_msz_gpr_shf p10_zer_lo
10100101010xxxxx110xxxxxxxxxxxxx n 988 SVE ld3w z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 : svemem_msz_gpr_shf p10_zer_lo
10100100011xxxxx110xxxxxxxxxxxxx n 969 SVE ld4b z_b_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 : svemem_gprs_bhsdx p10_zer_lo
10100101111xxxxx110xxxxxxxxxxxxx n 989 SVE ld4d z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 : svemem_msz_gpr_shf p10_zer_lo
10100100111xxxxx110xxxxxxxxxxxxx n 990 SVE ld4h z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 : svemem_msz_gpr_shf p10_zer_lo
10100101011xxxxx110xxxxxxxxxxxxx n 991 SVE ld4w z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 : svemem_msz_gpr_shf p10_zer_lo
10100100001xxxxx011xxxxxxxxxxxxx n 937 SVE ldff1b z_h_0 : svemem_gpr_shf p10_zer_lo
10100100010xxxxx011xxxxxxxxxxxxx n 937 SVE ldff1b z_s_0 : svemem_gpr_shf p10_zer_lo
10100100011xxxxx011xxxxxxxxxxxxx n 937 SVE ldff1b z_d_0 : svemem_gpr_shf p10_zer_lo
Expand Down Expand Up @@ -430,6 +451,9 @@
100001010x1xxxxx011xxxxxxxxxxxxx n 943 SVE ldff1w z_s_0 : svemem_gpr_vec32_ld p10_zer_lo
100001010x0xxxxx011xxxxxxxxxxxxx n 943 SVE ldff1w z_s_0 : svemem_gpr_vec32_ld p10_zer_lo
10100100000xxxxx110xxxxxxxxxxxxx n 950 SVE ldnt1b z_b_0 : svemem_gprs_b1 p10_zer_lo
10100101100xxxxx110xxxxxxxxxxxxx n 992 SVE ldnt1d z_msz_bhsd_0 : svemem_msz_gpr_shf p10_zer_lo
10100100100xxxxx110xxxxxxxxxxxxx n 993 SVE ldnt1h z_msz_bhsd_0 : svemem_msz_gpr_shf p10_zer_lo
10100101000xxxxx110xxxxxxxxxxxxx n 994 SVE ldnt1w z_msz_bhsd_0 : svemem_msz_gpr_shf p10_zer_lo
1000010110xxxxxx000xxxxxxxx0xxxx n 227 SVE ldr p0 : svemem_gpr_simm9_vl
1000010110xxxxxx010xxxxxxxxxxxxx n 227 SVE ldr z0 : svemem_gpr_simm9_vl
00000100xx000011100xxxxxxxxxxxxx n 902 SVE lsl z_tszl8_bhsd_0 : p10_mrg_lo z_tszl8_bhsd_0 tszl8_imm3_5
Expand Down Expand Up @@ -589,6 +613,7 @@
11100101100xxxxx101xxxxxxxxxxxxx n 981 SVE st1d svemem_gpr_vec64 : z_d_0 p10_lo
11100101101xxxxx1x0xxxxxxxxxxxxx n 981 SVE st1d svemem_gpr_vec32_st : z_d_0 p10_lo
11100101100xxxxx1x0xxxxxxxxxxxxx n 981 SVE st1d svemem_gpr_vec32_st : z_d_0 p10_lo
11100101111xxxxx010xxxxxxxxxxxxx n 981 SVE st1d svemem_gpr_shf : z_msz_bhsd_0 p10_lo
11100100111xxxxx101xxxxxxxxxxxxx n 980 SVE st1h svemem_vec_s_imm5 : z_s_0 p10_lo
11100100110xxxxx101xxxxxxxxxxxxx n 980 SVE st1h svemem_vec_d_imm5 : z_d_0 p10_lo
11100100101xxxxx101xxxxxxxxxxxxx n 980 SVE st1h svemem_gpr_vec64 : z_d_0 p10_lo
Expand All @@ -597,6 +622,9 @@
11100100100xxxxx1x0xxxxxxxxxxxxx n 980 SVE st1h svemem_gpr_vec32_st : z_d_0 p10_lo
11100100111xxxxx1x0xxxxxxxxxxxxx n 980 SVE st1h svemem_gpr_vec32_st : z_s_0 p10_lo
11100100110xxxxx1x0xxxxxxxxxxxxx n 980 SVE st1h svemem_gpr_vec32_st : z_s_0 p10_lo
11100100111xxxxx101xxxxxxxxxxxxx n 980 SVE st1h svemem_vec_s_imm5 : z_s_0 p10_lo
11100100110xxxxx101xxxxxxxxxxxxx n 980 SVE st1h svemem_vec_d_imm5 : z_d_0 p10_lo
111001001xxxxxxx010xxxxxxxxxxxxx n 980 SVE st1h svemem_gpr_shf : z_size21_hsd_0 p10_lo
11100101011xxxxx101xxxxxxxxxxxxx n 982 SVE st1w svemem_vec_s_imm5 : z_s_0 p10_lo
11100101010xxxxx101xxxxxxxxxxxxx n 982 SVE st1w svemem_vec_d_imm5 : z_d_0 p10_lo
11100101001xxxxx101xxxxxxxxxxxxx n 982 SVE st1w svemem_gpr_vec64 : z_d_0 p10_lo
Expand All @@ -605,10 +633,26 @@
11100101000xxxxx1x0xxxxxxxxxxxxx n 982 SVE st1w svemem_gpr_vec32_st : z_d_0 p10_lo
11100101011xxxxx1x0xxxxxxxxxxxxx n 982 SVE st1w svemem_gpr_vec32_st : z_s_0 p10_lo
11100101010xxxxx1x0xxxxxxxxxxxxx n 982 SVE st1w svemem_gpr_vec32_st : z_s_0 p10_lo
11100101011xxxxx101xxxxxxxxxxxxx n 982 SVE st1w svemem_vec_s_imm5 : z_s_0 p10_lo
11100101010xxxxx101xxxxxxxxxxxxx n 982 SVE st1w svemem_vec_d_imm5 : z_d_0 p10_lo
11100101010xxxxx010xxxxxxxxxxxxx n 982 SVE st1w svemem_gpr_shf : z_s_0 p10_lo
11100101011xxxxx010xxxxxxxxxxxxx n 982 SVE st1w svemem_gpr_shf : z_d_0 p10_lo
11100100001xxxxx011xxxxxxxxxxxxx n 970 SVE st2b svemem_gprs_bhsdx : z_b_0 z_msz_bhsd_0p1 p10_lo
11100101101xxxxx011xxxxxxxxxxxxx n 995 SVE st2d svemem_msz_stgpr_shf : z_msz_bhsd_0 z_msz_bhsd_0p1 p10_lo
11100100101xxxxx011xxxxxxxxxxxxx n 996 SVE st2h svemem_msz_stgpr_shf : z_msz_bhsd_0 z_msz_bhsd_0p1 p10_lo
11100101001xxxxx011xxxxxxxxxxxxx n 997 SVE st2w svemem_msz_stgpr_shf : z_msz_bhsd_0 z_msz_bhsd_0p1 p10_lo
11100100010xxxxx011xxxxxxxxxxxxx n 971 SVE st3b svemem_gprs_bhsdx : z_b_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 p10_lo
11100101110xxxxx011xxxxxxxxxxxxx n 998 SVE st3d svemem_msz_stgpr_shf : z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 p10_lo
11100100110xxxxx011xxxxxxxxxxxxx n 999 SVE st3h svemem_msz_stgpr_shf : z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 p10_lo
11100101010xxxxx011xxxxxxxxxxxxx n 1000 SVE st3w svemem_msz_stgpr_shf : z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 p10_lo
11100100011xxxxx011xxxxxxxxxxxxx n 972 SVE st4b svemem_gprs_bhsdx : z_b_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 p10_lo
11100101111xxxxx011xxxxxxxxxxxxx n 1001 SVE st4d svemem_msz_stgpr_shf : z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 p10_lo
11100100111xxxxx011xxxxxxxxxxxxx n 1002 SVE st4h svemem_msz_stgpr_shf : z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 p10_lo
11100101011xxxxx011xxxxxxxxxxxxx n 1003 SVE st4w svemem_msz_stgpr_shf : z_msz_bhsd_0 z_msz_bhsd_0p1 z_msz_bhsd_0p2 z_msz_bhsd_0p3 p10_lo
11100100000xxxxx011xxxxxxxxxxxxx n 952 SVE stnt1b svemem_gprs_b1 : z_b_0 p10_lo
11100101100xxxxx011xxxxxxxxxxxxx n 1004 SVE stnt1d svemem_msz_stgpr_shf : z_msz_bhsd_0 p10_lo
11100100100xxxxx011xxxxxxxxxxxxx n 1005 SVE stnt1h svemem_msz_stgpr_shf : z_msz_bhsd_0 p10_lo
11100101000xxxxx011xxxxxxxxxxxxx n 1006 SVE stnt1w svemem_msz_stgpr_shf : z_msz_bhsd_0 p10_lo
1110010110xxxxxx000xxxxxxxx0xxxx n 457 SVE str svemem_gpr_simm9_vl : p0
1110010110xxxxxx010xxxxxxxxxxxxx n 457 SVE str svemem_gpr_simm9_vl : z0
00000100xx1xxxxx000001xxxxxxxxxx n 470 SVE sub z0 : z5 z16 bhsd_sz
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2 changes: 2 additions & 0 deletions core/ir/aarch64/codec_sve2.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -35,3 +35,5 @@
# generation.

# Instruction definitions:


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