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i#3044 AArch64 SVE codec: Add memory scalar+vector 32-bit offset (#5893)
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This patch adds the appropriate macros, tests and codec entries to
encode the following variants:
LD1B    { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend>]
LD1B    { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <extend>]
LD1D    { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend> #3]
LD1D    { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend>]
LD1H    { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend> #1]
LD1H    { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend>]
LD1H    { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <extend> #1]
LD1H    { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <extend>]
LD1SB   { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend>]
LD1SB   { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <extend>]
LD1SH   { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend> #1]
LD1SH   { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend>]
LD1SH   { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <extend> #1]
LD1SH   { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <extend>]
LD1SW   { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend> #2]
LD1SW   { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend>]
LD1W    { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend> #2]
LD1W    { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend>]
LD1W    { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <extend> #2]
LD1W    { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <extend>]
LDFF1B  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend>]
LDFF1B  { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <extend>]
LDFF1D  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend> #3]
LDFF1D  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend>]
LDFF1H  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend> #1]
LDFF1H  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend>]
LDFF1H  { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <extend> #1]
LDFF1H  { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <extend>]
LDFF1SB { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend>]
LDFF1SB { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <extend>]
LDFF1SH { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend> #1]
LDFF1SH { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend>]
LDFF1SH { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <extend> #1]
LDFF1SH { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <extend>]
LDFF1SW { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend> #2]
LDFF1SW { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend>]
LDFF1W  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend> #2]
LDFF1W  { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <extend>]
LDFF1W  { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <extend> #2]
LDFF1W  { <Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <extend>]
PRFB    <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <extend>]
PRFB    <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <extend>]
PRFD    <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <extend> #3]
PRFD    <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <extend> #3]
PRFH    <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <extend> #1]
PRFH    <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <extend> #1]
PRFW    <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <extend> #2]
PRFW    <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <extend> #2]
ST1B    { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <extend>]
ST1B    { <Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <extend>]
ST1D    { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <extend> #3]
ST1D    { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <extend>]
ST1H    { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <extend> #1]
ST1H    { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <extend>]
ST1H    { <Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <extend> #1]
ST1H    { <Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <extend>]
ST1W    { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <extend> #2]
ST1W    { <Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <extend>]
ST1W    { <Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <extend> #2]
ST1W    { <Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <extend>]

Issue: #3044
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@jackgallagher-arm
jackgallagher-arm authored Mar 3, 2023
1 parent 280c399 commit 6a1d605
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Showing 6 changed files with 4,346 additions and 29 deletions.
88 changes: 88 additions & 0 deletions core/ir/aarch64/codec.c
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Original file line number Diff line number Diff line change
Expand Up @@ -6856,6 +6856,48 @@ encode_opnd_svemem_gprs_bhsdx(uint enc, int opcode, byte *pc, opnd_t opnd,
enc_out);
}

static inline bool
encode_svemem_gpr_vec_xs(uint enc, uint pos, opnd_t opnd, OUT uint *enc_out)
{
const dr_extend_type_t mod = opnd_get_index_extend(opnd, NULL, NULL);

uint xs;
switch (mod) {
case DR_EXTEND_UXTW: xs = 0; break;
case DR_EXTEND_SXTW: xs = 1; break;
default: return false;
}

*enc_out |= (xs << pos);

return true;
}

/* SVE memory address (32-bit offset) [<Xn|SP>, <Zm>.<T>, <mod> <amount>] */
static inline bool
decode_opnd_svemem_gpr_vec32_st(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
{
const aarch64_reg_offset element_size = TEST(1u << 22, enc) ? SINGLE_REG : DOUBLE_REG;
const aarch64_reg_offset msz = BITS(enc, 24, 23);
const bool scaled = TEST(1u << 21, enc);

const dr_extend_type_t mod = TEST(1u << 14, enc) ? DR_EXTEND_SXTW : DR_EXTEND_UXTW;

return decode_svemem_gpr_vec(enc, element_size, mod, msz, scaled, false, opnd);
}

static inline bool
encode_opnd_svemem_gpr_vec32_st(uint enc, int opcode, byte *pc, opnd_t opnd,
OUT uint *enc_out)
{
const aarch64_reg_offset element_size = TEST(1u << 22, enc) ? SINGLE_REG : DOUBLE_REG;
const uint msz = BITS(enc, 24, 23);
const bool scaled = TEST(1u << 21, enc);

return encode_svemem_gpr_vec(enc, element_size, msz, scaled, opnd, enc_out) &&
encode_svemem_gpr_vec_xs(enc, 14, opnd, enc_out);
}

static inline bool
decode_opnd_z_msz_bhsd_0p1(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
{
Expand Down Expand Up @@ -7414,6 +7456,52 @@ encode_opnd_mem12(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_out
return encode_opnd_mem12_scale(extract_uint(enc, 30, 2), false, opnd, enc_out);
}

/* SVE prefetch memory address (32-bit offset) [<Xn|SP>, <Zm>.<T>, <mod>{ <amount>}] */
static inline bool
decode_opnd_sveprf_gpr_vec32(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
{
const aarch64_reg_offset element_size = BITS(enc, 31, 30);
const dr_extend_type_t mod = TEST(1u << 22, enc) ? DR_EXTEND_SXTW : DR_EXTEND_UXTW;
const aarch64_reg_offset msz = BITS(enc, 14, 13);

return decode_svemem_gpr_vec(enc, element_size, mod, msz, msz > 0, true, opnd);
}

static inline bool
encode_opnd_sveprf_gpr_vec32(uint enc, int opcode, byte *pc, opnd_t opnd,
OUT uint *enc_out)
{
const aarch64_reg_offset element_size = BITS(enc, 31, 30);
const aarch64_reg_offset msz = BITS(enc, 14, 13);

return encode_svemem_gpr_vec(enc, element_size, msz, msz > 0, opnd, enc_out) &&
encode_svemem_gpr_vec_xs(enc, 22, opnd, enc_out);
}

/* SVE memory address (32-bit offset) [<Xn|SP>, <Zm>.<T>, <mod> <amount>] */
static inline bool
decode_opnd_svemem_gpr_vec32_ld(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
{
const aarch64_reg_offset element_size = BITS(enc, 31, 30);
const aarch64_reg_offset msz = BITS(enc, 24, 23);
const bool scaled = TEST(1u << 21, enc);
const dr_extend_type_t mod = TEST(1u << 22, enc) ? DR_EXTEND_SXTW : DR_EXTEND_UXTW;

return decode_svemem_gpr_vec(enc, element_size, mod, msz, scaled, false, opnd);
}

static inline bool
encode_opnd_svemem_gpr_vec32_ld(uint enc, int opcode, byte *pc, opnd_t opnd,
OUT uint *enc_out)
{
const aarch64_reg_offset element_size = BITS(enc, 31, 30);
const aarch64_reg_offset msz = BITS(enc, 24, 23);
const bool scaled = TEST(1u << 21, enc);

return encode_svemem_gpr_vec(enc, element_size, msz, scaled, opnd, enc_out) &&
encode_svemem_gpr_vec_xs(enc, 22, opnd, enc_out);
}

/* mem7post: post-indexed mem7, so offset is zero */

static inline bool
Expand Down
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