Merge branch 'master' into i5199-warmup-trace

DynamoRIO · Jul 11, 2023 · 0d1ef4d · 0d1ef4d
2 parents 81a8225 + bb2ff60
commit 0d1ef4d
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Showing 11 changed files with 1,966 additions and 113 deletions.
diff --git a/core/ir/aarch64/codec.c b/core/ir/aarch64/codec.c
@@ -6762,6 +6762,18 @@ encode_opnd_p_size_bhs_0(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *
     return encode_sized_p(0, 22, BYTE_REG, SINGLE_REG, opnd, enc_out);
 }
 
+static inline bool
+decode_opnd_p_size_bh_0(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
+{
+    return decode_sized_p(0, 22, BYTE_REG, HALF_REG, enc, pc, opnd);
+}
+
+static inline bool
+encode_opnd_p_size_bh_0(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_out)
+{
+    return encode_sized_p(0, 22, BYTE_REG, HALF_REG, opnd, enc_out);
+}
+
 static inline bool
 decode_opnd_p_size_hsd_0(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
 {
@@ -6972,6 +6984,18 @@ encode_opnd_z_size_bhs_5(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *
     return encode_sized_z(5, 22, BYTE_REG, SINGLE_REG, 0, 0, opnd, enc_out);
 }
 
+static inline bool
+decode_opnd_z_size_bh_5(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
+{
+    return decode_sized_z(5, 22, BYTE_REG, HALF_REG, 0, 0, enc, pc, opnd);
+}
+
+static inline bool
+encode_opnd_z_size_bh_5(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_out)
+{
+    return encode_sized_z(5, 22, BYTE_REG, HALF_REG, 0, 0, opnd, enc_out);
+}
+
 static inline bool
 decode_opnd_z_sizep1_bhs_5(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
 {
@@ -7225,6 +7249,18 @@ encode_opnd_z_size_bhsd_16(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint
     return encode_sized_z(16, 22, BYTE_REG, DOUBLE_REG, 0, 0, opnd, enc_out);
 }
 
+static inline bool
+decode_opnd_z_size_bh_16(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
+{
+    return decode_sized_z(16, 22, BYTE_REG, HALF_REG, 0, 0, enc, pc, opnd);
+}
+
+static inline bool
+encode_opnd_z_size_bh_16(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_out)
+{
+    return encode_sized_z(16, 22, BYTE_REG, HALF_REG, 0, 0, opnd, enc_out);
+}
+
 static inline bool
 decode_opnd_z_size_sd_16(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
 {
@@ -7814,6 +7850,47 @@ encode_opnd_z3_msz_bhsd_16(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint
     return true;
 }
 
+static inline bool
+decode_opnd_z4_msz_bhsd_16(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
+{
+    aarch64_reg_offset bit_size = extract_uint(enc, 23, 2);
+    if (bit_size < BYTE_REG)
+        return false;
+    if (bit_size > DOUBLE_REG)
+        return false;
+
+    return decode_single_sized(DR_REG_Z0, DR_REG_Z15, 16, 4, bit_size, 0, enc, opnd);
+}
+
+static inline bool
+encode_opnd_z4_msz_bhsd_16(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_out)
+{
+    IF_RETURN_FALSE(!opnd_is_element_vector_reg(opnd));
+
+    const aarch64_reg_offset size = get_vector_element_reg_offset(opnd);
+    if (size == NOT_A_REG)
+        return false;
+
+    if (size > DOUBLE_REG)
+        return false;
+    if (size < BYTE_REG)
+        return false;
+
+    opnd_size_t reg_size = OPSZ_SCALABLE;
+
+    uint reg_number;
+    if (!is_vreg(&reg_size, &reg_number, opnd))
+        return false;
+
+    if (reg_number > 15)
+        return false;
+
+    *enc_out |= (reg_number << 16);
+    *enc_out |= (size << 23);
+
+    return true;
+}
+
 static inline bool
 decode_opnd_z_msz_bhsd_16(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
 {

diff --git a/core/ir/aarch64/codec_sve.txt b/core/ir/aarch64/codec_sve.txt
@@ -835,8 +835,10 @@
 0000010011010101101xxxxxxxxxxxxx  n   804  SVE     uxtw          z_d_0 : p10_mrg_lo z_d_5
 00000101xx10xxxx0100100xxxx0xxxx  n   557  SVE     uzp1  p_size_bhsd_0 : p_size_bhsd_5 p_size_bhsd_16
 00000101xx1xxxxx011010xxxxxxxxxx  n   557  SVE     uzp1  z_size_bhsd_0 : z_size_bhsd_5 z_size_bhsd_16
+00000101101xxxxx000010xxxxxxxxxx  n   557  F64MM   uzp1          z_q_0 : z_q_5 z_q_16
 00000101xx10xxxx0100110xxxx0xxxx  n   558  SVE     uzp2  p_size_bhsd_0 : p_size_bhsd_5 p_size_bhsd_16
 00000101xx1xxxxx011011xxxxxxxxxx  n   558  SVE     uzp2  z_size_bhsd_0 : z_size_bhsd_5 z_size_bhsd_16
+00000101101xxxxx000011xxxxxxxxxx  n   558  F64MM   uzp2          z_q_0 : z_q_5 z_q_16
 00100101xx1xxxxx000001xxxxx1xxxx  w   877  SVE  whilele  p_size_bhsd_0 : w5 w16
 00100101xx1xxxxx000101xxxxx1xxxx  w   877  SVE  whilele  p_size_bhsd_0 : x5 x16
 00100101xx1xxxxx000011xxxxx0xxxx  w   878  SVE  whilelo  p_size_bhsd_0 : w5 w16
@@ -848,6 +850,7 @@
 00100101001010001001000xxxx00000  n   820  SVE    wrffr                : p_b_5
 00000101xx10xxxx0100000xxxx0xxxx  n   565  SVE     zip1  p_size_bhsd_0 : p_size_bhsd_5 p_size_bhsd_16
 00000101xx1xxxxx011000xxxxxxxxxx  n   565  SVE     zip1  z_size_bhsd_0 : z_size_bhsd_5 z_size_bhsd_16
+00000101101xxxxx000000xxxxxxxxxx  n   565  F64MM   zip1          z_q_0 : z_q_5 z_q_16
 00000101101xxxxx000001xxxxxxxxxx  n   566  SVE     zip2          z_q_0 : z_q_5 z_q_16
 00000101xx10xxxx0100010xxxx0xxxx  n   566  SVE     zip2  p_size_bhsd_0 : p_size_bhsd_5 p_size_bhsd_16
 00000101xx1xxxxx011001xxxxxxxxxx  n   566  SVE     zip2  z_size_bhsd_0 : z_size_bhsd_5 z_size_bhsd_16
diff --git a/core/ir/aarch64/codec_sve2.txt b/core/ir/aarch64/codec_sve2.txt
@@ -56,7 +56,11 @@
 00000100101xxxxx001111xxxxxxxxxx  n   1066 SVE2     bsl2n          z_d_0 : z_d_0 z_d_16 z_d_5
 01000101xx00000011011xxxxxxxxxxx  n   1161 SVE2      cadd  z_size_bhsd_0 : z_size_bhsd_0 z_size_bhsd_5 imm1_ew_10
 01000100xx0xxxxx0001xxxxxxxxxxxx  n   1162 SVE2      cdot    z_size_sd_0 : z_size_sd_0 z_sizep2_bh_5 z_sizep2_bh_16 imm2_nesw_10
+01000100111xxxxx0100xxxxxxxxxxxx  n   1162 SVE2      cdot          z_d_0 : z_d_0 z_msz_bhsd_5 z4_msz_bhsd_16 i1_index_20 imm2_nesw_10
+01000100101xxxxx0100xxxxxxxxxxxx  n   1162 SVE2      cdot          z_s_0 : z_s_0 z_b_5 z3_b_16 i2_index_19 imm2_nesw_10
 01000100xx0xxxxx0010xxxxxxxxxxxx  n   1163 SVE2      cmla  z_size_bhsd_0 : z_size_bhsd_0 z_size_bhsd_5 z_size_bhsd_16 imm2_nesw_10
+01000100101xxxxx0110xxxxxxxxxxxx  n   1163 SVE2      cmla   z_msz_bhsd_0 : z_msz_bhsd_0 z_msz_bhsd_5 z3_msz_bhsd_16 i2_index_19 imm2_nesw_10
+01000100111xxxxx0110xxxxxxxxxxxx  n   1163 SVE2      cmla          z_s_0 : z_s_0 z_s_5 z4_s_16 i1_index_20 imm2_nesw_10
 00000100001xxxxx001110xxxxxxxxxx  n   600  SVE2      eor3          z_d_0 : z_d_0 z_d_16 z_d_5
 01000101xx0xxxxx100100xxxxxxxxxx  n   1078 SVE2     eorbt  z_size_bhsd_0 : z_size_bhsd_0 z_size_bhsd_5 z_size_bhsd_16
 01000101xx0xxxxx100101xxxxxxxxxx  n   1079 SVE2     eortb  z_size_bhsd_0 : z_size_bhsd_0 z_size_bhsd_5 z_size_bhsd_16
@@ -87,7 +91,9 @@
 11000100100xxxxx100xxxxxxxxxxxxx  n   1187 SVE2   ldnt1sh          z_d_0 : svemem_vec_sd_gpr16 p10_zer_lo
 10000100100xxxxx100xxxxxxxxxxxxx  n   1187 SVE2   ldnt1sh          z_s_0 : svemem_vec_sd_gpr16 p10_zer_lo
 11000101000xxxxx100xxxxxxxxxxxxx  n   1188 SVE2   ldnt1sw          z_d_0 : svemem_vec_sd_gpr16 p10_zer_lo
+01000101xx1xxxxx100xxxxxxxx0xxxx  w   1189 SVE2     match    p_size_bh_0 : p10_zer_lo z_size_bh_5 z_size_bh_16
 00000100111xxxxx001111xxxxxxxxxx  n   1072 SVE2      nbsl          z_d_0 : z_d_0 z_d_16 z_d_5
+01000101xx1xxxxx100xxxxxxxx1xxxx  w   1190 SVE2    nmatch    p_size_bh_0 : p10_zer_lo z_size_bh_5 z_size_bh_16
 00000100001xxxxx011001xxxxxxxxxx  n   328  SVE2      pmul   z_msz_bhsd_0 : z_msz_bhsd_5 z_msz_bhsd_16
 01000101xx0xxxxx011010xxxxxxxxxx  n   1084 SVE2    pmullb    z_size_hd_0 : z_sizep1_bs_5 z_sizep1_bs_16
 01000101xx0xxxxx011011xxxxxxxxxx  n   1085 SVE2    pmullt    z_size_hd_0 : z_sizep1_bs_5 z_sizep1_bs_16
@@ -169,6 +175,8 @@
 01000100101xxxxx1110x1xxxxxxxxxx  n   1112 SVE2  sqdmullt          z_s_0 : z_msz_bhsd_5 z3_msz_bhsd_16 i3_index_11
 01000100xx001001101xxxxxxxxxxxxx  n   411  SVE2     sqneg  z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_5
 01000100xx0xxxxx0011xxxxxxxxxxxx  n   1169 SVE2 sqrdcmlah  z_size_bhsd_0 : z_size_bhsd_0 z_size_bhsd_5 z_size_bhsd_16 imm2_nesw_10
+01000100101xxxxx0111xxxxxxxxxxxx  n   1169 SVE2 sqrdcmlah   z_msz_bhsd_0 : z_msz_bhsd_0 z_msz_bhsd_5 z3_msz_bhsd_16 i2_index_19 imm2_nesw_10
+01000100111xxxxx0111xxxxxxxxxxxx  n   1169 SVE2 sqrdcmlah          z_s_0 : z_s_0 z_s_5 z4_s_16 i1_index_20 imm2_nesw_10
 01000100xx0xxxxx011100xxxxxxxxxx  n   412  SVE2  sqrdmlah  z_size_bhsd_0 : z_size_bhsd_0 z_size_bhsd_5 z_size_bhsd_16
 01000100111xxxxx000100xxxxxxxxxx  n   412  SVE2  sqrdmlah          z_d_0 : z_d_0 z_d_5 z4_d_16 i1_index_20
 010001000x1xxxxx000100xxxxxxxxxx  n   412  SVE2  sqrdmlah          z_h_0 : z_h_0 z_h_5 z3_h_16 i3_index_19
@@ -264,10 +272,12 @@
 01000100xx011111100xxxxxxxxxxxxx  n   1154 SVE2    uqsubr  z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5
 010001010x1xx000010010xxxxxxxxxx  n   1143 SVE2    uqxtnb  z_wtszl19_bhsd_0 : z_wtszl19p1_bhsd_5
 010001010x1xx000010011xxxxxxxxxx  n   1144 SVE2    uqxtnt  z_wtszl19_bhsd_0 : z_wtszl19_bhsd_0 z_wtszl19p1_bhsd_5
+0100010010000000101xxxxxxxxxxxxx  n   541  SVE2    urecpe          z_s_0 : p10_mrg_lo z_s_5
 01000100xx010101100xxxxxxxxxxxxx  n   542  SVE2    urhadd  z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5
 01000100xx000011100xxxxxxxxxxxxx  n   543  SVE2     urshl  z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5
 01000100xx000111100xxxxxxxxxxxxx  n   1155 SVE2    urshlr  z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5
 00000100xx001101100xxxxxxxxxxxxx  n   544  SVE2     urshr  z_tszl8_bhsd_0 : p10_mrg_lo z_tszl8_bhsd_0 tszl8_imm3_5p1
+0100010010000001101xxxxxxxxxxxxx  n   545  SVE2   ursqrte          z_s_0 : p10_mrg_lo z_s_5
 01000101xx0xxxxx111011xxxxxxxxxx  n   546  SVE2     ursra  z_tszl19_bhsd_0 : z_tszl19_bhsd_0 z_tszl19_bhsd_5 tszl19_imm3_16p1
 010001010x0xxxxx101010xxxxxxxxxx  n   1184 SVE2    ushllb  z_tszl19p1_hsd_0 : z_tszl19_bhs_5 tszl19lo_imm3_16
 010001010x0xxxxx101011xxxxxxxxxx  n   1185 SVE2    ushllt  z_tszl19p1_hsd_0 : z_tszl19_bhs_5 tszl19lo_imm3_16
@@ -277,4 +287,14 @@
 01000101xx0xxxxx000111xxxxxxxxxx  n   1136 SVE2    usublt   z_size_hsd_0 : z_sizep1_bhs_5 z_sizep1_bhs_16
 01000101xx0xxxxx010110xxxxxxxxxx  n   1137 SVE2    usubwb   z_size_hsd_0 : z_size_hsd_5 z_sizep1_bhs_16
 01000101xx0xxxxx010111xxxxxxxxxx  n   1138 SVE2    usubwt   z_size_hsd_0 : z_size_hsd_5 z_sizep1_bhs_16
+00100101xx1xxxxx000000xxxxx0xxxx  w   1191 SVE2   whilege  p_size_bhsd_0 : w5 w16
+00100101xx1xxxxx000100xxxxx0xxxx  w   1191 SVE2   whilege  p_size_bhsd_0 : x5 x16
+00100101xx1xxxxx000000xxxxx1xxxx  w   1192 SVE2   whilegt  p_size_bhsd_0 : w5 w16
+00100101xx1xxxxx000100xxxxx1xxxx  w   1192 SVE2   whilegt  p_size_bhsd_0 : x5 x16
+00100101xx1xxxxx000010xxxxx1xxxx  w   1193 SVE2   whilehi  p_size_bhsd_0 : w5 w16
+00100101xx1xxxxx000110xxxxx1xxxx  w   1193 SVE2   whilehi  p_size_bhsd_0 : x5 x16
+00100101xx1xxxxx000010xxxxx0xxxx  w   1194 SVE2   whilehs  p_size_bhsd_0 : w5 w16
+00100101xx1xxxxx000110xxxxx0xxxx  w   1194 SVE2   whilehs  p_size_bhsd_0 : x5 x16
+00100101xx1xxxxx001100xxxxx1xxxx  w   1195 SVE2   whilerw  p_size_bhsd_0 : x5 x16
+00100101xx1xxxxx001100xxxxx0xxxx  w   1196 SVE2   whilewr  p_size_bhsd_0 : x5 x16
 00000100xx1xxxxx001101xxxxxxxxxx  n   604  SVE2       xar  z_tszl19_bhsd_0 : z_tszl19_bhsd_0 z_tszl19_bhsd_5 tszl19_imm3_16p1