Merge pull request openhwgroup#539 from davidharrishmc/dev

PC logic moved from privileged unit to IFU.  Adopting more of Zicboz, Zcb, E tests from riscv-arch-test

bin/wally-tool-chain-install.sh

@@ -69,9 +69,9 @@ cd $RISCV
 git clone https://github.com/riscv/riscv-gnu-toolchain
 cd riscv-gnu-toolchain
 # Temporarily use the following commands until gcc-13 is part of riscv-gnu-toolchain (issue #1249)
-git clone https://github.com/gcc-mirror/gcc -b releases/gcc-13 gcc-13
-./configure --prefix=/opt/riscv --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" --with-gcc-src=`pwd`/gcc-13
-#./configure --prefix=${RISCV} --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;"
+#git clone https://github.com/gcc-mirror/gcc -b releases/gcc-13 gcc-13
+#./configure --prefix=/opt/riscv --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" --with-gcc-src=`pwd`/gcc-13
+./configure --prefix=${RISCV} --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;"
 make -j ${NUM_THREADS}
 
 # elf2hex (https://github.com/sifive/elf2hex)
@@ -151,20 +151,21 @@ sudo make install
 
 cd $RISCV
 opam init -y --disable-sandboxing
-opam switch create ocaml-base-compiler.4.08.0
+opam switch create 5.1.0
 opam install sail -y 
 
 eval $(opam config env)
 git clone https://github.com/riscv/sail-riscv.git
 cd sail-riscv
 # For now, use checkout that is stable for Wally
-git checkout 72b2516d10d472ac77482fd959a9401ce3487f60
+#git checkout 72b2516d10d472ac77482fd959a9401ce3487f60  # not new enough for Zicboz?
 make -j ${NUM_THREADS}
 ARCH=RV32 make -j ${NUM_THREADS}
 sudo ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64
 sudo ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32
 
-sudo pip3 install testresources
+# riscof
+sudo pip3 install -U testresources riscv_config
 pip3 install git+https://github.com/riscv/riscof.git
 
 # Download OSU Skywater 130 cell library

config/rv32gc/config.vh

@@ -35,7 +35,7 @@ localparam XLEN = 32'd32;
 // IEEE 754 compliance
 localparam IEEE754 = 0;
 
-localparam MISA = (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 <<3 | 1 << 5);
+localparam MISA = (32'h00000104 | 1 << 1 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 <<3 | 1 << 5);
 localparam ZICSR_SUPPORTED = 1;
 localparam ZIFENCEI_SUPPORTED = 1;
 localparam COUNTERS = 12'd32;

config/rv64gc/config.vh

@@ -34,7 +34,7 @@ localparam XLEN = 32'd64;
 localparam IEEE754 = 0;
 
 // MISA RISC-V configuration per specification
-localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0);
+localparam MISA = (32'h00000104 | 1 << 1 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0);
 localparam ZICSR_SUPPORTED = 1;
 localparam ZIFENCEI_SUPPORTED = 1;
 localparam COUNTERS = 12'd32;

sim/imperas.ic

@@ -79,7 +79,7 @@
 #
 # SVxx Memory 0x0000000000 0x7FFFFFFFFF
 #
---callcommand refRoot/cpu/setPMA -lo 0x0000000000 -hi 0x7FFFFFFFFF -attributes " ------ ---- " # INITIAL
+--callcommand refRoot/cpu/setPMA -lo 0x0000000000 -hi 0x7FFFFFFFFF -attributes " ---a-- ---- " # INITIAL
 --callcommand refRoot/cpu/setPMA -lo 0x0000001000 -hi 0x0000001FFF -attributes " r-x-A- 1248 " # BOOTROM
 --callcommand refRoot/cpu/setPMA -lo 0x0000012100 -hi 0x000001211F -attributes " rw-aA- --48 " # SDC
 --callcommand refRoot/cpu/setPMA -lo 0x0002000000 -hi 0x000200FFFF -attributes " rw-aA- 1248 " # CLINT

sim/regression-wally

@@ -107,7 +107,7 @@ for test in tests32i:
   configs.append(tc)
 
 
-tests32e = ["wally32e"] 
+tests32e = ["arch32e"] 
 for test in tests32e:
   tc = TestCase(
         name=test,

src/ieu/alu.sv

@@ -69,7 +69,7 @@ module alu import cvw::*; #(parameter cvw_t P, parameter WIDTH) (
   assign LTU = ~Carry;
 
   // Select appropriate ALU Result
-  always_comb begin
+  always_comb 
     case (ALUSelect)                                
       3'b000: FullResult = Sum;                           // add or sub (including address generation)
       3'b001: FullResult = Shift;                         // sll, sra, or srl
@@ -80,7 +80,6 @@ module alu import cvw::*; #(parameter cvw_t P, parameter WIDTH) (
       3'b110: FullResult = A | CondMaskInvB;              // or, orn, bset
       3'b111: FullResult = A & CondMaskInvB;              // and, bclr
     endcase
-  end
 
   // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits
   if (WIDTH == 64)  assign PreALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult;

src/ifu/ifu.sv

@@ -56,8 +56,9 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   output logic                 BPWrongM,                                 // Prediction is wrong
   // Mem
   output logic                 CommittedF,                               // I$ or bus memory operation started, delay interrupts
-  input  logic [P.XLEN-1:0]    UnalignedPCNextF,                         // The next PCF, but not aligned to 2 bytes. 
-  output logic [P.XLEN-1:0]    PC2NextF,                                 // Selected PC between branch prediction and next valid PC if CSRWriteFence
+  input  logic [P.XLEN-1:0]    EPCM,                                     // Exception Program counter from privileged unit
+  input  logic [P.XLEN-1:0]    TrapVectorM,                              // Trap vector, from privileged unit
+  input  logic                 RetM, TrapM,                              // return instruction, or trap
   output logic [31:0]          InstrD,                                   // The decoded instruction in Decode stage
   output logic [31:0]          InstrM,                                   // The decoded instruction in Memory stage
   output logic [31:0]          InstrOrigM,                               // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL
@@ -100,6 +101,9 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   localparam [31:0]            nop = 32'h00000013;                       // instruction for NOP
 
   logic [P.XLEN-1:0]           PCNextF;                                  // Next PCF, selected from Branch predictor, Privilege, or PC+2/4
+  logic [P.XLEN-1:0]           PC1NextF;                                 // Branch predictor next PCF
+  logic [P.XLEN-1:0]           PC2NextF;                                 // Selected PC between branch prediction and next valid PC if CSRWriteFence
+  logic [P.XLEN-1:0]           UnalignedPCNextF;                         // The next PCF, but not aligned to 2 bytes. 
   logic                        BranchMisalignedFaultE;                   // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed)
   logic [P.XLEN-1:0]           PCPlus2or4F;                              // PCF + 2 (CompressedF) or PCF + 4 (Non-compressed)
   logic [P.XLEN-1:0]           PCSpillNextF;                             // Next PCF after possible + 2 to handle spill
@@ -128,7 +132,6 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   logic                        IFUCacheBusStallF;                        // EIther I$ or bus busy with multicycle operation
   logic                        GatedStallD;                              // StallD gated by selected next spill
   // branch predictor signal
-  logic [P.XLEN-1:0]           PC1NextF;                                 // Branch predictor next PCF
   logic                        BusCommittedF;                            // Bus memory operation in flight, delay interrupts
   logic                        CacheCommittedF;                          // I$ memory operation started, delay interrupts
   logic                        SelIROM;                                  // PMA indicates instruction address is in the IROM
@@ -300,20 +303,25 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
     mux2 #(P.XLEN) pcmux2(.d0(PC1NextF), .d1(NextValidPCE), .s(CSRWriteFenceM),.y(PC2NextF));
   else assign PC2NextF = PC1NextF;
 
+  mux3 #(P.XLEN) pcmux3(PC2NextF, EPCM, TrapVectorM, {TrapM, RetM}, UnalignedPCNextF);
   mux2 #(P.XLEN) pcresetmux({UnalignedPCNextF[P.XLEN-1:1], 1'b0}, P.RESET_VECTOR[P.XLEN-1:0], reset, PCNextF);
   flopen #(P.XLEN) pcreg(clk, ~StallF | reset, PCNextF, PCF);
 
   // pcadder
   // add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32
   assign PCPlus4F = PCF[P.XLEN-1:2] + 1; // add 4 to PC
-  // choose PC+2 or PC+4 based on CompressedF, which arrives later. 
-  // Speeds up critical path as compared to selecting adder input based on CompressedF
 
-  always_comb
-    if (CompressedF) // add 2
-      if (PCF[1]) PCPlus2or4F = {PCPlus4F, 2'b00}; 
-      else        PCPlus2or4F = {PCF[P.XLEN-1:2], 2'b10};
-    else          PCPlus2or4F = {PCPlus4F, PCF[1:0]}; // add 4
+  if (P.COMPRESSED_SUPPORTED) begin: pcadd
+    // choose PC+2 or PC+4 based on CompressedF, which arrives later. 
+    // Speeds up critical path as compared to selecting adder input based on CompressedF
+    always_comb
+      if (CompressedF) // add 2
+        if (PCF[1]) PCPlus2or4F = {PCPlus4F, 2'b00}; 
+        else        PCPlus2or4F = {PCF[P.XLEN-1:2], 2'b10};
+      else          PCPlus2or4F = {PCPlus4F, PCF[1:0]}; // add 4
+  end else begin: pcadd
+    assign PCPlus2or4F = {PCPlus4F, PCF[1:0]}; // always add 4 if compressed instructions are not supported
+  end
 
   ////////////////////////////////////////////////////////////////////////////////////////////////
   // Branch and Jump Predictor

src/privileged/csr.sv

@@ -34,7 +34,7 @@ module csr import cvw::*;  #(parameter cvw_t P) (
   input  logic                     StallE, StallM, StallW,
   input  logic [31:0]              InstrM,                    // current instruction
   input  logic [31:0]              InstrOrigM,                // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL
-  input  logic [P.XLEN-1:0]        PCM, PC2NextF,             // program counter, next PC going to trap/return logic
+  input  logic [P.XLEN-1:0]        PCM,                       // program counter, next PC going to trap/return logic
   input  logic [P.XLEN-1:0]        SrcAM, IEUAdrM,            // SrcA and memory address from IEU
   input  logic                     CSRReadM, CSRWriteM,       // read or write CSR
   input  logic                     TrapM,                     // trap is occurring
@@ -86,9 +86,11 @@ module csr import cvw::*;  #(parameter cvw_t P) (
   output logic [3:0]               ENVCFG_CBE,
   output logic                     ENVCFG_PBMTE,              // Page-based memory type enable
   output logic                     ENVCFG_ADUE,               // HPTW A/D Update enable
+  // PC logic output from privileged unit to IFU                                  
+  output logic [P.XLEN-1:0]        EPCM,                      // Exception Program counter to IFU PC logic
+  output logic [P.XLEN-1:0]        TrapVectorM,               // Trap vector, to IFU PC logic
   //
   output logic [P.XLEN-1:0]        CSRReadValW,               // value read from CSR
-  output logic [P.XLEN-1:0]        UnalignedPCNextF,          // Next PC, accounting for traps and returns
   output logic                     IllegalCSRAccessM,         // Illegal CSR access: CSR doesn't exist or is inaccessible at this privilege level
   output logic                     BigEndianM                 // memory access is big-endian based on privilege mode and STATUS register endian fields
 );
@@ -117,10 +119,8 @@ module csr import cvw::*;  #(parameter cvw_t P) (
   logic                    IllegalCSRMWriteReadonlyM;
   logic [P.XLEN-1:0]       CSRReadVal2M;
   logic [11:0]             MIP_REGW_writeable;
-  logic [P.XLEN-1:0]       TVecM, TrapVectorM, NextFaultMtvalM;
+  logic [P.XLEN-1:0]       TVecM,NextFaultMtvalM;
   logic                    MTrapM, STrapM;
-  logic [P.XLEN-1:0]       EPC;
-  logic                    RetM;
   logic                    SelMtvecM;
   logic [P.XLEN-1:0]       TVecAlignedM;
   logic                    InstrValidNotFlushedM;
@@ -168,9 +168,7 @@ module csr import cvw::*;  #(parameter cvw_t P) (
   // Trap Returns
   // A trap sets the PC to TrapVector
   // A return sets the PC to MEPC or SEPC
-  assign RetM = mretM | sretM;
-  mux2 #(P.XLEN) epcmux(SEPC_REGW, MEPC_REGW, mretM, EPC);
-  mux3 #(P.XLEN) pcmux3(PC2NextF, EPC, TrapVectorM, {TrapM, RetM}, UnalignedPCNextF);
+  mux2 #(P.XLEN) epcmux(SEPC_REGW, MEPC_REGW, mretM, EPCM);
 
   ///////////////////////////////////////////
   // CSRWriteValM

src/privileged/privdec.sv

@@ -38,7 +38,7 @@ module privdec import cvw::*;  #(parameter cvw_t P) (
   input  logic         STATUS_TSR, STATUS_TVM, STATUS_TW,   // status bits
   output logic         IllegalInstrFaultM,                  // Illegal instruction
   output logic         EcallFaultM, BreakpointFaultM,       // Ecall or breakpoint; must retire, so don't flush it when the trap occurs
-  output logic         sretM, mretM,                        // return instructions
+  output logic         sretM, mretM, RetM,                  // return instructions
   output logic         wfiM, wfiW, sfencevmaM               // wfi / sfence.vma / sinval.vma instructions
 );
 
@@ -66,6 +66,7 @@ module privdec import cvw::*;  #(parameter cvw_t P) (
   assign sretM =      PrivilegedM & (InstrM[31:20] == 12'b000100000010) & rs1zeroM & P.S_SUPPORTED & 
                       (PrivilegeModeW == P.M_MODE | PrivilegeModeW == P.S_MODE & ~STATUS_TSR); 
   assign mretM =      PrivilegedM & (InstrM[31:20] == 12'b001100000010) & rs1zeroM & (PrivilegeModeW == P.M_MODE);
+  assign RetM =       sretM | mretM;
   assign ecallM =     PrivilegedM & (InstrM[31:20] == 12'b000000000000) & rs1zeroM;
   assign ebreakM =    PrivilegedM & (InstrM[31:20] == 12'b000000000001) & rs1zeroM;
   assign wfiM =       PrivilegedM & (InstrM[31:20] == 12'b000100000101) & rs1zeroM;

src/privileged/privileged.sv

@@ -37,7 +37,7 @@ module privileged import cvw::*;  #(parameter cvw_t P) (
   input  logic [31:0]       InstrM,                                         // Instruction
   input  logic [31:0]       InstrOrigM,                                     // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL
   input  logic [P.XLEN-1:0] IEUAdrM,                                        // address from IEU
-  input  logic [P.XLEN-1:0] PCM, PC2NextF,                                  // program counter, next PC going to trap/return PC logic
+  input  logic [P.XLEN-1:0] PCM,                                            // program counter
   // control signals                                                       
   input  logic              InstrValidM,                                    // Current instruction is valid (not flushed)
   input  logic              CommittedM, CommittedF,                         // current instruction is using bus; don't interrupt
@@ -85,8 +85,9 @@ module privileged import cvw::*;  #(parameter cvw_t P) (
   output logic [3:0]        ENVCFG_CBE,                                     // Cache block operation enables
   output logic              ENVCFG_PBMTE,                                   // Page-based memory type enable
   output logic              ENVCFG_ADUE,                                    // HPTW A/D Update enable
-  // PC logic output in privileged unit                                    
-  output logic [P.XLEN-1:0] UnalignedPCNextF,                               // Next PC from trap/return PC logic
+  // PC logic output from privileged unit to IFU                                  
+  output logic [P.XLEN-1:0] EPCM,                                           // Exception Program counter to IFU PC logic
+  output logic [P.XLEN-1:0] TrapVectorM,                                    // Trap vector, to IFU PC logic
   // control outputs                                                       
   output logic              RetM, TrapM,                                    // return instruction, or trap
   output logic              sfencevmaM,                                     // sfence.vma instruction
@@ -125,11 +126,11 @@ module privileged import cvw::*;  #(parameter cvw_t P) (
   privdec #(P) pmd(.clk, .reset, .StallW, .FlushW, .InstrM(InstrM[31:15]), 
     .PrivilegedM, .IllegalIEUFPUInstrM, .IllegalCSRAccessM, 
     .PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_TW, .IllegalInstrFaultM, 
-    .EcallFaultM, .BreakpointFaultM, .sretM, .mretM, .wfiM, .wfiW, .sfencevmaM);
+    .EcallFaultM, .BreakpointFaultM, .sretM, .mretM, .RetM, .wfiM, .wfiW, .sfencevmaM);
 
   // Control and Status Registers
   csr #(P) csr(.clk, .reset, .FlushM, .FlushW, .StallE, .StallM, .StallW,
-    .InstrM, .InstrOrigM, .PCM, .SrcAM, .IEUAdrM, .PC2NextF,
+    .InstrM, .InstrOrigM, .PCM, .SrcAM, .IEUAdrM, 
     .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .InterruptM,
     .MTimerInt, .MExtInt, .SExtInt, .MSwInt,
     .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .StoreStallD,
@@ -142,7 +143,8 @@ module privileged import cvw::*;  #(parameter cvw_t P) (
     .MEDELEG_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW,
     .SATP_REGW, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
     .SetFflagsM, .FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_ADUE,
-    .CSRReadValW,.UnalignedPCNextF, .IllegalCSRAccessM, .BigEndianM);
+    .EPCM, .TrapVectorM,
+    .CSRReadValW, .IllegalCSRAccessM, .BigEndianM);
 
   // pipeline early-arriving trap sources
   privpiperegs ppr(.clk, .reset, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
@@ -154,9 +156,8 @@ module privileged import cvw::*;  #(parameter cvw_t P) (
     .InstrMisalignedFaultM, .InstrAccessFaultM, .HPTWInstrAccessFaultM, .IllegalInstrFaultM,
     .BreakpointFaultM, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
     .LoadAccessFaultM, .StoreAmoAccessFaultM, .EcallFaultM, .InstrPageFaultM,
-    .LoadPageFaultM, .StoreAmoPageFaultM,
-    .mretM, .sretM, .PrivilegeModeW, 
+    .LoadPageFaultM, .StoreAmoPageFaultM, .PrivilegeModeW, 
     .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .MEDELEG_REGW, .STATUS_MIE, .STATUS_SIE,
     .InstrValidM, .CommittedM, .CommittedF,
-    .TrapM, .RetM, .wfiM, .wfiW, .InterruptM, .ExceptionM, .IntPendingM, .DelegateM, .CauseM);
+    .TrapM, .wfiM, .wfiW, .InterruptM, .ExceptionM, .IntPendingM, .DelegateM, .CauseM);
 endmodule