ip: Pmods: PmodCOLOR/RTCC minor bugfixes

re-added missing *_ooc.xdc file for PmodCOLOR
removed duplicate driver .mdd and .tcl files for PmodRTCC

ip/Pmods/PmodCOLOR_v1_0/component.xml

@@ -1925,7 +1925,7 @@
       <spirit:file>
         <spirit:name>src/PmodCOLOR.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_6f798c83</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_81e50893</spirit:userFileType>
         <spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
@@ -2236,11 +2236,11 @@
       </xilinx:taxonomies>
       <xilinx:displayName>PmodCOLOR_v1_0</xilinx:displayName>
       <xilinx:coreRevision>3</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2017-10-06T19:10:25Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2017-10-16T18:59:00Z</xilinx:coreCreationDateTime>
       <xilinx:tags>
         <xilinx:tag xilinx:name="natinst.com:user:PmodCOLOR:1.0_ARCHIVE_LOCATION">C:/Users/arbrown/Documents/GitHub/vivado-library/ip/Pmods/PmodCOLOR_v1_0</xilinx:tag>
         <xilinx:tag xilinx:name="digilentinc.com:user:PmodCOLOR:1.0_ARCHIVE_LOCATION">C:/Users/arbrown/Documents/GitHub/vivado-library/ip/Pmods/PmodCOLOR_v1_0</xilinx:tag>
-        <xilinx:tag xilinx:name="digilentinc.com:IP:PmodCOLOR:1.0_ARCHIVE_LOCATION">C:/Users/arbrown/Documents/GitHub/vivado-library/ip/Pmods/PmodCOLOR_v1_0</xilinx:tag>
+        <xilinx:tag xilinx:name="digilentinc.com:IP:PmodCOLOR:1.0_ARCHIVE_LOCATION">C:/Users/arthur/Documents/GitHub/vivado-library/ip/Pmods/PmodCOLOR_v1_0</xilinx:tag>
       </xilinx:tags>
       <xilinx:configElementInfos>
         <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_LITE_GPIO.ADDR_WIDTH" xilinx:valueSource="user"/>

ip/Pmods/PmodCOLOR_v1_0/src/PmodCOLOR_ooc.xdc

@@ -0,0 +1,11 @@
+################################################################################
+
+# This XDC is used only for OOC mode of synthesis, implementation
+# This constraints file contains default clock frequencies to be used during
+# out-of-context flows such as OOC Synthesis and Hierarchical Designs.
+# This constraints file is not used in normal top-down synthesis (default flow
+# of Vivado)
+################################################################################
+create_clock -name s_axi_aclk -period 10 [get_ports s_axi_aclk]
+
+################################################################################