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feat: port Chisel2 to Chisel3 rocket/
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@SingularityKChen @sequencer
SingularityKChen authored and sequencer committed Mar 1, 2023
1 parent 0e4af6d commit d6a982b
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Showing 5 changed files with 44 additions and 46 deletions.
2 changes: 1 addition & 1 deletion src/main/scala/rocket/BTB.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -202,7 +202,7 @@ class BTB(implicit p: Parameters) extends BtbModule {
val tgts = Reg(Vec(entries, UInt((matchBits - log2Up(coreInstBytes)).W)))
val tgtPages = Reg(Vec(entries, UInt(log2Up(nPages).W)))
val pages = Reg(Vec(nPages, UInt((vaddrBits - matchBits).W)))
val pageValid = RegInit(init = 0.U(nPages.W))
val pageValid = RegInit(0.U(nPages.W))
val pagesMasked = (pageValid.asBools zip pages).map { case (v, p) => Mux(v, p, 0.U) }

val isValid = RegInit(0.U(entries.W))
Expand Down
67 changes: 33 additions & 34 deletions src/main/scala/rocket/NBDcache.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,6 @@ package freechips.rocketchip.rocket

import chisel3._
import chisel3.util._
import chisel3.util.ImplicitConversions._
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tilelink._
Expand Down Expand Up @@ -198,7 +197,7 @@ class MSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCach
rpq.io.deq.ready := (io.replay.ready && state === s_drain_rpq) || state === s_invalid

val acked = Reg(Bool())
when (io.mem_grant.valid) { acked := true }
when (io.mem_grant.valid) { acked := true.B }

when (state === s_drain_rpq && !rpq.io.deq.valid) {
state := s_invalid
Expand Down Expand Up @@ -237,7 +236,7 @@ class MSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCach
}
when (io.req_pri_val && io.req_pri_rdy) {
req := io.req_bits
acked := false
acked := false.B
val old_coh = io.req_bits.old_meta.coh
val needs_wb = old_coh.onCacheControl(M_FLUSH)._1
val (is_hit, _, coh_on_hit) = old_coh.onAccess(io.req_bits.cmd)
Expand Down Expand Up @@ -271,9 +270,9 @@ class MSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCach
io.req_sec_rdy := sec_rdy && rpq.io.enq.ready

val meta_hazard = RegInit(0.U(2.W))
when (meta_hazard =/= 0.U) { meta_hazard := meta_hazard + 1 }
when (io.meta_write.fire) { meta_hazard := 1 }
io.probe_rdy := !idx_match || (!state.isOneOf(states_before_refill) && meta_hazard === 0)
when (meta_hazard =/= 0.U) { meta_hazard := meta_hazard + 1.U }
when (io.meta_write.fire) { meta_hazard := 1.U }
io.probe_rdy := !idx_match || (!state.isOneOf(states_before_refill) && meta_hazard === 0.U)

io.meta_write.valid := state.isOneOf(s_meta_write_req, s_meta_clear)
io.meta_write.bits.idx := req_idx
Expand All @@ -294,7 +293,7 @@ class MSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCach
io.mem_acquire.bits := edge.AcquireBlock(
fromSource = id.U,
toAddress = Cat(io.tag, req_idx) << blockOffBits,
lgSize = lgCacheBlockBytes,
lgSize = lgCacheBlockBytes.U,
growPermissions = grow_param)._2

io.meta_read.valid := state === s_drain_rpq
Expand Down Expand Up @@ -335,7 +334,7 @@ class MSHRFile(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModu
})

// determine if the request is cacheable or not
val cacheable = edge.manager.supportsAcquireBFast(io.req.bits.addr, lgCacheBlockBytes)
val cacheable = edge.manager.supportsAcquireBFast(io.req.bits.addr, lgCacheBlockBytes.U)

val sdq_val = RegInit(0.U(cfg.nSDQ.W))
val sdq_alloc_id = PriorityEncoder(~sdq_val(cfg.nSDQ-1,0))
Expand All @@ -361,8 +360,8 @@ class MSHRFile(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModu
var pri_rdy = false.B
var sec_rdy = false.B

io.fence_rdy := true
io.probe_rdy := true
io.fence_rdy := true.B
io.probe_rdy := true.B

val mshrs = (0 until cfg.nMSHRs) map { i =>
val mshr = Module(new MSHR(i))
Expand Down Expand Up @@ -394,8 +393,8 @@ class MSHRFile(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCacheModu
sec_rdy = sec_rdy || mshr.io.req_sec_rdy
idx_match = idx_match || mshr.io.idx_match

when (!mshr.io.req_pri_rdy) { io.fence_rdy := false }
when (!mshr.io.probe_rdy) { io.probe_rdy := false }
when (!mshr.io.req_pri_rdy) { io.fence_rdy := false.B }
when (!mshr.io.probe_rdy) { io.probe_rdy := false.B }

mshr
}
Expand Down Expand Up @@ -474,20 +473,20 @@ class WritebackUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCach
val data_req_cnt = RegInit(0.U(log2Up(refillCycles+1).W)) //TODO Zero width
val (_, last_beat, all_beats_done, beat_count) = edge.count(io.release)

io.release.valid := false
io.release.valid := false.B
when (active) {
r1_data_req_fired := false
r1_data_req_fired := false.B
r2_data_req_fired := r1_data_req_fired
when (io.data_req.fire && io.meta_read.fire) {
r1_data_req_fired := true
data_req_cnt := data_req_cnt + 1
r1_data_req_fired := true.B
data_req_cnt := data_req_cnt + 1.U
}
when (r2_data_req_fired) {
io.release.valid := true
io.release.valid := true.B
when(!io.release.ready) {
r1_data_req_fired := false
r2_data_req_fired := false
data_req_cnt := data_req_cnt - Mux[UInt]((refillCycles > 1).B && r1_data_req_fired, 2, 1)
r1_data_req_fired := false.B
r2_data_req_fired := false.B
data_req_cnt := data_req_cnt - Mux[UInt]((refillCycles > 1).B && r1_data_req_fired, 2.U, 1.U)
}
when(!r1_data_req_fired) {
// We're done if this is the final data request and the Release can be sent
Expand All @@ -496,8 +495,8 @@ class WritebackUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCach
}
}
when (io.req.fire) {
active := true
data_req_cnt := 0
active := true.B
data_req_cnt := 0.U
req := io.req.bits
}

Expand All @@ -521,14 +520,14 @@ class WritebackUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCach
val probeResponse = edge.ProbeAck(
fromSource = req.source,
toAddress = r_address,
lgSize = lgCacheBlockBytes,
lgSize = lgCacheBlockBytes.U,
reportPermissions = req.param,
data = io.data_resp)

val voluntaryRelease = edge.Release(
fromSource = req.source,
toAddress = r_address,
lgSize = lgCacheBlockBytes,
lgSize = lgCacheBlockBytes.U,
shrinkPermissions = req.param,
data = io.data_resp)._2

Expand Down Expand Up @@ -755,7 +754,7 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
dtlb.io.sfence.bits.addr := s1_req.addr
dtlb.io.sfence.bits.asid := io.cpu.s1_data.data
dtlb.io.sfence.bits.hv := s1_req.cmd === M_HFENCEV
dtlb.io.sfence.bits.hg := s1_req.cmd == M_HFENCEG
dtlb.io.sfence.bits.hg := s1_req.cmd === M_HFENCEG

when (io.cpu.req.valid) {
s1_req := io.cpu.req.bits
Expand Down Expand Up @@ -843,23 +842,23 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule

// load-reserved/store-conditional
val lrsc_count = RegInit(0.U)
val lrsc_valid = lrsc_count > lrscBackoff
val lrsc_valid = lrsc_count > lrscBackoff.U
val lrsc_addr = Reg(UInt())
val (s2_lr, s2_sc) = (s2_req.cmd === M_XLR, s2_req.cmd === M_XSC)
val s2_lrsc_addr_match = lrsc_valid && lrsc_addr === (s2_req.addr >> blockOffBits)
val s2_sc_fail = s2_sc && !s2_lrsc_addr_match
when (lrsc_count > 0) { lrsc_count := lrsc_count - 1 }
when (lrsc_count > 0.U) { lrsc_count := lrsc_count - 1.U }
when (s2_valid_masked && s2_hit || s2_replay) {
when (s2_lr) {
lrsc_count := lrscCycles - 1
lrsc_count := lrscCycles.U - 1.U
lrsc_addr := s2_req.addr >> blockOffBits
}
when (lrsc_count > 0) {
lrsc_count := 0
when (lrsc_count > 0.U) {
lrsc_count := 0.U
}
}
when (s2_valid_masked && !(s2_tag_match && s2_has_permission) && s2_lrsc_addr_match) {
lrsc_count := 0
lrsc_count := 0.U
}

val s2_data = Wire(Vec(nWays, Bits(encRowBits.W)))
Expand Down Expand Up @@ -968,10 +967,10 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
val s2_store_bypass_data = Reg(Bits(coreDataBits.W))
val s2_store_bypass = Reg(Bool())
when (s1_clk_en) {
s2_store_bypass := false
s2_store_bypass := false.B
when (bypasses.map(_._1).reduce(_||_)) {
s2_store_bypass_data := PriorityMux(bypasses)
s2_store_bypass := true
s2_store_bypass := true.B
}
}

Expand Down Expand Up @@ -1049,5 +1048,5 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule
io.cpu.perf.tlbMiss := io.ptw.req.fire

// no clock-gating support
io.cpu.clock_enabled := true
io.cpu.clock_enabled := true.B
}
8 changes: 4 additions & 4 deletions src/main/scala/rocket/PTW.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -476,7 +476,7 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
}
}

val s0_valid = !l2_refill && arb.io.out.fire()
val s0_valid = !l2_refill && arb.io.out.fire
val s0_suitable = arb.io.out.bits.bits.vstage1 === arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.need_gpa
val s1_valid = RegNext(s0_valid && s0_suitable && arb.io.out.bits.valid)
val s2_valid = RegNext(s1_valid)
Expand Down Expand Up @@ -584,7 +584,7 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(

switch (state) {
is (s_ready) {
when (arb.io.out.fire()) {
when (arb.io.out.fire) {
val satp_initial_count = pgLevels.U - minPgLevels.U - satp.additionalPgLevels
val vsatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.vsatp.additionalPgLevels
val hgatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.hgatp.additionalPgLevels
Expand Down Expand Up @@ -677,7 +677,7 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
// fragment_superpage
Mux(state === s_fragment_superpage && !homogeneous && count =/= (pgLevels - 1).U, makePTE(makeFragmentedSuperpagePPN(r_pte.ppn)(count), r_pte),
// when tlb request come->request mem, use root address in satp(or vsatp,hgatp)
Mux(arb.io.out.fire(), Mux(arb.io.out.bits.bits.stage2, makeHypervisorRootPTE(io.dpath.hgatp, io.dpath.vsatp.ppn, r_pte), makePTE(satp.ppn, r_pte)),
Mux(arb.io.out.fire, Mux(arb.io.out.bits.bits.stage2, makeHypervisorRootPTE(io.dpath.hgatp, io.dpath.vsatp.ppn, r_pte), makePTE(satp.ppn, r_pte)),
r_pte)))))))

when (l2_hit && !l2_error) {
Expand Down Expand Up @@ -773,7 +773,7 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
private def makeHypervisorRootPTE(hgatp: PTBR, vpn: UInt, default: PTE) = {
val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels
val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> (pgLevels-i)*pgLevelBits))
val lsbs = WireDefault(t = UInt(maxHypervisorExtraAddrBits.W), init = idxs(count))
val lsbs = WireDefault(UInt(maxHypervisorExtraAddrBits.W), idxs(count))
val pte = WireDefault(default)
pte.ppn := Cat(hgatp.ppn >> maxHypervisorExtraAddrBits, lsbs)
pte
Expand Down
9 changes: 4 additions & 5 deletions src/main/scala/rocket/ScratchpadSlavePort.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,6 @@ package freechips.rocketchip.rocket

import chisel3._
import chisel3.util._
import chisel3.util.ImplicitConversions._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
Expand Down Expand Up @@ -85,11 +84,11 @@ class ScratchpadSlavePort(address: Seq[AddressSet], coreDataBytes: Int, usingAto
}

req.size := a.size
req.signed := false
req.signed := false.B
req.addr := a.address
req.tag := 0.U
req.phys := true
req.no_xcpt := true
req.phys := true.B
req.no_xcpt := true.B
req.data := 0.U
req.no_alloc := false.B
req.mask := 0.U
Expand All @@ -112,7 +111,7 @@ class ScratchpadSlavePort(address: Seq[AddressSet], coreDataBytes: Int, usingAto
io.dmem.s1_data.data := acq.data
io.dmem.s1_data.mask := acq.mask
io.dmem.s1_kill := state =/= s_wait1
io.dmem.s2_kill := false
io.dmem.s2_kill := false.B

tl_in.d.valid := io.dmem.resp.valid || state === s_grant
tl_in.d.bits := Mux(acq.opcode.isOneOf(TLMessages.PutFullData, TLMessages.PutPartialData),
Expand Down
4 changes: 2 additions & 2 deletions src/main/scala/rocket/TLB.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -306,7 +306,7 @@ case class TLBConfig(
* @param edge collect SoC metadata.
*/
class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) {
val io = new Bundle {
val io = IO(new Bundle {
/** request from Core */
val req = Flipped(Decoupled(new TLBReq(lgMaxSize)))
/** response to Core */
Expand All @@ -317,7 +317,7 @@ class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: T
val ptw = new TLBPTWIO
/** suppress a TLB refill, one cycle after a miss */
val kill = Input(Bool())
}
})

val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits)
val vpn = io.req.bits.vaddr(vaddrBits-1, pgIdxBits)
Expand Down

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