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Add some processing to the WB32 MCU series. #324

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merged 5 commits into from
Jul 27, 2022
Merged

Add some processing to the WB32 MCU series. #324

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af3b93a
Added drive current control for special pins.
Jun 20, 2022
c0510a6
Update hal_usb_lld.h
Jun 29, 2022
022d0ec
Update hal_usb_lld.h
Jun 29, 2022
7aa5e64
Added the implementation of embedded flash for WB32 MCU.
Jul 7, 2022
ccd4fea
Update hal_pal_lld.c
Jul 13, 2022
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23 changes: 21 additions & 2 deletions os/common/ext/CMSIS/WB32/WB32F3G71xx/wb32f3g71xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -945,8 +945,24 @@ typedef struct
#warning Not supported compiler type
#endif



static const uint32_t flash_size_code_map[16] = {
0x80000, /* 512kB */
0x8000, /* 32kB */
0x60000, /* 384kB */
0x40000, /* 256kB */
0x20000, /* 128kB */
0x8000, /* 32kB */
0x18000, /* 96kB */
0x10000, /* 64kB */
0x8000, /* 32kB */
0x8000, /* 32kB */
0x8000, /* 32kB */
0x8000, /* 32kB */
0x8000, /* 32kB */
0x8000, /* 32kB */
0x8000, /* 32kB */
0x30000, /* 192kB */
};

/* ================================================================================ */
/* ================ Peripheral memory map ================ */
Expand All @@ -958,6 +974,9 @@ typedef struct
#define SRAM_BB_BASE ((uint32_t)0x22000000UL) /*!< SRAM base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000UL) /*!< Peripheral base address in the bit-band region */

#define SYS_MEMSE ((uint32_t)0x40016404UL)
#define FLASH_SIZE flash_size_code_map[(*((volatile uint32_t *)(SYS_MEMSE))) & 0xFU]

#define APB1PERIPH_BASE PERIPH_BASE
#define APB2PERIPH_BASE (PERIPH_BASE + 0x08000)
#define AHBPERIPH_BASE (PERIPH_BASE + 0x10000)
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21 changes: 21 additions & 0 deletions os/common/ext/CMSIS/WB32/WB32FQ95xx/wb32fq95xx.h
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Expand Up @@ -890,6 +890,24 @@ typedef struct
#warning Not supported compiler type
#endif

static const uint32_t flash_size_code_map[16] = {
0x80000, /* 512kB */
0x8000, /* 32kB */
0x60000, /* 384kB */
0x40000, /* 256kB */
0x20000, /* 128kB */
0x8000, /* 32kB */
0x18000, /* 96kB */
0x10000, /* 64kB */
0x8000, /* 32kB */
0x8000, /* 32kB */
0x8000, /* 32kB */
0x8000, /* 32kB */
0x8000, /* 32kB */
0x8000, /* 32kB */
0x8000, /* 32kB */
0x30000, /* 192kB */
};

/* ================================================================================ */
/* ================ Peripheral memory map ================ */
Expand All @@ -901,6 +919,9 @@ typedef struct
#define SRAM_BB_BASE ((uint32_t)0x22000000UL) /*!< SRAM base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000UL) /*!< Peripheral base address in the bit-band region */

#define SYS_MEMSE ((uint32_t)0x40016404UL)
#define FLASH_SIZE flash_size_code_map[(*((volatile uint32_t *)(SYS_MEMSE))) & 0xFU]

#define APB1PERIPH_BASE PERIPH_BASE
#define APB2PERIPH_BASE (PERIPH_BASE + 0x08000)
#define AHBPERIPH_BASE (PERIPH_BASE + 0x10000)
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6 changes: 6 additions & 0 deletions os/hal/ports/WB32/LLD/GPIOv1/hal_pal_lld.c
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Expand Up @@ -96,6 +96,12 @@ void _pal_lld_setgroupmode(ioportid_t port, ioportmask_t mask, iomode_t mode) {
uint32_t altr = (mode & PAL_WB32_ALTERNATE_MASK) >> 7;
uint32_t current = (mode & PAL_WB32_CURRENT_MASK) >> 11;

#ifdef SPI_SCK_PIN
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if ((PAL_PORT(SPI_SCK_PIN) == port) && (PAL_PORT_BIT(PAL_PAD(SPI_SCK_PIN)) & mask)) {
current |= (PAL_WB32_CURRENT_LEVEL3 >> 11);
}
#endif

port->CFGMSK = ~mask;
port->MODER = (moder & 0x3) * 0x55555555U;
port->OTYPER = (otyper & 0x1) * 0xFFFFFFFFU;
Expand Down
1 change: 1 addition & 0 deletions os/hal/ports/WB32/LLD/USBv1/hal_usb_lld.h
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Expand Up @@ -472,6 +472,7 @@ struct USBDriver {
WB32_USB->POWER |= USB_POWER_RESUME; \
osalThreadSleepMilliseconds(WB32_USB_HOST_WAKEUP_DURATION); \
WB32_USB->POWER &= ~USB_POWER_RESUME; \
_usb_wakeup(usbp); \
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} while (false)

/*===========================================================================*/
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