M³ Hardware

This repository contains the hardware RTL code of the M³ operating system [1]. Currently, the following components are included:

• Network-on-chip: set up as a 2x2 star-mesh topology with 4 routers and 8 processing modules
• Trusted Communication Unit (TCU) [2]
• Processing module: RISC-V Rocket Chip Core (already generated RTL code) [3]
• Gbit Ethernet interface for platform access and debugging (uses the UDP/IP stack from [4])
• 4x Gbit Ethernet interface to Quad Gigabit Ethernet FMC card [5]
• 2x DDR4 interface with 2 GB DRAM each
• UART connected to RISC-V (PM0)

Repository structure

The source code is distributed into several "units", while each unit can contain source code, constraints for synthesis, scripts, and testbenches. The directory "global_src" contains header files used by multiple units.

Supported platforms

In general, this RTL code targets both FPGA and ASIC implementations. Specific blocks (e.g. memory, clock generators) must be replaced accordingly by using approprate defines.

The provided tool flow supports Linux (Ubuntu) and targets the Xilinx VCU118 board [6]. Xilinx-specific RTL blocks are marked with the flag XILINX_FPGA. For FPGA-based simulation and synthesis, Xilinx Vivado is used. The scripts are successfully tested with Vivado versions 2019.1 and 2020.2. Other versions up to 2022.2 may also work but are not tested.

The tool flow is set up on top-level fpga_top. The following input parameters can be used to configure the top-level:

• PM_DOMAIN_TYPE: Select a PM type from the list given in global_src/pm_types.vh
• CLKFREQ_PM_MHZ: Select a clock frequency in MHz for each PM.
• PM_UART_ATTACHED: Select which PM should be attached to the USB-UART. Note that there is only one USB-UART interface available.

All processing modules and the NoC are clocked at a clock frequency of 100 MHz. All clocks are generated by an internal PLL (Mixed-mode-Clock Manager, MMCME). If timing is not met during synthesis, reducing the clock frequency is an option, especially for RISC-V BOOM cores.

Getting started

The RTL code can be simulated and synthesized. For synthesis, a valid Xilinx license must be available to generate the bitfile.

1. Set up repository and environment

Clone the repository:

$ git clone https://github.com/Barkhausen-Institut/M3-hardware.git

Pull in submodules:

$ git submodule update --init

Run the following script at the root directoy to initialize the repo:

$ source init_repo.sh

This has to be done only once. Everytime you open a new terminal only run the following script at the root directory to configure the environment:

$ source conf_env.sh

Furthermore, make sure that Xilinx Vivado is added to your environment.

2. Simulate a testcase on top-level

Change to a given testcase on top-level, e.g.:

$ cd units/fpga_top/simulation/vivado/tc_memory_test

Start the simulation:

$ make simulate

The Vivado GUI will open up where you can run the simulation and view selected waveforms.

3. Synthesize the design

Change to the synthesis directory:

$ cd units/fpga_top/rtl2gds/vivado

Start synthesis:

$ make all

This will generate the netlist, do place & route, and generate the bitfile.

References

[1] Microkernel-based system for heterogeneous manycores: https://github.com/Barkhausen-Institut/M3

[2] Specification of Trusted Communication Unit: https://github.com/Barkhausen-Institut/TCU-if

[3] Rocket Chip Generator: https://github.com/chipsalliance/rocket-chip

[4] Alex Forencich - Verilog Ethernet: https://github.com/alexforencich/verilog-ethernet

[5] Opsero - Quad Gigabit Ethernet FPGA Mezzanine Card: https://opsero.com/product/ethernet-fmc

[6] Xilinx VCU118 board: https://www.xilinx.com/products/boards-and-kits/vcu118.html