Update driver to new xrt version

tests/fpga_drivers/__init__.py

@@ -60,8 +60,6 @@ def __init__(self, fpga_slot_id=0, fpga_image=None, drm_ctrl_base_addr=0,
         self._fpga_read_register = None
         self._fpga_write_register = None
         self._fpga_register_lock = self._get_lock()
-        self._fpga_read_register_lock = self._fpga_register_lock
-        self._fpga_write_register_lock = self._fpga_register_lock
 
         if not no_clear_fpga:
            self.clear_fpga()

tests/fpga_drivers/_aws_f1.py

@@ -149,11 +149,14 @@ def read_register(register_offset, returned_data, driver=self):
                 driver (accelize_drm.fpga_drivers._aws_f1.FpgaDriver):
                     Keep a reference to driver.
             """
-            with driver._fpga_read_register_lock():
-                return driver._fpga_read_register(
-                    driver._fpga_handle,
-                    driver._drm_ctrl_base_addr + register_offset,
-                    returned_data)
+            try:
+                with driver._fpga_register_lock():
+                    return driver._fpga_read_register(
+                        driver._fpga_handle,
+                        driver._drm_ctrl_base_addr + register_offset,
+                        returned_data)
+            except AttributeError:
+                return -1
 
         return read_register
 
@@ -183,10 +186,13 @@ def write_register(register_offset, data_to_write, driver=self):
                 driver (accelize_drm.fpga_drivers._aws_f1.FpgaDriver):
                     Keep a reference to driver.
             """
-            with driver._fpga_write_register_lock():
-                return driver._fpga_write_register(
-                    driver._fpga_handle,
-                    driver._drm_ctrl_base_addr + register_offset,
-                    data_to_write)
+            try:
+                with driver._fpga_register_lock():
+                    return driver._fpga_write_register(
+                        driver._fpga_handle,
+                        driver._drm_ctrl_base_addr + register_offset,
+                        data_to_write)
+            except AttributeError:
+                return -1
 
         return write_register

tests/fpga_drivers/_aws_som.py

@@ -27,7 +27,7 @@
 
 def int_to_bytes(x: int) -> bytes:
     return x.to_bytes(4, 'little', signed=False)
-    
+
 def bytes_to_int(xbytes: bytes) -> int:
     return int.from_bytes(xbytes, 'little', signed=False)
 
@@ -44,7 +44,7 @@ class FpgaDriver(_FpgaDriverBase):
     """
     _name = _match(r'_(.+)\.py', _basename(__file__)).group(1)
     _reglock = _Lock()
-    
+
     @staticmethod
     def _get_xrt_lib():
         """
@@ -55,7 +55,7 @@ def _get_xrt_lib():
             if _isfile(_join(prefix, 'bin','xbutil')):
                 return prefix
         raise RuntimeError('Unable to find Xilinx XRT')
-    
+
     @staticmethod
     def _get_driver():
         """
@@ -74,7 +74,7 @@ def _get_driver():
         else:
             raise RuntimeError('Unable to find Xilinx XRT Library')
         return fpga_library
-    
+
     @staticmethod
     def _get_xbutil():
         xrt_path = FpgaDriver._get_xrt_lib()
@@ -94,7 +94,7 @@ def _get_lock(self):
         Get a lock on the FPGA driver
         """
         return _Lock
-    
+
     def _clear_fpga(self):
         """
         Clear FPGA
@@ -138,7 +138,7 @@ def _program_fpga(self, fpga_image):
         # Init global specific variables
         self.shm_pages = list()
         self.ctrl_sw_exec = None
-        
+
         # Start Controller SW
         fpga_image = ''
         if not _isfile(fpga_image):
@@ -210,10 +210,10 @@ def _uninit_fpga(self):
             self.ctrl_sw_exec.send_signal(signal.SIGINT)
             self.ctrl_sw_exec.wait()
         print('Terminate DRM')
-        
+
     def int_to_bytes(x: int) -> bytes:
         return x.to_bytes((x.bit_length() + 7) // 8, 'little', signed=False)
-		
+
     def int_from_bytes(xbytes: bytes) -> int:
         return int.from_bytes(xbytes, 'big')
 
@@ -246,7 +246,7 @@ def read_register(register_offset, returned_data, driver=self):
                 driver (accelize_drm.fpga_drivers._aws_xrt.FpgaDriver):
                     Keep a reference to driver.
             """
-            with driver._fpga_read_register_lock():
+            with driver._fpga_register_lock():
                 if register_offset >= 0x10000:
                     '''
                     size_or_error = driver._fpga_read_register(
@@ -266,7 +266,7 @@ def read_register(register_offset, returned_data, driver=self):
                         reg_value = page_index
                     else:
                         shm = driver.shm_pages[page_index]
-                        reg_value = bytes_to_int(shm.read(4, register_offset))                        
+                        reg_value = bytes_to_int(shm.read(4, register_offset))
 #                    print('Read @%08X: 0x%08X' % (register_offset, reg_value))
                     returned_data.contents.value = reg_value
                     ret = 0
@@ -291,7 +291,7 @@ def _get_write_register_callback(self):
             _c_size_t  # size
         )
         self._fpga_write_register = xcl_write
-        
+
         def write_register(register_offset, data_to_write, driver=self):
             """
             Write register.
@@ -302,7 +302,7 @@ def write_register(register_offset, data_to_write, driver=self):
                 driver (accelize_drm.fpga_drivers._aws_xrt.FpgaDriver):
                     Keep a reference to driver.
             """
-            with driver._fpga_read_register_lock():
+            with driver._fpga_register_lock():
                 if register_offset >= 0x10000:
                     '''
                     size_or_error = driver._fpga_write_register(

tests/fpga_drivers/_aws_xrt.py

@@ -4,6 +4,7 @@
 
 Requires XRT: https://github.com/Xilinx/XRT
 """
+import pyopencl as cl
 from ctypes import (
     cdll as _cdll, POINTER as _POINTER, c_char_p as _c_char_p,
     c_uint as _c_uint, c_uint64 as _c_uint64, c_int as _c_int,
@@ -117,11 +118,12 @@ def _clear_fpga(self):
         """
         Clear FPGA
         """
-        clear_fpga = _run(
-            ['fpga-clear-local-image', '-S', str(self._fpga_slot_id)],
-            stderr=_STDOUT, stdout=_PIPE, universal_newlines=True, check=False)
-        if clear_fpga.returncode:
-            raise RuntimeError(clear_fpga.stdout)
+        clear_image = _join(SCRIPT_DIR, 'clear.awsxclbin')
+        dev = cl.get_platforms()[0].get_devices()
+        binary = open(clear_image, 'rb').read()
+        ctx = cl.Context(dev_type=cl.device_type.ALL)
+        prg = cl.Program(ctx, [dev[self._fpga_slot_id]], [binary])
+        prg.build()
         print('FPGA cleared')
 
     def _program_fpga(self, fpga_image):
@@ -131,26 +133,13 @@ def _program_fpga(self, fpga_image):
         Args:
             fpga_image (str): FPGA image.
         """
-        # Vitis does not reprogram a FPGA that has already the bitstream.
-        # So to force it we write another bitstream first.
-        clear_image = _join(SCRIPT_DIR, 'clear.awsxclbin')
-        load_image = _run(
-            [self._xbutil, 'program',
-             '-d', str(self._fpga_slot_id), '-p', clear_image],
-            stderr=_STDOUT, stdout=_PIPE, universal_newlines=True, check=False)
-        if load_image.returncode:
-            raise RuntimeError(load_image.stdout)
-        print('Cleared AWS XRT slot #%d' % self._fpga_slot_id)
-
-        # Now load the real image
-        fpga_image = _realpath(_fsdecode(fpga_image))
-        load_image = _run(
-            [self._xbutil, 'program',
-             '-d', str(self._fpga_slot_id), '-p', fpga_image],
-            stderr=_STDOUT, stdout=_PIPE, universal_newlines=True, check=False)
-        if load_image.returncode:
-            raise RuntimeError(load_image.stdout)
-        print('Programmed AWS XRT slot #%d with FPGA image %s' % (self._fpga_slot_id, fpga_image))
+        self._clear_fpga()
+        dev = cl.get_platforms()[0].get_devices()
+        binary = open(fpga_image, 'rb').read()
+        ctx = cl.Context(dev_type=cl.device_type.ALL)
+        prg = cl.Program(ctx, [dev[self._fpga_slot_id]], [binary])
+        prg.build()
+        print(f'FPGA programed with {fpga_image}')
 
     def _reset_fpga(self):
         """
@@ -162,6 +151,7 @@ def _reset_fpga(self):
             stderr=_STDOUT, stdout=_PIPE, universal_newlines=True, check=False)
         if reset_image.returncode:
             raise RuntimeError(reset_image.stdout)
+        print(f'FPGA reset')
 
     def _init_fpga(self):
         """
@@ -192,6 +182,9 @@ def _init_fpga(self):
             raise RuntimeError("xclOpen failed to open device")
         self._fpga_handle = device_handle
 
+    def _uninit_fpga(self):
+        pass
+
     def _get_read_register_callback(self):
         """
         Read register callback.
@@ -220,7 +213,7 @@ def read_register(register_offset, returned_data, driver=self):
                 driver (accelize_drm.fpga_drivers._aws_xrt.FpgaDriver):
                     Keep a reference to driver.
             """
-            with driver._fpga_read_register_lock():
+            with driver._fpga_register_lock():
                 size_or_error = driver._fpga_read_register(
                     driver._fpga_handle,
                     2,  # XCL_ADDR_KERNEL_CTRL
@@ -262,7 +255,7 @@ def write_register(register_offset, data_to_write, driver=self):
                 driver (accelize_drm.fpga_drivers._aws_xrt.FpgaDriver):
                     Keep a reference to driver.
             """
-            with driver._fpga_write_register_lock():
+            with driver._fpga_register_lock():
                 size_or_error = driver._fpga_write_register(
                     driver._fpga_handle,
                     2,  # XCL_ADDR_KERNEL_CTRL

tests/fpga_drivers/_som_xrt.py

@@ -156,7 +156,7 @@ def _reset_fpga(self):
             print('No loaded bitstream to reset')
             return
         self._program_fpga(image_name + ".som")
-        
+
     def _init_fpga(self):
         """
         Initialize FPGA handle with XRT and OpenCL libraries.
@@ -225,7 +225,7 @@ def read_register(register_offset, returned_data, driver=self):
                 driver (accelize_drm.fpga_drivers._aws_xrt.FpgaDriver):
                     Keep a reference to driver.
             """
-            with driver._fpga_read_register_lock():
+            with driver._fpga_register_lock():
                 size_or_error = driver._fpga_read_register(
                     driver._fpga_handle,
                     2,  # XCL_ADDR_KERNEL_CTRL
@@ -267,7 +267,7 @@ def write_register(register_offset, data_to_write, driver=self):
                 driver (accelize_drm.fpga_drivers._aws_xrt.FpgaDriver):
                     Keep a reference to driver.
             """
-            with driver._fpga_write_register_lock():
+            with driver._fpga_register_lock():
                 size_or_error = driver._fpga_write_register(
                     driver._fpga_handle,
                     2,  # XCL_ADDR_KERNEL_CTRL

tests/fpga_drivers/_xrt.py

@@ -127,6 +127,7 @@ def _program_fpga(self, fpga_image):
         Args:
             fpga_image (str): FPGA image.
         """
+        self._clear_fpga()
         load_image = _run(
             [self._xbutil, 'program', '-d', 'all', '-u', fpga_image],
             stderr=_STDOUT, stdout=_PIPE, universal_newlines=True, check=False)
@@ -207,7 +208,7 @@ def read_register(register_offset, returned_data, driver=self):
                 driver (accelize_drm.fpga_drivers._aws_xrt.FpgaDriver):
                     Keep a reference to driver.
             """
-            with driver._fpga_read_register_lock():
+            with driver._fpga_register_lock():
                 size_or_error = driver._fpga_read_register(
                     driver._fpga_handle,
                     2,  # XCL_ADDR_KERNEL_CTRL
@@ -249,7 +250,7 @@ def write_register(register_offset, data_to_write, driver=self):
                 driver (accelize_drm.fpga_drivers._aws_xrt.FpgaDriver):
                     Keep a reference to driver.
             """
-            with driver._fpga_write_register_lock():
+            with driver._fpga_register_lock():
                 size_or_error = driver._fpga_write_register(
                     driver._fpga_handle,
                     2,  # XCL_ADDR_KERNEL_CTRL

tox.ini

@@ -66,6 +66,7 @@ description =
 
 deps =
     cython
+    pyopencl
     flake8
     flask
     pytest