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Achievement: QuickdrawAchievement: Pull Shark

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Achievement: QuickdrawAchievement: Pull Shark

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AUDIY/README.md

Hi there 👋 I'm AUDIY!

Stats

About me

An FPGA&CPLD engineer in a certain circuit design department. What a pretty circuit!
Twitter: @AUDIY14
GitHub: AUDIY

I'm currently working on

  1. FIR_x2
    FPGA based PCM oversampling FIR filter (oversample ratio: 2).
  2. AUDIY_Verilog_IP
    Verilog IP that AUDIY originally designed.
  3. AUDIY_OSPCB
    Open Source PCB Files Engineered by AUDIY.
  4. DSFIO
    DSD Stream File (*.dsf) reader library written in C.

Blog

電子回路わからん日記 (https://audio-diy.hatenablog.com/)

Presentation Achievements

  1. 第15回ACRiウェビナー：X界隈のFPGAエンジニア集合！
    Theme: Efinix Trionを使って嵌ったこと

My interests are

  1. FPGA
  2. Verilog HDL
  3. Python
  4. C/C++
  5. Audio Signal Processing
  6. Electronic Circuit Design

I'm learning

  1. C++
  2. SystemVerilog (including SVA)
  3. VHDL
  4. PSL assertion

Pinned Loading

  1. FIR_x2 FIR_x2 Public

    FPGA based PCM oversampling FIR filter.

    Verilog 4

  2. DSFIO DSFIO Public

    DSD Stream File (*.dsf) reader library written in C.

    C 2

  3. AUDIY_Verilog_IP AUDIY_Verilog_IP Public

    Verilog IP that AUDIY originally designed.

    Verilog 2

  4. AUDIY_OSPCB AUDIY_OSPCB Public

    Open Source PCB Files Engineered by AUDIY

    HTML 1