Add patch to fix volatile access bug (#595)

We have a customer affected by this bug, which was fixed after LLVM 19,
and we'd like to do a release of LLVM-ET 19 with the fix.

LLVM PR: llvm/llvm-project#111679

Original commit message:

[DAGISel] Keep flags when converting FP load/store to integer (#111679)

This DAG combine replaces a floating-point load/store pair which has no
other uses with an integer one, but did not copy the memory operand
flags to the new instructions, resulting in it dropping the volatile
flag. This optimisation is still valid if one or both of the
instructions is volatile, so we can copy over the whole
MachineMemOperand to generate volatile integer loads and stores where
needed.

patches/llvm-project/0001-libc-tests-with-picolibc-xfail-two-remaining-tests.patch

@@ -1,4 +1,4 @@
-From cb6cfe0e5fc29d3867f523900f0d46a4ef5dff1b Mon Sep 17 00:00:00 2001
+From 9fb80381b839fdbe15ddfa732bed5c25d6e4a5a2 Mon Sep 17 00:00:00 2001
 From: =?UTF-8?q?Dominik=20W=C3=B3jt?= <[email protected]>
 Date: Mon, 16 Oct 2023 11:35:48 +0200
 Subject: [libc++] tests with picolibc: xfail two remaining tests
@@ -25,10 +25,10 @@ index c9c2ba200214..4898a9a06e09 100644
  // architectures.
  // XFAIL: target={{.+}}-pc-windows-msvc
 diff --git a/libcxx/test/std/language.support/support.start.term/quick_exit.pass.cpp b/libcxx/test/std/language.support/support.start.term/quick_exit.pass.cpp
-index 5a70ea5bd570..92dfbe8eb1ab 100644
+index d8eff69cb53f..e16048df722e 100644
 --- a/libcxx/test/std/language.support/support.start.term/quick_exit.pass.cpp
 +++ b/libcxx/test/std/language.support/support.start.term/quick_exit.pass.cpp
-@@ -16,6 +16,9 @@
+@@ -17,6 +17,9 @@
 
  // test quick_exit and at_quick_exit
 

patches/llvm-project/0002-libc-tests-with-picolibc-disable-large-tests.patch

@@ -1,4 +1,4 @@
-From 80000ddfade0f706ad1ebb488a51132a88cbe61d Mon Sep 17 00:00:00 2001
+From f007f1de21df336ec81d70da1fb5e29f7c129036 Mon Sep 17 00:00:00 2001
 From: =?UTF-8?q?Dominik=20W=C3=B3jt?= <[email protected]>
 Date: Wed, 15 Nov 2023 12:18:35 +0100
 Subject: [libc++] tests with picolibc: disable large tests

patches/llvm-project/0003-Disable-failing-compiler-rt-test.patch

@@ -1,4 +1,4 @@
-From c4837fa13ec89cc06b07af8cba8494189520e546 Mon Sep 17 00:00:00 2001
+From 427bdbdf7dd45baed77dfa62de8a062290c64ef7 Mon Sep 17 00:00:00 2001
 From: Piotr Przybyla <[email protected]>
 Date: Wed, 15 Nov 2023 16:04:24 +0000
 Subject: Disable failing compiler-rt test

patches/llvm-project/0004-libc-tests-with-picolibc-mark-sort-test-as-long-one.patch

@@ -1,4 +1,4 @@
-From ac480df06d78bd7457d2a6333be8578cda88c240 Mon Sep 17 00:00:00 2001
+From 46eee3644f998b186bb4b8a0ab7ed919ef6e6204 Mon Sep 17 00:00:00 2001
 From: =?UTF-8?q?Dominik=20W=C3=B3jt?= <[email protected]>
 Date: Thu, 9 Nov 2023 14:14:30 +0100
 Subject: [libc++] tests with picolibc: mark sort test as long one

patches/llvm-project/0005-libc-tests-with-picolibc-XFAIL-uses-of-atomics.patch

@@ -1,4 +1,4 @@
-From 3b7ada947d511fe0edb7cca0dbdb640d8e1ecd2b Mon Sep 17 00:00:00 2001
+From f1e3a99a85a8ff733c64ee9aab1dac53286a6cbf Mon Sep 17 00:00:00 2001
 From: =?UTF-8?q?Dominik=20W=C3=B3jt?= <[email protected]>
 Date: Thu, 9 Nov 2023 15:25:14 +0100
 Subject: [libc++] tests with picolibc: XFAIL uses of atomics
@@ -88,10 +88,10 @@ index 000000000000..5ecc58f3e385
 +if "has-no-atomics" in config.available_features:
 +    config.unsupported = True
 diff --git a/libcxx/utils/libcxx/test/features.py b/libcxx/utils/libcxx/test/features.py
-index 6ef40755c59d..6c2960260189 100644
+index e978875d543f..015db3bf6ed2 100644
 --- a/libcxx/utils/libcxx/test/features.py
 +++ b/libcxx/utils/libcxx/test/features.py
-@@ -206,6 +206,21 @@ DEFAULT_FEATURES = [
+@@ -215,6 +215,21 @@ DEFAULT_FEATURES = [
            """,
          ),
      ),

patches/llvm-project/0006-libc-tests-with-picolibc-mark-two-more-large-tests.patch

@@ -1,4 +1,4 @@
-From 8eb9344a4ba97b45cea1a6adec98aff6c6149359 Mon Sep 17 00:00:00 2001
+From 5ee90b274c191017e68c4e47b14f56f742d44679 Mon Sep 17 00:00:00 2001
 From: =?UTF-8?q?Dominik=20W=C3=B3jt?= <[email protected]>
 Date: Wed, 22 Nov 2023 16:12:39 +0100
 Subject: [libc++] tests with picolibc: mark two more large tests

patches/llvm-project/0007-Remove-ctime.timespec.compile.pass.cpp-xfail.patch → patches/llvm-project/0007-PATCH-Remove-ctime.timespec.compile.pass.cpp-xfail.patch

@@ -1,4 +1,4 @@
-From 062e640b82615fff780781e9d7d58a11a970e85f Mon Sep 17 00:00:00 2001
+From 0290e3effb05afaaee8b2c6b698a478a27328a84 Mon Sep 17 00:00:00 2001
 From: David Candler <[email protected]>
 Date: Mon, 9 Sep 2024 13:55:35 +0100
 Subject: [PATCH] Remove ctime.timespec.compile.pass.cpp xfail

patches/llvm-project/0008-libc-AArch64-Add-an-AArch64-setjmp-longjmp-101177.patch → patches/llvm-project/0008-PATCH-libc-AArch64-Add-an-AArch64-setjmp-longjmp.-10.patch

@@ -1,4 +1,4 @@
-From cf044b4ec3224d65603bb1805d870a3c111bc297 Mon Sep 17 00:00:00 2001
+From d5d8fc34ff6062bde7cc4de0434cfcd65a9a26d6 Mon Sep 17 00:00:00 2001
 From: Simon Tatham <[email protected]>
 Date: Wed, 31 Jul 2024 17:09:52 +0100
 Subject: [PATCH] [libc][AArch64] Add an AArch64 setjmp/longjmp. (#101177)

patches/llvm-project/0009-DAGISel-Keep-flags-when-converting-FP-load-store-to-.patch

@@ -0,0 +1,103 @@
+From 3c1ac713817946d3475fbaf02b9e9d5e67823e89 Mon Sep 17 00:00:00 2001
+From: Oliver Stannard <[email protected]>
+Date: Thu, 10 Oct 2024 10:17:50 +0200
+Subject: [DAGISel] Keep flags when converting FP load/store to integer
+ (#111679)
+
+This DAG combine replaces a floating-point load/store pair which has no
+other uses with an integer one, but did not copy the memory operand
+flags to the new instructions, resulting in it dropping the volatile
+flag. This optimisation is still valid if one or both of the
+instructions is volatile, so we can copy over the whole
+MachineMemOperand to generate volatile integer loads and stores where
+needed.
+---
+ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 10 ++++----
+ .../CodeGen/ARM/load-store-pair-volatile.ll   | 24 +++++++++++++++++++
+ llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll   | 10 ++++----
+ 3 files changed, 33 insertions(+), 11 deletions(-)
+ create mode 100644 llvm/test/CodeGen/ARM/load-store-pair-volatile.ll
+
+diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+index 7b1f1dc40211..030670c98af8 100644
+--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
++++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+@@ -20045,13 +20045,11 @@ SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) {
+         !FastLD || !FastST)
+       return SDValue();
+
+-    SDValue NewLD =
+-        DAG.getLoad(IntVT, SDLoc(Value), LD->getChain(), LD->getBasePtr(),
+-                    LD->getPointerInfo(), LD->getAlign());
++    SDValue NewLD = DAG.getLoad(IntVT, SDLoc(Value), LD->getChain(),
++                                LD->getBasePtr(), LD->getMemOperand());
+
+-    SDValue NewST =
+-        DAG.getStore(ST->getChain(), SDLoc(N), NewLD, ST->getBasePtr(),
+-                     ST->getPointerInfo(), ST->getAlign());
++    SDValue NewST = DAG.getStore(ST->getChain(), SDLoc(N), NewLD,
++                                 ST->getBasePtr(), ST->getMemOperand());
+
+     AddToWorklist(NewLD.getNode());
+     AddToWorklist(NewST.getNode());
+diff --git a/llvm/test/CodeGen/ARM/load-store-pair-volatile.ll b/llvm/test/CodeGen/ARM/load-store-pair-volatile.ll
+new file mode 100644
+index 000000000000..6278672d9e23
+--- /dev/null
++++ b/llvm/test/CodeGen/ARM/load-store-pair-volatile.ll
+@@ -0,0 +1,24 @@
++; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
++; RUN: llc -mtriple=arm-none-eabi -stop-after=finalize-isel < %s | FileCheck %s
++
++define void @test(ptr %vol_one, ptr %p_in, ptr %p_out, i32 %n) {
++  ; CHECK-LABEL: name: test
++  ; CHECK: bb.0.entry:
++  ; CHECK-NEXT:   liveins: $r0, $r1, $r2
++  ; CHECK-NEXT: {{  $}}
++  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $r2
++  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $r1
++  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr = COPY $r0
++  ; CHECK-NEXT:   [[LDRi12_:%[0-9]+]]:gpr = LDRi12 [[COPY1]], 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.p_in)
++  ; CHECK-NEXT:   STRi12 killed [[LDRi12_]], [[COPY2]], 0, 14 /* CC::al */, $noreg :: (volatile store (s32) into %ir.vol_one)
++  ; CHECK-NEXT:   [[LDRi12_1:%[0-9]+]]:gpr = LDRi12 [[COPY2]], 4, 14 /* CC::al */, $noreg :: (volatile load (s32) from %ir.vol_two)
++  ; CHECK-NEXT:   STRi12 killed [[LDRi12_1]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.p_out)
++  ; CHECK-NEXT:   MOVPCLR 14 /* CC::al */, $noreg
++entry:
++  %vol_two = getelementptr inbounds i8, ptr %vol_one, i32 4
++  %a = load float, ptr %p_in, align 4
++  store volatile float %a, ptr %vol_one, align 4
++  %b = load volatile float, ptr %vol_two, align 4
++  store float %b, ptr %p_out, align 4
++  ret void
++}
+diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll b/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
+index ccc36530c795..150fa91524ab 100644
+--- a/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
++++ b/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
+@@ -1442,8 +1442,8 @@ define void @caller_fpr_stack() {
+   ; 32BIT-NEXT:   renamable $r4 = LWZtoc @f14, $r2 :: (load (s32) from got)
+   ; 32BIT-NEXT:   renamable $f0 = LFD 0, killed renamable $r3 :: (dereferenceable load (s64) from @d15)
+   ; 32BIT-NEXT:   renamable $r5 = LWZtoc @f16, $r2 :: (load (s32) from got)
+-  ; 32BIT-NEXT:   renamable $r3 = LWZ 0, killed renamable $r4 :: (load (s32) from @f14)
+-  ; 32BIT-NEXT:   renamable $r4 = LWZ 0, killed renamable $r5 :: (load (s32) from @f16)
++  ; 32BIT-NEXT:   renamable $r3 = LWZ 0, killed renamable $r4 :: (dereferenceable load (s32) from @f14)
++  ; 32BIT-NEXT:   renamable $r4 = LWZ 0, killed renamable $r5 :: (dereferenceable load (s32) from @f16)
+   ; 32BIT-NEXT:   ADJCALLSTACKDOWN 144, 0, implicit-def dead $r1, implicit $r1
+   ; 32BIT-NEXT:   renamable $r5 = LI 0
+   ; 32BIT-NEXT:   renamable $r6 = LIS 16352
+@@ -1532,9 +1532,9 @@ define void @caller_fpr_stack() {
+   ; 64BIT-NEXT:   renamable $x3 = LDtoc @f14, $x2 :: (load (s64) from got)
+   ; 64BIT-NEXT:   renamable $x4 = LDtoc @d15, $x2 :: (load (s64) from got)
+   ; 64BIT-NEXT:   renamable $x5 = LDtoc @f16, $x2 :: (load (s64) from got)
+-  ; 64BIT-NEXT:   renamable $r3 = LWZ 0, killed renamable $x3 :: (load (s32) from @f14)
+-  ; 64BIT-NEXT:   renamable $x4 = LD 0, killed renamable $x4 :: (load (s64) from @d15)
+-  ; 64BIT-NEXT:   renamable $r5 = LWZ 0, killed renamable $x5 :: (load (s32) from @f16)
++  ; 64BIT-NEXT:   renamable $r3 = LWZ 0, killed renamable $x3 :: (dereferenceable load (s32) from @f14)
++  ; 64BIT-NEXT:   renamable $x4 = LD 0, killed renamable $x4 :: (dereferenceable load (s64) from @d15)
++  ; 64BIT-NEXT:   renamable $r5 = LWZ 0, killed renamable $x5 :: (dereferenceable load (s32) from @f16)
+   ; 64BIT-NEXT:   ADJCALLSTACKDOWN 176, 0, implicit-def dead $r1, implicit $r1
+   ; 64BIT-NEXT:   renamable $x6 = LDtocCPT %const.0, $x2 :: (load (s64) from got)
+   ; 64BIT-NEXT:   STW killed renamable $r5, 168, $x1 :: (store (s32))
+-- 
+2.34.1
+