GitHub - AJacquin/verilator-unisims: This is mainly a simulation library of xilinx primitives that are verilator compatible.

AJacquin / verilator-unisims Public

forked from uwsampl/verilator-unisims

This is mainly a simulation library of xilinx primitives that are verilator compatible.

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Name		Name	Last commit message	Last commit date
Latest commit History 41 Commits
.gitignore		.gitignore
BUFG.v		BUFG.v
BUFGCE.v		BUFGCE.v
BUFGMUX.v		BUFGMUX.v
BUFIO.v		BUFIO.v
BUFIO2.v		BUFIO2.v
BUFPLL.v		BUFPLL.v
BUFR.v		BUFR.v
DCM_SP.v		DCM_SP.v
DNA_PORT.v		DNA_PORT.v
DSP48E1.v		DSP48E1.v
DSP48E2.v		DSP48E2.v
FD.v		FD.v
FDC.v		FDC.v
FDE.v		FDE.v
FDP.v		FDP.v
FDR.v		FDR.v
FDRE.v		FDRE.v
FDS.v		FDS.v
FDSE.v		FDSE.v
GND.v		GND.v
IBUFDS.v		IBUFDS.v
IBUFGDS.v		IBUFGDS.v
IDDR2.v		IDDR2.v
INV.v		INV.v
IOBUF.v		IOBUF.v
IODELAY2.v		IODELAY2.v
ISERDES2.v		ISERDES2.v
LDC.v		LDC.v
LUT1.v		LUT1.v
LUT2.v		LUT2.v
LUT3.v		LUT3.v
LUT4.v		LUT4.v
LUT5.v		LUT5.v
LUT6.v		LUT6.v
LUT6_2.v		LUT6_2.v
MMCME2_BASE.v		MMCME2_BASE.v
MULT_AND.v		MULT_AND.v
MUXCY.v		MUXCY.v
MUXCY_L.v		MUXCY_L.v
MUXF5.v		MUXF5.v
MUXF6.v		MUXF6.v
MUXF7.v		MUXF7.v
OBUFDS.v		OBUFDS.v
OBUFT.sv		OBUFT.sv
ODDR.v		ODDR.v
ODDR2.v		ODDR2.v
OSERDES2.v		OSERDES2.v
PLL_BASE.v		PLL_BASE.v
RAM16X1D.v		RAM16X1D.v
RAM32X1D.v		RAM32X1D.v
RAMB16BWER.v		RAMB16BWER.v
README		README
SRL16E.v		SRL16E.v
URAM288.v		URAM288.v
VCC.v		VCC.v
XORCY.v		XORCY.v
dyn_reconf.v		dyn_reconf.v
freq_gen.v		freq_gen.v
period_check.v		period_check.v
period_count.v		period_count.v
phase_shift.v		phase_shift.v
pll.v		pll.v

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This is mainly a simulation library of xilinx primitives that are
verilator compatible.

This is mainly a simulation library of xilinx primitives that are verilator compatible.

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