diff --git a/include/zephyr/dt-bindings/acpi/acpi.h b/include/zephyr/dt-bindings/acpi/acpi.h
index 6084aebb7a83..8c545b538a5a 100644
--- a/include/zephyr/dt-bindings/acpi/acpi.h
+++ b/include/zephyr/dt-bindings/acpi/acpi.h
@@ -3,6 +3,10 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ACPI_ACPI_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_ACPI_ACPI_H_
 
 #define ACPI_IRQ_DETECT 0xFFFFFFFU
 #define ACPI_IRQ_FLAG_DETECT 0xFFFFFFFU
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ACPI_ACPI_H_ */
diff --git a/include/zephyr/dt-bindings/adc/stm32_adc.h b/include/zephyr/dt-bindings/adc/stm32_adc.h
index b2020d214233..fbf1329e34b1 100644
--- a/include/zephyr/dt-bindings/adc/stm32_adc.h
+++ b/include/zephyr/dt-bindings/adc/stm32_adc.h
@@ -3,8 +3,8 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_STM32_ADC_H_
-#define ZEPHYR_INCLUDE_DT_BINDINGS_STM32_ADC_H_
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADC_STM32_ADC_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_ADC_STM32_ADC_H_
 
 #include <zephyr/dt-bindings/adc/adc.h>
 
@@ -64,4 +64,24 @@
 	STM32_ADC(resolution, reg_val, STM32_ADC_RES_MASK, STM32_ADC_RES_SHIFT, \
 		  STM32_ADC_RES_REG)
 
-#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_STM32_ADC_H_ */
+/**
+ * @name STM32 ADC clock source
+ * This value is to set <st,adc-clock-source>
+ * One or both values may not apply to all series. Refer to the RefMan
+ * @{
+ */
+#define SYNC  1
+#define ASYNC 2
+/** @} */
+
+/**
+ * @name STM32 ADC sequencer type
+ * This value is to set <st,adc-sequencer>
+ * One or both values may not apply to all series. Refer to the RefMan
+ * @{
+ */
+#define NOT_FULLY_CONFIGURABLE	0
+#define FULLY_CONFIGURABLE	1
+/** @} */
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADC_STM32_ADC_H_ */
diff --git a/include/zephyr/dt-bindings/adc/stm32f1_adc.h b/include/zephyr/dt-bindings/adc/stm32f1_adc.h
index fc1ee78238ad..1a45adb303f6 100644
--- a/include/zephyr/dt-bindings/adc/stm32f1_adc.h
+++ b/include/zephyr/dt-bindings/adc/stm32f1_adc.h
@@ -3,8 +3,8 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_STM32F1_ADC_H_
-#define ZEPHYR_INCLUDE_DT_BINDINGS_STM32F1_ADC_H_
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADC_STM32F1_ADC_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_ADC_STM32F1_ADC_H_
 
 #include <zephyr/dt-bindings/adc/stm32_adc.h>
 
@@ -23,4 +23,4 @@
 #define STM32F1_ADC_RES(resolution)	\
 	STM32_ADC_RES(resolution, STM32_ADC_RES_REG_VAL)
 
-#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_STM32F1_ADC_H_ */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADC_STM32F1_ADC_H_ */
diff --git a/include/zephyr/dt-bindings/adc/stm32f4_adc.h b/include/zephyr/dt-bindings/adc/stm32f4_adc.h
index 9a50cbc7b03c..067091476844 100644
--- a/include/zephyr/dt-bindings/adc/stm32f4_adc.h
+++ b/include/zephyr/dt-bindings/adc/stm32f4_adc.h
@@ -3,8 +3,8 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_STM32F4_ADC_H_
-#define ZEPHYR_INCLUDE_DT_BINDINGS_STM32F4_ADC_H_
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADC_STM32F4_ADC_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_ADC_STM32F4_ADC_H_
 
 #include <zephyr/dt-bindings/adc/stm32_adc.h>
 
@@ -13,4 +13,4 @@
 #define STM32_ADC_RES_SHIFT	24
 #define STM32_ADC_RES_MASK	BIT_MASK(2)
 
-#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_STM32F4_ADC_H_ */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADC_STM32F4_ADC_H_ */
diff --git a/include/zephyr/dt-bindings/adc/stm32h7_adc.h b/include/zephyr/dt-bindings/adc/stm32h7_adc.h
index c2a914233e76..10ea15cecafa 100644
--- a/include/zephyr/dt-bindings/adc/stm32h7_adc.h
+++ b/include/zephyr/dt-bindings/adc/stm32h7_adc.h
@@ -3,8 +3,8 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_STM32H7_ADC_H_
-#define ZEPHYR_INCLUDE_DT_BINDINGS_STM32H7_ADC_H_
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADC_STM32H7_ADC_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_ADC_STM32H7_ADC_H_
 
 #include <zephyr/dt-bindings/adc/stm32_adc.h>
 
@@ -24,4 +24,4 @@
 	STM32_ADC(resolution, reg_val, STM32H72X_ADC3_RES_MASK, \
 		  STM32H72X_ADC3_RES_SHIFT, STM32_ADC_RES_REG)
 
-#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_STM32H7_ADC_H_ */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADC_STM32H7_ADC_H_ */
diff --git a/include/zephyr/dt-bindings/adc/stm32l4_adc.h b/include/zephyr/dt-bindings/adc/stm32l4_adc.h
index 20decbdb0d7b..4f2a288b166b 100644
--- a/include/zephyr/dt-bindings/adc/stm32l4_adc.h
+++ b/include/zephyr/dt-bindings/adc/stm32l4_adc.h
@@ -3,8 +3,8 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_STM32L4_ADC_H_
-#define ZEPHYR_INCLUDE_DT_BINDINGS_STM32L4_ADC_H_
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADC_STM32L4_ADC_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_ADC_STM32L4_ADC_H_
 
 #include <zephyr/dt-bindings/adc/stm32_adc.h>
 
@@ -13,4 +13,4 @@
 #define STM32_ADC_RES_SHIFT	3
 #define STM32_ADC_RES_MASK	BIT_MASK(2)
 
-#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_STM32L4_ADC_H_ */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADC_STM32L4_ADC_H_ */
diff --git a/include/zephyr/dt-bindings/adc/stm32u5_adc.h b/include/zephyr/dt-bindings/adc/stm32u5_adc.h
index f4efab96b6ff..4c38e40e9256 100644
--- a/include/zephyr/dt-bindings/adc/stm32u5_adc.h
+++ b/include/zephyr/dt-bindings/adc/stm32u5_adc.h
@@ -3,8 +3,8 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_STM32U5_ADC_H_
-#define ZEPHYR_INCLUDE_DT_BINDINGS_STM32U5_ADC_H_
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADC_STM32U5_ADC_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_ADC_STM32U5_ADC_H_
 
 #include <zephyr/dt-bindings/adc/stm32_adc.h>
 
@@ -13,4 +13,4 @@
 #define STM32_ADC_RES_SHIFT	2
 #define STM32_ADC_RES_MASK	BIT_MASK(2)
 
-#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_STM32U5_ADC_H_ */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADC_STM32U5_ADC_H_ */
diff --git a/include/zephyr/dt-bindings/clock/ch32v00x-clocks.h b/include/zephyr/dt-bindings/clock/ch32v00x-clocks.h
index 128e370e6117..07ad65df31cf 100644
--- a/include/zephyr/dt-bindings/clock/ch32v00x-clocks.h
+++ b/include/zephyr/dt-bindings/clock/ch32v00x-clocks.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef __CH32V00X_CLOCKS_H__
-#define __CH32V00X_CLOCKS_H__
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_CH32V00X_CLOCKS_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_CH32V00X_CLOCKS_H_
 
 #define CH32V00X_AHB_PCENR_OFFSET  0
 #define CH32V00X_APB2_PCENR_OFFSET 1
@@ -39,4 +39,4 @@
 #define CH32V00X_CLOCK_PWR    CH32V00X_CLOCK_CONFIG(APB1, 28)
 #define CH32V00X_CLOCK_USB    CH32V00X_CLOCK_CONFIG(APB1, 23)
 
-#endif
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_CH32V00X_CLOCKS_H_ */
diff --git a/include/zephyr/dt-bindings/clock/imx8ulp_clock.h b/include/zephyr/dt-bindings/clock/imx8ulp_clock.h
index 3de43dc3e968..db2a5d0eddb1 100644
--- a/include/zephyr/dt-bindings/clock/imx8ulp_clock.h
+++ b/include/zephyr/dt-bindings/clock/imx8ulp_clock.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef _INCLUDE_ZEPHYR_DT_BINDINGS_CLOCK_IMX8ULP_CLOCK_H_
-#define _INCLUDE_ZEPHYR_DT_BINDINGS_CLOCK_IMX8ULP_CLOCK_H_
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX8ULP_CLOCK_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX8ULP_CLOCK_H_
 
 /* IMPORTANT: the indexes used by these macros need to
  * match the indexes in the PCC driver LUT at which the
@@ -15,4 +15,4 @@
 /* clocks managed by PCC4 */
 #define IMX8ULP_CLOCK_LPUART7 0
 
-#endif /* _INCLUDE_ZEPHYR_DT_BINDINGS_CLOCK_IMX8ULP_CLOCK_H_ */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX8ULP_CLOCK_H_ */
diff --git a/include/zephyr/dt-bindings/clock/r7fa4m1xxxxxx-clock.h b/include/zephyr/dt-bindings/clock/r7fa4m1xxxxxx-clock.h
index 355c4982a3d3..b27fc884bd87 100644
--- a/include/zephyr/dt-bindings/clock/r7fa4m1xxxxxx-clock.h
+++ b/include/zephyr/dt-bindings/clock/r7fa4m1xxxxxx-clock.h
@@ -4,9 +4,9 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef ZEPHYR_DT_BINDINGS_CLOCK_R7FA4M1XXXXXX_CLOCK_H_
-#define ZEPHYR_DT_BINDINGS_CLOCK_R7FA4M1XXXXXX_CLOCK_H_
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_R7FA4M1XXXXXX_CLOCK_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_R7FA4M1XXXXXX_CLOCK_H_
 
 #include <zephyr/dt-bindings/clock/renesas-ra-cgc.h>
 
-#endif /* ZEPHYR_DT_BINDINGS_CLOCK_R7FA4M1XXXXXX_CLOCK_H_ */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_R7FA4M1XXXXXX_CLOCK_H_ */
diff --git a/include/zephyr/dt-bindings/clock/ra_clock.h b/include/zephyr/dt-bindings/clock/ra_clock.h
index 97fc2e41b560..8268386f6787 100644
--- a/include/zephyr/dt-bindings/clock/ra_clock.h
+++ b/include/zephyr/dt-bindings/clock/ra_clock.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RA_H_
-#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RA_H_
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RA_CLOCK_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RA_CLOCK_H_
 
 #define MSTPA 0
 #define MSTPB 1
@@ -13,4 +13,4 @@
 #define MSTPD 3
 #define MSTPE 4
 
-#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RA_H_ */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RA_CLOCK_H_ */
diff --git a/include/zephyr/dt-bindings/clock/scg_k4.h b/include/zephyr/dt-bindings/clock/scg_k4.h
index 985629a1f697..0299c2f5eb16 100644
--- a/include/zephyr/dt-bindings/clock/scg_k4.h
+++ b/include/zephyr/dt-bindings/clock/scg_k4.h
@@ -2,6 +2,8 @@
  * Copyright 2023 NXP
  * SPDX-License-Identifier: Apache-2.0
  */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SCG_K4_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SCG_K4_H_
 
 #define SCG_K4_CORESYS_CLK 0U
 #define SCG_K4_SLOW_CLK    1U
@@ -12,3 +14,5 @@
 #define SCG_K4_SIRC_CLK    6U
 #define SCG_K4_FIRC_CLK    7U
 #define SCG_K4_RTCOSC_CLK  8U
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SCG_K4_H_ */
diff --git a/include/zephyr/dt-bindings/dai/esai.h b/include/zephyr/dt-bindings/dai/esai.h
index cc0150135001..5511f6c0d09d 100644
--- a/include/zephyr/dt-bindings/dai/esai.h
+++ b/include/zephyr/dt-bindings/dai/esai.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef _INCLUDE_ZEPHYR_DT_BINDINGS_DAI_ESAI_H_
-#define _INCLUDE_ZEPHYR_DT_BINDINGS_DAI_ESAI_H_
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DAI_ESAI_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_DAI_ESAI_H_
 
 /* ESAI pin IDs
  * the values of these macros are meant to match
@@ -51,4 +51,4 @@
 #define ESAI_CLOCK_INPUT 0
 #define ESAI_CLOCK_OUTPUT 1
 
-#endif /* _INCLUDE_ZEPHYR_DT_BINDINGS_DAI_ESAI_H_ */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DAI_ESAI_H_ */
diff --git a/include/zephyr/dt-bindings/dma/gd32_dma.h b/include/zephyr/dt-bindings/dma/gd32_dma.h
index 0f71fa1e7e42..893a691940cc 100644
--- a/include/zephyr/dt-bindings/dma/gd32_dma.h
+++ b/include/zephyr/dt-bindings/dma/gd32_dma.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GD32_DMA_H_
-#define ZEPHYR_INCLUDE_DT_BINDINGS_GD32_DMA_H_
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_GD32_DMA_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_GD32_DMA_H_
 
 /* macros for channel-cfg */
 
@@ -47,4 +47,4 @@
 #define GD32_DMA_PRIORITY_HIGH	      GD32_DMA_CH_CFG_PRIORITY(2)
 #define GD32_DMA_PRIORITY_VERY_HIGH   GD32_DMA_CH_CFG_PRIORITY(3)
 
-#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GD32_DMA_H_ */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_GD32_DMA_H_ */
diff --git a/include/zephyr/dt-bindings/dma/stm32_dma.h b/include/zephyr/dt-bindings/dma/stm32_dma.h
index a6c1448b4a95..6eb1e5be139f 100644
--- a/include/zephyr/dt-bindings/dma/stm32_dma.h
+++ b/include/zephyr/dt-bindings/dma/stm32_dma.h
@@ -3,8 +3,8 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_STM32_DMA_H_
-#define ZEPHYR_INCLUDE_DT_BINDINGS_STM32_DMA_H_
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_STM32_DMA_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_STM32_DMA_H_
 
 /**
  * @name custom DMA flags for channel configuration
@@ -70,4 +70,4 @@
 
 /** @} */
 
-#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_STM32_DMA_H_ */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_STM32_DMA_H_ */
diff --git a/include/zephyr/dt-bindings/ethernet/nxp_enet.h b/include/zephyr/dt-bindings/ethernet/nxp_enet.h
index 0e307c9ebfc6..0771ad757e03 100644
--- a/include/zephyr/dt-bindings/ethernet/nxp_enet.h
+++ b/include/zephyr/dt-bindings/ethernet/nxp_enet.h
@@ -4,12 +4,12 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_NXP_ENET_H_
-#define ZEPHYR_INCLUDE_DT_BINDINGS_NXP_ENET_H_
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ETHERNET_NXP_ENET_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_ETHERNET_NXP_ENET_H_
 
 #define NXP_ENET_MII_MODE	0
 #define NXP_ENET_RMII_MODE	1
 #define NXP_ENET_RGMII_MODE	2
 #define NXP_ENET_INVALID_MII_MODE 100
 
-#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_NXP_ENET_H_ */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ETHERNET_NXP_ENET_H_ */
diff --git a/include/zephyr/dt-bindings/flash_controller/npcx_fiu_qspi.h b/include/zephyr/dt-bindings/flash_controller/npcx_fiu_qspi.h
index c214218f523e..20112be26b6e 100644
--- a/include/zephyr/dt-bindings/flash_controller/npcx_fiu_qspi.h
+++ b/include/zephyr/dt-bindings/flash_controller/npcx_fiu_qspi.h
@@ -3,8 +3,8 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NPCK_FIU_QSPI_H_
-#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NPCK_FIU_QSPI_H_
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_FLASH_CONTROLLER_NPCX_FIU_QSPI_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_FLASH_CONTROLLER_NPCX_FIU_QSPI_H_
 
 #include <zephyr/dt-bindings/dt-util.h>
 
@@ -22,4 +22,4 @@
 #define NPCX_RD_MODE_FAST	1
 #define NPCX_RD_MODE_FAST_DUAL	3
 
-#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NPCK_FIU_QSPI_H_ */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_FLASH_CONTROLLER_NPCX_FIU_QSPI_H_ */
diff --git a/include/zephyr/dt-bindings/flash_controller/ospi.h b/include/zephyr/dt-bindings/flash_controller/ospi.h
index 14148d95ab3d..e903405999ef 100644
--- a/include/zephyr/dt-bindings/flash_controller/ospi.h
+++ b/include/zephyr/dt-bindings/flash_controller/ospi.h
@@ -3,8 +3,8 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_OSPI_H_
-#define ZEPHYR_INCLUDE_DT_BINDINGS_OSPI_H_
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_FLASH_CONTROLLER_OSPI_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_FLASH_CONTROLLER_OSPI_H_
 
 /**
  * @name OSPI definition for the OctoSPI peripherals
@@ -30,4 +30,4 @@
 /* Double Transfer Rate */
 #define OSPI_DTR_TRANSFER                 2
 
-#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_OSPI_H_ */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_FLASH_CONTROLLER_OSPI_H_ */
diff --git a/include/zephyr/dt-bindings/flash_controller/xspi.h b/include/zephyr/dt-bindings/flash_controller/xspi.h
index f847258889c0..d64b877aed20 100644
--- a/include/zephyr/dt-bindings/flash_controller/xspi.h
+++ b/include/zephyr/dt-bindings/flash_controller/xspi.h
@@ -3,8 +3,8 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_XSPI_H_
-#define ZEPHYR_INCLUDE_DT_BINDINGS_XSPI_H_
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_FLASH_CONTROLLER_XSPI_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_FLASH_CONTROLLER_XSPI_H_
 
 /**
  * @name XSPI definition for the xSPI peripherals
@@ -28,4 +28,4 @@
 /* Double Transfer Rate */
 #define XSPI_DTR_TRANSFER                 2
 
-#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_XSPI_H_ */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_FLASH_CONTROLLER_XSPI_H_ */
diff --git a/include/zephyr/dt-bindings/gnss/u_blox_m8.h b/include/zephyr/dt-bindings/gnss/u_blox_m8.h
index 26117e632592..38ab27eee00e 100644
--- a/include/zephyr/dt-bindings/gnss/u_blox_m8.h
+++ b/include/zephyr/dt-bindings/gnss/u_blox_m8.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_U_BLOX_M8_H_
-#define ZEPHYR_INCLUDE_DT_BINDINGS_U_BLOX_M8_H_
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GNSS_U_BLOX_M8_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_GNSS_U_BLOX_M8_H_
 
 #include <zephyr/dt-bindings/dt-util.h>
 
@@ -20,4 +20,4 @@
 #define UBX_M8_UART_BAUDRATE_460800	0x07
 #define UBX_M8_UART_BAUDRATE_921600	0x08
 
-#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_U_BLOX_M8_H_ */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GNSS_U_BLOX_M8_H_ */
diff --git a/include/zephyr/dt-bindings/gpio/st-morpho-header.h b/include/zephyr/dt-bindings/gpio/st-morpho-header.h
index 82047c391cb0..12f537d8b8d0 100644
--- a/include/zephyr/dt-bindings/gpio/st-morpho-header.h
+++ b/include/zephyr/dt-bindings/gpio/st-morpho-header.h
@@ -2,8 +2,8 @@
  * Copyright (c) 2023 Teslabs Engineering S.L.
  * SPDX-License-Identifier: Apache-2.0
  */
-#ifndef INCLUDE_ZEPHYR_DT_BINDINGS_GPIO_ST_MORPHO_HEADER_H_
-#define INCLUDE_ZEPHYR_DT_BINDINGS_GPIO_ST_MORPHO_HEADER_H_
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ST_MORPHO_HEADER_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ST_MORPHO_HEADER_H_
 
 /** ST Morpho pin mask (0...143). */
 #define ST_MORPHO_PIN_MASK 0xFF
@@ -160,4 +160,4 @@
 
 /** @} */
 
-#endif /* INCLUDE_ZEPHYR_DT_BINDINGS_GPIO_ST_MORPHO_HEADER_H_ */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ST_MORPHO_HEADER_H_ */
diff --git a/include/zephyr/dt-bindings/i2c/it8xxx2-i2c.h b/include/zephyr/dt-bindings/i2c/it8xxx2-i2c.h
index 199e813308ec..ff40e7f0fc32 100644
--- a/include/zephyr/dt-bindings/i2c/it8xxx2-i2c.h
+++ b/include/zephyr/dt-bindings/i2c/it8xxx2-i2c.h
@@ -3,8 +3,8 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_I2C_IT8XXX2_H_
-#define ZEPHYR_INCLUDE_DT_BINDINGS_I2C_IT8XXX2_H_
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_I2C_IT8XXX2_I2C_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_I2C_IT8XXX2_I2C_H_
 
 
 #define IT8XXX2_ECPM_CGCTRL4R_OFF	0x09
@@ -28,4 +28,4 @@
 #define I2C_CHE_LOCATE		4
 #define I2C_CHF_LOCATE		5
 
-#endif	/* ZEPHYR_INCLUDE_DT_BINDINGS_I2C_IT8XXX2_H_ */
+#endif	/* ZEPHYR_INCLUDE_DT_BINDINGS_I2C_IT8XXX2_I2C_H_ */
diff --git a/include/zephyr/dt-bindings/input/cst816s-gesture-codes.h b/include/zephyr/dt-bindings/input/cst816s-gesture-codes.h
index ec96e193279c..2428f6a782c8 100644
--- a/include/zephyr/dt-bindings/input/cst816s-gesture-codes.h
+++ b/include/zephyr/dt-bindings/input/cst816s-gesture-codes.h
@@ -15,4 +15,4 @@
 #define CST816S_GESTURE_CODE_DOUBLE_CLICK 0x0B
 #define CST816S_GESTURE_CODE_LONG_PRESS   0x0C
 
-#endif
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INPUT_CST816S_GESTURE_CODES_H_ */
diff --git a/include/zephyr/dt-bindings/inputmux/inputmux_trigger_ports.h b/include/zephyr/dt-bindings/inputmux/inputmux_trigger_ports.h
index d348dce7030e..373ebab06b49 100644
--- a/include/zephyr/dt-bindings/inputmux/inputmux_trigger_ports.h
+++ b/include/zephyr/dt-bindings/inputmux/inputmux_trigger_ports.h
@@ -21,4 +21,4 @@
 #define LPC55S36_DMA1_OTRIG_BASE 0x24000002
 #define LPC55S36_DMA1_ITRIG_BASE 0x20000008
 
-#endif
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INPUTMUX_TRIGGER_PORTS_H_ */
diff --git a/include/zephyr/dt-bindings/interrupt-controller/arm-gic.h b/include/zephyr/dt-bindings/interrupt-controller/arm-gic.h
index 5e33911d11a4..522b237e0a6a 100644
--- a/include/zephyr/dt-bindings/interrupt-controller/arm-gic.h
+++ b/include/zephyr/dt-bindings/interrupt-controller/arm-gic.h
@@ -3,8 +3,8 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#ifndef __DT_BINDING_ARM_GIC_H
-#define __DT_BINDING_ARM_GIC_H
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H_
 
 #include <zephyr/dt-bindings/dt-util.h>
 
@@ -26,4 +26,4 @@
 
 #define IRQ_DEFAULT_PRIORITY	0xa0
 
-#endif
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H_ */
diff --git a/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c2-intmux.h b/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c2-intmux.h
index 5f4cd793f181..9be7246c667d 100644
--- a/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c2-intmux.h
+++ b/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c2-intmux.h
@@ -59,4 +59,4 @@
 
 #define ESP_INTR_FLAG_SHARED	(1<<8)	/* Interrupt can be shared between ISRs */
 
-#endif
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C2_INTMUX_H_ */
diff --git a/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c3-intmux.h b/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c3-intmux.h
index f6059000505c..2dcf67d73da2 100644
--- a/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c3-intmux.h
+++ b/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c3-intmux.h
@@ -78,4 +78,4 @@
 
 #define ESP_INTR_FLAG_SHARED	(1<<8)	/* Interrupt can be shared between ISRs */
 
-#endif
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C3_INTMUX_H_ */
diff --git a/include/zephyr/dt-bindings/interrupt-controller/esp-xtensa-intmux.h b/include/zephyr/dt-bindings/interrupt-controller/esp-xtensa-intmux.h
index 32194e69a483..c9efd890a173 100644
--- a/include/zephyr/dt-bindings/interrupt-controller/esp-xtensa-intmux.h
+++ b/include/zephyr/dt-bindings/interrupt-controller/esp-xtensa-intmux.h
@@ -86,4 +86,4 @@
 
 #define ESP_INTR_FLAG_SHARED	(1<<8)	/* Interrupt can be shared between ISRs */
 
-#endif
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_XTENSA_INTMUX_H_ */
diff --git a/include/zephyr/dt-bindings/interrupt-controller/esp32s2-xtensa-intmux.h b/include/zephyr/dt-bindings/interrupt-controller/esp32s2-xtensa-intmux.h
index 383f9a62306e..ba26891b6bde 100644
--- a/include/zephyr/dt-bindings/interrupt-controller/esp32s2-xtensa-intmux.h
+++ b/include/zephyr/dt-bindings/interrupt-controller/esp32s2-xtensa-intmux.h
@@ -113,4 +113,4 @@
 
 #define ESP_INTR_FLAG_SHARED	(1<<8)	/* Interrupt can be shared between ISRs */
 
-#endif
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32S2_XTENSA_INTMUX_H_ */
diff --git a/include/zephyr/dt-bindings/interrupt-controller/esp32s3-xtensa-intmux.h b/include/zephyr/dt-bindings/interrupt-controller/esp32s3-xtensa-intmux.h
index 87c690606f60..a1d34baaaf03 100644
--- a/include/zephyr/dt-bindings/interrupt-controller/esp32s3-xtensa-intmux.h
+++ b/include/zephyr/dt-bindings/interrupt-controller/esp32s3-xtensa-intmux.h
@@ -111,4 +111,4 @@
 
 #define ESP_INTR_FLAG_SHARED	(1<<8)	/* Interrupt can be shared between ISRs */
 
-#endif
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32S3_XTENSA_INTMUX_H_ */
diff --git a/include/zephyr/dt-bindings/interrupt-controller/intel-ioapic.h b/include/zephyr/dt-bindings/interrupt-controller/intel-ioapic.h
index 8637c6de7ef0..246590b884b9 100644
--- a/include/zephyr/dt-bindings/interrupt-controller/intel-ioapic.h
+++ b/include/zephyr/dt-bindings/interrupt-controller/intel-ioapic.h
@@ -28,4 +28,4 @@
 #define IRQ_TYPE_FIXED_LEVEL_HIGH		(IRQ_DELIVERY_FIXED | IRQ_TYPE_LEVEL | IRQ_TYPE_HIGH)
 #define IRQ_TYPE_FIXED_LEVEL_LOW		(IRQ_DELIVERY_FIXED | IRQ_TYPE_LEVEL | IRQ_TYPE_LOW)
 
-#endif
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_INTEL_IOAPIC_H_ */
diff --git a/include/zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h b/include/zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h
index 1acf552c8595..83470ae74e77 100644
--- a/include/zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h
+++ b/include/zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h
@@ -3,8 +3,8 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#ifndef __DT_BINDING_MCHP_XEC_ECIA_H
-#define __DT_BINDING_MCHP_XEC_ECIA_H
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_MCHP_XEC_ECIA_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_MCHP_XEC_ECIA_H_
 
 /*
  * Encode peripheral interrupt information into a 32-bit unsigned.
@@ -26,4 +26,4 @@
 #define MCHP_XEC_ECIA_NVIC_AGGR(e)	(((e) >> 16) & 0xff)
 #define MCHP_XEC_ECIA_NVIC_DIRECT(e)	(((e) >> 24) & 0xff)
 
-#endif /* __DT_BINDING_MCHP_XEC_ECIA_H */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_MCHP_XEC_ECIA_H_ */
diff --git a/include/zephyr/dt-bindings/interrupt-controller/ti-vim.h b/include/zephyr/dt-bindings/interrupt-controller/ti-vim.h
index 30485bd20e69..a142e80fc715 100644
--- a/include/zephyr/dt-bindings/interrupt-controller/ti-vim.h
+++ b/include/zephyr/dt-bindings/interrupt-controller/ti-vim.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef __DT_BINDING_TI_VIM_H
-#define __DT_BINDING_TI_VIM_H
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_TI_VIM_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_TI_VIM_H_
 
 #include <zephyr/sys/util_macro.h>
 
@@ -14,4 +14,4 @@
 
 #define IRQ_DEFAULT_PRIORITY  0xf
 
-#endif /* __DT_BINDING_TI_VIM_H */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_TI_VIM_H_ */
diff --git a/include/zephyr/dt-bindings/ipc_service/static_vrings.h b/include/zephyr/dt-bindings/ipc_service/static_vrings.h
index a01414bf9722..58e6089ae3df 100644
--- a/include/zephyr/dt-bindings/ipc_service/static_vrings.h
+++ b/include/zephyr/dt-bindings/ipc_service/static_vrings.h
@@ -3,12 +3,12 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#ifndef __DT_BINDING_IPC_SERVICE_STATIC_VRINGS_H
-#define __DT_BINDING_IPC_SERVICE_STATIC_VRINGS_H
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_IPC_SERVICE_STATIC_VRINGS_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_IPC_SERVICE_STATIC_VRINGS_H_
 
 #include <zephyr/dt-bindings/dt-util.h>
 
 #define	PRIO_COOP	BIT(0)
 #define	PRIO_PREEMPT	BIT(1)
 
-#endif /* __DT_BINDING_IPC_SERVICE_STATIC_VRINGS_H */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_IPC_SERVICE_STATIC_VRINGS_H_ */
diff --git a/include/zephyr/dt-bindings/led/seagate_legend_b1414.h b/include/zephyr/dt-bindings/led/seagate_legend_b1414.h
index e7f5b8a315dc..04e27dbc604c 100644
--- a/include/zephyr/dt-bindings/led/seagate_legend_b1414.h
+++ b/include/zephyr/dt-bindings/led/seagate_legend_b1414.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef ZEPHYR_SAMPLES_DRIVERS_LED_B1414_H_
-#define ZEPHYR_SAMPLES_DRIVERS_LED_B1414_H_
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_LED_SEAGATE_LEGEND_B1414_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_LED_SEAGATE_LEGEND_B1414_H_
 
 /*
  * At 6 MHz: 1 bit in 166.666 ns
@@ -17,4 +17,4 @@
 #define ZERO_FRAME	0x60
 #define ONE_FRAME	0x7C
 
-#endif
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_LED_SEAGATE_LEGEND_B1414_H_ */
diff --git a/include/zephyr/dt-bindings/led/worldsemi_ws2812c.h b/include/zephyr/dt-bindings/led/worldsemi_ws2812c.h
index e723227a0221..1815b054cdb2 100644
--- a/include/zephyr/dt-bindings/led/worldsemi_ws2812c.h
+++ b/include/zephyr/dt-bindings/led/worldsemi_ws2812c.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef ZEPHYR_DT_LED_WS2812C_H_
-#define ZEPHYR_DT_LED_WS2812C_H_
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_LED_WORLDSEMI_WS2812C_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_LED_WORLDSEMI_WS2812C_H_
 
 /*
  * At 7 MHz: 1 bit in 142.86 ns
@@ -17,4 +17,4 @@
 #define WS2812C_ZERO_FRAME (0xC0U)
 #define WS2812C_ONE_FRAME  (0xFCU)
 
-#endif
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_LED_WORLDSEMI_WS2812C_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/ambiq-apollo3-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/ambiq-apollo3-pinctrl.h
index fbbbd42ae4c6..6ce4564f181c 100644
--- a/include/zephyr/dt-bindings/pinctrl/ambiq-apollo3-pinctrl.h
+++ b/include/zephyr/dt-bindings/pinctrl/ambiq-apollo3-pinctrl.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef __APOLLO3_PINCTRL_H__
-#define __APOLLO3_PINCTRL_H__
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_AMBIQ_APOLLO3_PINCTRL_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_AMBIQ_APOLLO3_PINCTRL_H_
 
 #define APOLLO3_ALT_FUNC_POS  0
 #define APOLLO3_ALT_FUNC_MASK 0xf
@@ -491,4 +491,4 @@
 #define UA1CTS_P73       APOLLO3_PINMUX(73, 6)
 #define UA1RTS_P73       APOLLO3_PINMUX(73, 7)
 
-#endif /* __APOLLO3_PINCTRL_H__ */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_AMBIQ_APOLLO3_PINCTRL_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/ambiq-apollo4-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/ambiq-apollo4-pinctrl.h
index af207a9c218b..522b5155ab71 100644
--- a/include/zephyr/dt-bindings/pinctrl/ambiq-apollo4-pinctrl.h
+++ b/include/zephyr/dt-bindings/pinctrl/ambiq-apollo4-pinctrl.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef __APOLLO4_PINCTRL_H__
-#define __APOLLO4_PINCTRL_H__
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_AMBIQ_APOLLO4_PINCTRL_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_AMBIQ_APOLLO4_PINCTRL_H_
 
 #define APOLLO4_ALT_FUNC_POS 0
 #define APOLLO4_ALT_FUNC_MASK 0xf
@@ -1117,4 +1117,4 @@
 #define CT127_P127 APOLLO4_PINMUX(127, 6)
 #define OBSBUS15_P127 APOLLO4_PINMUX(127, 8)
 
-#endif /* __APOLLO4_PINCTRL_H__ */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_AMBIQ_APOLLO4_PINCTRL_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/b91-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/b91-pinctrl.h
index 941ca610d744..26206b98f453 100644
--- a/include/zephyr/dt-bindings/pinctrl/b91-pinctrl.h
+++ b/include/zephyr/dt-bindings/pinctrl/b91-pinctrl.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef ZEPHYR_B91_PINCTRL_COMMON_H_
-#define ZEPHYR_B91_PINCTRL_COMMON_H_
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_B91_PINCTRL_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_B91_PINCTRL_H_
 
 /* IDs for GPIO functions */
 
@@ -71,4 +71,4 @@
 #define B91_PINMUX_GET_PIN(pinmux)        ((pinmux >> B91_PIN_POS) & B91_PIN_MSK)
 #define B91_PINMUX_GET_PIN_ID(pinmux)     ((pinmux >> B91_PIN_POS) & B91_PIN_ID_MSK)
 
-#endif  /* ZEPHYR_B91_PINCTRL_COMMON_H_ */
+#endif  /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_B91_PINCTRL_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/cc13xx_cc26xx-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/cc13xx_cc26xx-pinctrl.h
index 042fb9df7a79..753ee905f8d2 100644
--- a/include/zephyr/dt-bindings/pinctrl/cc13xx_cc26xx-pinctrl.h
+++ b/include/zephyr/dt-bindings/pinctrl/cc13xx_cc26xx-pinctrl.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef CC13XX_CC26XX_PINCTRL_COMMON_H_
-#define CC13XX_CC26XX_PINCTRL_COMMON_H_
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_CC13XX_CC26XX_PINCTRL_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_CC13XX_CC26XX_PINCTRL_H_
 
 /* Adapted from hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ioc.h */
 
@@ -63,4 +63,4 @@
 #define IOC_RISING_EDGE  0x00020000 /* Edge detection on rising edge */
 #define IOC_BOTH_EDGES   0x00030000 /* Edge detection on both edges */
 
-#endif  /* CC13XX_CC26XX_PINCTRL_COMMON_H_ */
+#endif  /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_CC13XX_CC26XX_PINCTRL_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/ch32v003-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/ch32v003-pinctrl.h
index 0c606aed6e41..7353e26f23e9 100644
--- a/include/zephyr/dt-bindings/pinctrl/ch32v003-pinctrl.h
+++ b/include/zephyr/dt-bindings/pinctrl/ch32v003-pinctrl.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef __CH32V003_PINCTRL_H__
-#define __CH32V003_PINCTRL_H__
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_CH32V003_PINCTRL_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_CH32V003_PINCTRL_H_
 
 #define CH32V003_PINMUX_PORT_PA 0
 #define CH32V003_PINMUX_PORT_PC 1
@@ -134,4 +134,4 @@
 #define I2C1_SDA_PD0_1 CH32V003_PINMUX_DEFINE(PD, 0, I2C1, 1)
 #define I2C1_SDA_PC6_2 CH32V003_PINMUX_DEFINE(PC, 6, I2C1, 2)
 
-#endif /* __CH32V003_PINCTRL_H__ */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_CH32V003_PINCTRL_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/esp32-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/esp32-pinctrl.h
index 2728fbd06f4b..b16af53668c8 100644
--- a/include/zephyr/dt-bindings/pinctrl/esp32-pinctrl.h
+++ b/include/zephyr/dt-bindings/pinctrl/esp32-pinctrl.h
@@ -6,8 +6,8 @@
  * NOTE: Autogenerated file using esp_genpinctrl.py
  */
 
-#ifndef INC_DT_BINDS_PINCTRL_ESP32_PINCTRL_HAL_H_
-#define INC_DT_BINDS_PINCTRL_ESP32_PINCTRL_HAL_H_
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32_PINCTRL_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32_PINCTRL_H_
 
 /* DAC_CH1 */
 #define DAC_CH1_GPIO25 \
@@ -11518,4 +11518,4 @@
 	ESP32_PINMUX(33, ESP_NOSIG, ESP_U2TXD_OUT)
 
 
-#endif /* INC_DT_BINDS_PINCTRL_ESP32_PINCTRL_HAL_H_ */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32_PINCTRL_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/esp32c2-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/esp32c2-pinctrl.h
index 3b57a76c3e64..c995d08d39e1 100644
--- a/include/zephyr/dt-bindings/pinctrl/esp32c2-pinctrl.h
+++ b/include/zephyr/dt-bindings/pinctrl/esp32c2-pinctrl.h
@@ -6,8 +6,8 @@
  * NOTE: Autogenerated file using esp_genpinctrl.py
  */
 
-#ifndef INC_DT_BINDS_PINCTRL_ESP32C2_PINCTRL_HAL_H_
-#define INC_DT_BINDS_PINCTRL_ESP32C2_PINCTRL_HAL_H_
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32C2_PINCTRL_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32C2_PINCTRL_H_
 
 /* LEDC_CH0 */
 #define LEDC_CH0_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
@@ -793,4 +793,4 @@
 #define UART1_TX_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_U1TXD_OUT)
 
 
-#endif /* INC_DT_BINDS_PINCTRL_ESP32C2_PINCTRL_HAL_H_ */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32C2_PINCTRL_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/esp32c3-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/esp32c3-pinctrl.h
index 73a2a04c1914..4b44af9dcdef 100644
--- a/include/zephyr/dt-bindings/pinctrl/esp32c3-pinctrl.h
+++ b/include/zephyr/dt-bindings/pinctrl/esp32c3-pinctrl.h
@@ -6,8 +6,8 @@
  * NOTE: Autogenerated file using esp_genpinctrl.py
  */
 
-#ifndef INC_DT_BINDS_PINCTRL_ESP32C3_PINCTRL_HAL_H_
-#define INC_DT_BINDS_PINCTRL_ESP32C3_PINCTRL_HAL_H_
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32C3_PINCTRL_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32C3_PINCTRL_H_
 
 /* I2C0_SCL */
 #define I2C0_SCL_GPIO0 ESP32_PINMUX(0, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
@@ -1809,4 +1809,4 @@
 
 #define UART1_TX_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#endif /* INC_DT_BINDS_PINCTRL_ESP32C3_PINCTRL_HAL_H_ */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32C3_PINCTRL_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/esp32c6-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/esp32c6-pinctrl.h
index 7ae822da112a..0a3d10a64262 100644
--- a/include/zephyr/dt-bindings/pinctrl/esp32c6-pinctrl.h
+++ b/include/zephyr/dt-bindings/pinctrl/esp32c6-pinctrl.h
@@ -6,8 +6,8 @@
  * NOTE: Autogenerated file using esp_genpinctrl.py
  */
 
-#ifndef INC_DT_BINDS_PINCTRL_ESP32C6_PINCTRL_HAL_H_
-#define INC_DT_BINDS_PINCTRL_ESP32C6_PINCTRL_HAL_H_
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32C6_PINCTRL_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32C6_PINCTRL_H_
 
 /* I2C0_SCL */
 #define I2C0_SCL_GPIO0 \
@@ -2214,4 +2214,4 @@
 #define UART1_TX_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_U1TXD_OUT)
 
 
-#endif /* INC_DT_BINDS_PINCTRL_ESP32C6_PINCTRL_HAL_H_ */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32C6_PINCTRL_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/esp32s2-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/esp32s2-pinctrl.h
index 5d97a79b176f..5d841d72bf28 100644
--- a/include/zephyr/dt-bindings/pinctrl/esp32s2-pinctrl.h
+++ b/include/zephyr/dt-bindings/pinctrl/esp32s2-pinctrl.h
@@ -6,8 +6,8 @@
  * NOTE: Autogenerated file using esp_genpinctrl.py
  */
 
-#ifndef INC_DT_BINDS_PINCTRL_ESP32S2_PINCTRL_HAL_H_
-#define INC_DT_BINDS_PINCTRL_ESP32S2_PINCTRL_HAL_H_
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32S2_PINCTRL_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32S2_PINCTRL_H_
 
 /* I2C0_SCL */
 #define I2C0_SCL_GPIO0 \
@@ -7584,4 +7584,4 @@
 	ESP32_PINMUX(45, ESP_NOSIG, ESP_U1TXD_OUT)
 
 
-#endif /* INC_DT_BINDS_PINCTRL_ESP32S2_PINCTRL_HAL_H_ */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32S2_PINCTRL_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/esp32s3-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/esp32s3-pinctrl.h
index 0ea854985809..363f921aa7b8 100644
--- a/include/zephyr/dt-bindings/pinctrl/esp32s3-pinctrl.h
+++ b/include/zephyr/dt-bindings/pinctrl/esp32s3-pinctrl.h
@@ -6,8 +6,8 @@
  * NOTE: Autogenerated file using esp_genpinctrl.py
  */
 
-#ifndef INC_DT_BINDS_PINCTRL_ESP32S3_PINCTRL_HAL_H_
-#define INC_DT_BINDS_PINCTRL_ESP32S3_PINCTRL_HAL_H_
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32S3_PINCTRL_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32S3_PINCTRL_H_
 
 /* I2C0_SCL */
 #define I2C0_SCL_GPIO0 ESP32_PINMUX(0, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
@@ -15025,4 +15025,4 @@
 #define UART2_TX_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_U2TXD_OUT)
 
 
-#endif /* INC_DT_BINDS_PINCTRL_ESP32S3_PINCTRL_HAL_H_ */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_ESP32S3_PINCTRL_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/ifx_cat1-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/ifx_cat1-pinctrl.h
index a763e8ac9e2d..dcf743c164ee 100644
--- a/include/zephyr/dt-bindings/pinctrl/ifx_cat1-pinctrl.h
+++ b/include/zephyr/dt-bindings/pinctrl/ifx_cat1-pinctrl.h
@@ -3,7 +3,8 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IFX_CAT1_PINCTRL_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IFX_CAT1_PINCTRL_H_
 /**
  * @brief Pin control binding helper.
  */
@@ -105,3 +106,5 @@
 		DT_REG_ADDR_BY_IDX(DT_NODELABEL(gpio_prt0), 1),			   \
 		DT_PHA_BY_IDX(node, gpios_prop, 0, pin)				   \
 		)
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IFX_CAT1_PINCTRL_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/renesas-rzt2m-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/renesas-rzt2m-pinctrl.h
index ed1cbf7ee96b..c05d339acf6f 100644
--- a/include/zephyr/dt-bindings/pinctrl/renesas-rzt2m-pinctrl.h
+++ b/include/zephyr/dt-bindings/pinctrl/renesas-rzt2m-pinctrl.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef __RENESAS_RZT2M_PINCTRL_H__
-#define __RENESAS_RZT2M_PINCTRL_H__
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_RZT2M_PINCTRL_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_RZT2M_PINCTRL_H_
 
 #define RZT2M_PINMUX(port, pin, func) ((port << 16) | (pin << 8) | func)
 
@@ -15,4 +15,4 @@
 #define UART3TX_P18_0	RZT2M_PINMUX(18, 0, 4)
 #define UART3RX_P17_7	RZT2M_PINMUX(17, 7, 4)
 
-#endif /* __RENESAS_RZT2M_PINCTRL_H__ */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_RZT2M_PINCTRL_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h
index 5d88ea6eea8c..7ff1721798ce 100644
--- a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h
+++ b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef __ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_RA_PINCTRL_H__
-#define __ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_RA_PINCTRL_H__
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RA_H__
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RA_H__
 
 #define RA_PORT_NUM_POS  0
 #define RA_PORT_NUM_MASK 0xf
@@ -54,4 +54,4 @@
 	(1 << RA_MODE_POS | psel << RA_PSEL_POS | port_num << RA_PORT_NUM_POS |                    \
 	 pin_num << RA_PIN_NUM_POS)
 
-#endif /* __ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_RA_PINCTRL_H__ */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RA_H__ */
diff --git a/include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h
index 38d6e0420b42..1ea0209ad3ed 100644
--- a/include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h
+++ b/include/zephyr/dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h
@@ -7,16 +7,239 @@
 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RPI_PICO_RP2040_PINCTRL_H_
 #define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RPI_PICO_RP2040_PINCTRL_H_
 
-#define RP2_PINCTRL_GPIO_FUNC_XIP  0
+#define RP2_PINCTRL_GPIO_FUNC_XIP 0
+#define RP2_PINCTRL_GPIO_FUNC_SPI 1
+#define RP2_PINCTRL_GPIO_FUNC_UART 2
+#define RP2_PINCTRL_GPIO_FUNC_I2C 3
+#define RP2_PINCTRL_GPIO_FUNC_PWM 4
+#define RP2_PINCTRL_GPIO_FUNC_SIO 5
+#define RP2_PINCTRL_GPIO_FUNC_PIO0 6
+#define RP2_PINCTRL_GPIO_FUNC_PIO1 7
 #define RP2_PINCTRL_GPIO_FUNC_GPCK 8
 #define RP2_PINCTRL_GPIO_FUNC_USB  9
 #define RP2_PINCTRL_GPIO_FUNC_NULL 0xf
 
-#include "rpi-pico-pinctrl-common.h"
+#define RP2_ALT_FUNC_POS 0
+#define RP2_ALT_FUNC_MASK 0xf
 
-#define ADC_CH0_P26 RP2XXX_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_NULL)
-#define ADC_CH1_P27 RP2XXX_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_NULL)
-#define ADC_CH2_P28 RP2XXX_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_NULL)
-#define ADC_CH3_P29 RP2XXX_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_NULL)
+#define RP2_PIN_NUM_POS 4
+#define RP2_PIN_NUM_MASK 0x1f
+
+#define RP2_GPIO_OVERRIDE_NORMAL 0
+#define RP2_GPIO_OVERRIDE_INVERT 1
+#define RP2_GPIO_OVERRIDE_LOW 2
+#define RP2_GPIO_OVERRIDE_HIGH 3
+
+#define RP2040_PINMUX(pin_num, alt_func) (pin_num << RP2_PIN_NUM_POS |	\
+					alt_func << RP2_ALT_FUNC_POS)
+
+#define UART0_TX_P0 RP2040_PINMUX(0, RP2_PINCTRL_GPIO_FUNC_UART)
+#define UART0_RX_P1 RP2040_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_UART)
+#define UART0_CTS_P2 RP2040_PINMUX(2, RP2_PINCTRL_GPIO_FUNC_UART)
+#define UART0_RTS_P3 RP2040_PINMUX(3, RP2_PINCTRL_GPIO_FUNC_UART)
+#define UART1_TX_P4 RP2040_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_UART)
+#define UART1_RX_P5 RP2040_PINMUX(5, RP2_PINCTRL_GPIO_FUNC_UART)
+#define UART1_CTS_P6 RP2040_PINMUX(6, RP2_PINCTRL_GPIO_FUNC_UART)
+#define UART1_RTS_P7 RP2040_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_UART)
+#define UART1_TX_P8 RP2040_PINMUX(8, RP2_PINCTRL_GPIO_FUNC_UART)
+#define UART1_RX_P9 RP2040_PINMUX(9, RP2_PINCTRL_GPIO_FUNC_UART)
+#define UART1_CTS_P10 RP2040_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_UART)
+#define UART1_RTS_P11 RP2040_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_UART)
+#define UART0_TX_P12 RP2040_PINMUX(12, RP2_PINCTRL_GPIO_FUNC_UART)
+#define UART0_RX_P13 RP2040_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_UART)
+#define UART0_CTS_P14 RP2040_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_UART)
+#define UART0_RTS_P15 RP2040_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_UART)
+#define UART0_TX_P16 RP2040_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_UART)
+#define UART0_RX_P17 RP2040_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_UART)
+#define UART0_CTS_P18 RP2040_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_UART)
+#define UART0_RTS_P19 RP2040_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_UART)
+#define UART1_TX_P20 RP2040_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_UART)
+#define UART1_RX_P21 RP2040_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_UART)
+#define UART1_CTS_P22 RP2040_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_UART)
+#define UART1_RTS_P23 RP2040_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_UART)
+#define UART1_TX_P24 RP2040_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_UART)
+#define UART1_RX_P25 RP2040_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_UART)
+#define UART1_CTS_P26 RP2040_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_UART)
+#define UART1_RTS_P27 RP2040_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_UART)
+#define UART0_TX_P28 RP2040_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_UART)
+#define UART0_RX_P29 RP2040_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_UART)
+
+#define I2C0_SDA_P0 RP2040_PINMUX(0, RP2_PINCTRL_GPIO_FUNC_I2C)
+#define I2C0_SCL_P1 RP2040_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_I2C)
+#define I2C1_SDA_P2 RP2040_PINMUX(2, RP2_PINCTRL_GPIO_FUNC_I2C)
+#define I2C1_SCL_P3 RP2040_PINMUX(3, RP2_PINCTRL_GPIO_FUNC_I2C)
+#define I2C0_SDA_P4 RP2040_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_I2C)
+#define I2C0_SCL_P5 RP2040_PINMUX(5, RP2_PINCTRL_GPIO_FUNC_I2C)
+#define I2C1_SDA_P6 RP2040_PINMUX(6, RP2_PINCTRL_GPIO_FUNC_I2C)
+#define I2C1_SCL_P7 RP2040_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_I2C)
+#define I2C0_SDA_P8 RP2040_PINMUX(8, RP2_PINCTRL_GPIO_FUNC_I2C)
+#define I2C0_SCL_P9 RP2040_PINMUX(9, RP2_PINCTRL_GPIO_FUNC_I2C)
+#define I2C1_SDA_P10 RP2040_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_I2C)
+#define I2C1_SCL_P11 RP2040_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_I2C)
+#define I2C0_SDA_P12 RP2040_PINMUX(12, RP2_PINCTRL_GPIO_FUNC_I2C)
+#define I2C0_SCL_P13 RP2040_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_I2C)
+#define I2C1_SDA_P14 RP2040_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_I2C)
+#define I2C1_SCL_P15 RP2040_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_I2C)
+#define I2C0_SDA_P16 RP2040_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_I2C)
+#define I2C0_SCL_P17 RP2040_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_I2C)
+#define I2C1_SDA_P18 RP2040_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_I2C)
+#define I2C1_SCL_P19 RP2040_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_I2C)
+#define I2C0_SDA_P20 RP2040_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_I2C)
+#define I2C0_SCL_P21 RP2040_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_I2C)
+#define I2C1_SDA_P22 RP2040_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_I2C)
+#define I2C1_SCL_P23 RP2040_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_I2C)
+#define I2C0_SDA_P24 RP2040_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_I2C)
+#define I2C0_SCL_P25 RP2040_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_I2C)
+#define I2C1_SDA_P26 RP2040_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_I2C)
+#define I2C1_SCL_P27 RP2040_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_I2C)
+#define I2C0_SDA_P28 RP2040_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_I2C)
+#define I2C0_SCL_P29 RP2040_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_I2C)
+
+#define PWM_0A_P0 RP2040_PINMUX(0, RP2_PINCTRL_GPIO_FUNC_PWM)
+#define PWM_0B_P1 RP2040_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_PWM)
+#define PWM_1A_P2 RP2040_PINMUX(2, RP2_PINCTRL_GPIO_FUNC_PWM)
+#define PWM_1B_P3 RP2040_PINMUX(3, RP2_PINCTRL_GPIO_FUNC_PWM)
+#define PWM_2A_P4 RP2040_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_PWM)
+#define PWM_2B_P5 RP2040_PINMUX(5, RP2_PINCTRL_GPIO_FUNC_PWM)
+#define PWM_3A_P6 RP2040_PINMUX(6, RP2_PINCTRL_GPIO_FUNC_PWM)
+#define PWM_3B_P7 RP2040_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_PWM)
+#define PWM_4A_P8 RP2040_PINMUX(8, RP2_PINCTRL_GPIO_FUNC_PWM)
+#define PWM_4B_P9 RP2040_PINMUX(9, RP2_PINCTRL_GPIO_FUNC_PWM)
+#define PWM_5A_P10 RP2040_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_PWM)
+#define PWM_5B_P11 RP2040_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_PWM)
+#define PWM_6A_P12 RP2040_PINMUX(12, RP2_PINCTRL_GPIO_FUNC_PWM)
+#define PWM_6B_P13 RP2040_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_PWM)
+#define PWM_7A_P14 RP2040_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_PWM)
+#define PWM_7B_P15 RP2040_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_PWM)
+#define PWM_0A_P16 RP2040_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_PWM)
+#define PWM_0B_P17 RP2040_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_PWM)
+#define PWM_1A_P18 RP2040_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_PWM)
+#define PWM_1B_P19 RP2040_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_PWM)
+#define PWM_2A_P20 RP2040_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_PWM)
+#define PWM_2B_P21 RP2040_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_PWM)
+#define PWM_3A_P22 RP2040_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_PWM)
+#define PWM_3B_P22 RP2040_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_PWM)
+#define PWM_4A_P24 RP2040_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_PWM)
+#define PWM_4B_P25 RP2040_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_PWM)
+#define PWM_5A_P26 RP2040_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_PWM)
+#define PWM_5B_P27 RP2040_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_PWM)
+#define PWM_6A_P28 RP2040_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_PWM)
+#define PWM_6B_P29 RP2040_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_PWM)
+
+#define SPI0_RX_P0 RP2040_PINMUX(0, RP2_PINCTRL_GPIO_FUNC_SPI)
+#define SPI0_CSN_P1 RP2040_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_SPI)
+#define SPI0_SCK_P2 RP2040_PINMUX(2, RP2_PINCTRL_GPIO_FUNC_SPI)
+#define SPI0_TX_P3 RP2040_PINMUX(3, RP2_PINCTRL_GPIO_FUNC_SPI)
+#define SPI0_RX_P4 RP2040_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_SPI)
+#define SPI0_CSN_P5 RP2040_PINMUX(5, RP2_PINCTRL_GPIO_FUNC_SPI)
+#define SPI0_SCK_P6 RP2040_PINMUX(6, RP2_PINCTRL_GPIO_FUNC_SPI)
+#define SPI0_TX_P7 RP2040_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_SPI)
+#define SPI1_RX_P8 RP2040_PINMUX(8, RP2_PINCTRL_GPIO_FUNC_SPI)
+#define SPI1_CSN_P9 RP2040_PINMUX(9, RP2_PINCTRL_GPIO_FUNC_SPI)
+#define SPI1_SCK_P10 RP2040_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_SPI)
+#define SPI1_TX_P11 RP2040_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_SPI)
+#define SPI1_RX_P12 RP2040_PINMUX(12, RP2_PINCTRL_GPIO_FUNC_SPI)
+#define SPI1_CSN_P13 RP2040_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_SPI)
+#define SPI1_SCK_P14 RP2040_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_SPI)
+#define SPI1_TX_P15 RP2040_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_SPI)
+#define SPI0_RX_P16 RP2040_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_SPI)
+#define SPI0_CSN_P17 RP2040_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_SPI)
+#define SPI0_SCK_P18 RP2040_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_SPI)
+#define SPI0_TX_P19 RP2040_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_SPI)
+#define SPI0_RX_P20 RP2040_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_SPI)
+#define SPI0_CSN_P21 RP2040_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_SPI)
+#define SPI0_SCK_P22 RP2040_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_SPI)
+#define SPI0_TX_P23 RP2040_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_SPI)
+#define SPI1_RX_P24 RP2040_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_SPI)
+#define SPI1_CSN_P25 RP2040_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_SPI)
+#define SPI1_SCK_P26 RP2040_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_SPI)
+#define SPI1_TX_P27 RP2040_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_SPI)
+#define SPI1_RX_P28 RP2040_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_SPI)
+#define SPI1_CSN_P29 RP2040_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_SPI)
+
+#define ADC_CH0_P26 RP2040_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_NULL)
+#define ADC_CH1_P27 RP2040_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_NULL)
+#define ADC_CH2_P28 RP2040_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_NULL)
+#define ADC_CH3_P29 RP2040_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_NULL)
+
+#define PIO0_P0 RP2040_PINMUX(0, RP2_PINCTRL_GPIO_FUNC_PIO0)
+#define PIO0_P1 RP2040_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_PIO0)
+#define PIO0_P2 RP2040_PINMUX(2, RP2_PINCTRL_GPIO_FUNC_PIO0)
+#define PIO0_P3 RP2040_PINMUX(3, RP2_PINCTRL_GPIO_FUNC_PIO0)
+#define PIO0_P4 RP2040_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_PIO0)
+#define PIO0_P5 RP2040_PINMUX(5, RP2_PINCTRL_GPIO_FUNC_PIO0)
+#define PIO0_P6 RP2040_PINMUX(6, RP2_PINCTRL_GPIO_FUNC_PIO0)
+#define PIO0_P7 RP2040_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_PIO0)
+#define PIO0_P8 RP2040_PINMUX(8, RP2_PINCTRL_GPIO_FUNC_PIO0)
+#define PIO0_P9 RP2040_PINMUX(9, RP2_PINCTRL_GPIO_FUNC_PIO0)
+#define PIO0_P10 RP2040_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_PIO0)
+#define PIO0_P11 RP2040_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_PIO0)
+#define PIO0_P12 RP2040_PINMUX(12, RP2_PINCTRL_GPIO_FUNC_PIO0)
+#define PIO0_P13 RP2040_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_PIO0)
+#define PIO0_P14 RP2040_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_PIO0)
+#define PIO0_P15 RP2040_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_PIO0)
+#define PIO0_P16 RP2040_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_PIO0)
+#define PIO0_P17 RP2040_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_PIO0)
+#define PIO0_P18 RP2040_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_PIO0)
+#define PIO0_P19 RP2040_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_PIO0)
+#define PIO0_P20 RP2040_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_PIO0)
+#define PIO0_P21 RP2040_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_PIO0)
+#define PIO0_P22 RP2040_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_PIO0)
+#define PIO0_P23 RP2040_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_PIO0)
+#define PIO0_P24 RP2040_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_PIO0)
+#define PIO0_P25 RP2040_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_PIO0)
+#define PIO0_P26 RP2040_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_PIO0)
+#define PIO0_P27 RP2040_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_PIO0)
+#define PIO0_P28 RP2040_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_PIO0)
+#define PIO0_P29 RP2040_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_PIO0)
+
+#define PIO1_P0 RP2040_PINMUX(0, RP2_PINCTRL_GPIO_FUNC_PIO1)
+#define PIO1_P1 RP2040_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_PIO1)
+#define PIO1_P2 RP2040_PINMUX(2, RP2_PINCTRL_GPIO_FUNC_PIO1)
+#define PIO1_P3 RP2040_PINMUX(3, RP2_PINCTRL_GPIO_FUNC_PIO1)
+#define PIO1_P4 RP2040_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_PIO1)
+#define PIO1_P5 RP2040_PINMUX(5, RP2_PINCTRL_GPIO_FUNC_PIO1)
+#define PIO1_P6 RP2040_PINMUX(6, RP2_PINCTRL_GPIO_FUNC_PIO1)
+#define PIO1_P7 RP2040_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_PIO1)
+#define PIO1_P8 RP2040_PINMUX(8, RP2_PINCTRL_GPIO_FUNC_PIO1)
+#define PIO1_P9 RP2040_PINMUX(9, RP2_PINCTRL_GPIO_FUNC_PIO1)
+#define PIO1_P10 RP2040_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_PIO1)
+#define PIO1_P11 RP2040_PINMUX(11, RP2_PINCTRL_GPIO_FUNC_PIO1)
+#define PIO1_P12 RP2040_PINMUX(12, RP2_PINCTRL_GPIO_FUNC_PIO1)
+#define PIO1_P13 RP2040_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_PIO1)
+#define PIO1_P14 RP2040_PINMUX(14, RP2_PINCTRL_GPIO_FUNC_PIO1)
+#define PIO1_P15 RP2040_PINMUX(15, RP2_PINCTRL_GPIO_FUNC_PIO1)
+#define PIO1_P16 RP2040_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_PIO1)
+#define PIO1_P17 RP2040_PINMUX(17, RP2_PINCTRL_GPIO_FUNC_PIO1)
+#define PIO1_P18 RP2040_PINMUX(18, RP2_PINCTRL_GPIO_FUNC_PIO1)
+#define PIO1_P19 RP2040_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_PIO1)
+#define PIO1_P20 RP2040_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_PIO1)
+#define PIO1_P21 RP2040_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_PIO1)
+#define PIO1_P22 RP2040_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_PIO1)
+#define PIO1_P23 RP2040_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_PIO1)
+#define PIO1_P24 RP2040_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_PIO1)
+#define PIO1_P25 RP2040_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_PIO1)
+#define PIO1_P26 RP2040_PINMUX(26, RP2_PINCTRL_GPIO_FUNC_PIO1)
+#define PIO1_P27 RP2040_PINMUX(27, RP2_PINCTRL_GPIO_FUNC_PIO1)
+#define PIO1_P28 RP2040_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_PIO1)
+#define PIO1_P29 RP2040_PINMUX(29, RP2_PINCTRL_GPIO_FUNC_PIO1)
+
+#define GPIN0_P20 RP2040_PINMUX(20, RP2_PINCTRL_GPIO_FUNC_GPCK)
+#define GPIN1_P22 RP2040_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_GPCK)
+#define GPOUT0_P21 RP2040_PINMUX(21, RP2_PINCTRL_GPIO_FUNC_GPCK)
+#define GPOUT1_P23 RP2040_PINMUX(23, RP2_PINCTRL_GPIO_FUNC_GPCK)
+#define GPOUT2_P24 RP2040_PINMUX(24, RP2_PINCTRL_GPIO_FUNC_GPCK)
+#define GPOUT3_P25 RP2040_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_GPCK)
+
+#define USB_VBUS_DET_P1  RP2040_PINMUX(1, RP2_PINCTRL_GPIO_FUNC_USB)
+#define USB_VBUS_DET_P4  RP2040_PINMUX(4, RP2_PINCTRL_GPIO_FUNC_USB)
+#define USB_VBUS_DET_P7  RP2040_PINMUX(7, RP2_PINCTRL_GPIO_FUNC_USB)
+#define USB_VBUS_DET_P10 RP2040_PINMUX(10, RP2_PINCTRL_GPIO_FUNC_USB)
+#define USB_VBUS_DET_P13 RP2040_PINMUX(13, RP2_PINCTRL_GPIO_FUNC_USB)
+#define USB_VBUS_DET_P16 RP2040_PINMUX(16, RP2_PINCTRL_GPIO_FUNC_USB)
+#define USB_VBUS_DET_P19 RP2040_PINMUX(19, RP2_PINCTRL_GPIO_FUNC_USB)
+#define USB_VBUS_DET_P22 RP2040_PINMUX(22, RP2_PINCTRL_GPIO_FUNC_USB)
+#define USB_VBUS_DET_P25 RP2040_PINMUX(25, RP2_PINCTRL_GPIO_FUNC_USB)
+#define USB_VBUS_DET_P28 RP2040_PINMUX(28, RP2_PINCTRL_GPIO_FUNC_USB)
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RPI_PICO_RP2040_PINCTRL_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/rv32m1-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/rv32m1-pinctrl.h
index 62bf6438e504..9686623d9088 100644
--- a/include/zephyr/dt-bindings/pinctrl/rv32m1-pinctrl.h
+++ b/include/zephyr/dt-bindings/pinctrl/rv32m1-pinctrl.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef _ZEPHYR_DT_BINDINGS_PINCTRL_RV32M1_PINCTRL_
-#define _ZEPHYR_DT_BINDINGS_PINCTRL_RV32M1_PINCTRL_
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RV32M1_PINCTRL_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RV32M1_PINCTRL_H_
 
 /**
  * @brief Specify PORTx->PCR register MUX field
@@ -19,4 +19,4 @@
 	(((pin) & 0x3F) << 22) |                \
 	(((mux) & 0x7) << 8))
 
-#endif /* _ZEPHYR_DT_BINDINGS_PINCTRL_RV32M1_PINCTRL_ */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RV32M1_PINCTRL_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/stm32-pinctrl-common.h b/include/zephyr/dt-bindings/pinctrl/stm32-pinctrl-common.h
index 0c5933c580e5..31044cb6d77a 100644
--- a/include/zephyr/dt-bindings/pinctrl/stm32-pinctrl-common.h
+++ b/include/zephyr/dt-bindings/pinctrl/stm32-pinctrl-common.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef ZEPHYR_STM32_PINCTRL_COMMON_H_
-#define ZEPHYR_STM32_PINCTRL_COMMON_H_
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_STM32_PINCTRL_COMMON_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_STM32_PINCTRL_COMMON_H_
 
 /**
  * @brief numerical IDs for IO ports
@@ -37,4 +37,4 @@
 #define STM32PIN(_port, _pin) \
 	(_port << 4 | _pin)
 
-#endif	/* ZEPHYR_STM32_PINCTRL_COMMON_H_ */
+#endif	/* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_STM32_PINCTRL_COMMON_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/stm32f1-afio.h b/include/zephyr/dt-bindings/pinctrl/stm32f1-afio.h
index eee466921344..b2832a0b34cb 100644
--- a/include/zephyr/dt-bindings/pinctrl/stm32f1-afio.h
+++ b/include/zephyr/dt-bindings/pinctrl/stm32f1-afio.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef ZEPHYR_STM32_AFIO_H_
-#define ZEPHYR_STM32_AFIO_H_
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_STM32F1_AFIO_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_STM32F1_AFIO_H_
 
 #define STM32_REMAP_REG_MASK    0x1U
 #define STM32_REMAP_REG_SHIFT   0U
@@ -208,4 +208,4 @@
 /** TIM17 (remap) */
 #define TIM17_REMAP1		STM32_REMAP(1U, 0x1U, 2U, STM32_AFIO_MAPR2)
 
-#endif	/* ZEPHYR_STM32_AFIO_H_ */
+#endif	/* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_STM32F1_AFIO_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/stm32f1-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/stm32f1-pinctrl.h
index ae16673eb57d..ed6668b92f34 100644
--- a/include/zephyr/dt-bindings/pinctrl/stm32f1-pinctrl.h
+++ b/include/zephyr/dt-bindings/pinctrl/stm32f1-pinctrl.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef ZEPHYR_STM32_PINCTRLF1_H_
-#define ZEPHYR_STM32_PINCTRLF1_H_
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_STM32F1_PINCTRL_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_STM32F1_PINCTRL_H_
 
 #include <zephyr/dt-bindings/pinctrl/stm32-pinctrl-common.h>
 #include <zephyr/dt-bindings/pinctrl/stm32f1-afio.h>
@@ -115,4 +115,4 @@
 #define STM32_ODR_MASK			0x1
 #define STM32_ODR_SHIFT			9
 
-#endif	/* ZEPHYR_STM32_PINCTRLF1_H_ */
+#endif	/* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_STM32F1_PINCTRL_H_ */
diff --git a/include/zephyr/dt-bindings/pwm/it8xxx2_pwm.h b/include/zephyr/dt-bindings/pwm/it8xxx2_pwm.h
index 19fd7a14d303..8aea1453fc29 100644
--- a/include/zephyr/dt-bindings/pwm/it8xxx2_pwm.h
+++ b/include/zephyr/dt-bindings/pwm/it8xxx2_pwm.h
@@ -3,8 +3,8 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PWM_IT8XXX2_H_
-#define ZEPHYR_INCLUDE_DT_BINDINGS_PWM_IT8XXX2_H_
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PWM_IT8XXX2_PWM_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PWM_IT8XXX2_PWM_H_
 
 #include <zephyr/dt-bindings/dt-util.h>
 
@@ -31,4 +31,4 @@
  */
 #define PWM_IT8XXX2_OPEN_DRAIN	BIT(8)
 
-#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PWM_IT8XXX2_H_ */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PWM_IT8XXX2_PWM_H_ */
diff --git a/include/zephyr/dt-bindings/pwm/pwm_ifx_cat1.h b/include/zephyr/dt-bindings/pwm/pwm_ifx_cat1.h
index 82256c709c1b..75216175d653 100644
--- a/include/zephyr/dt-bindings/pwm/pwm_ifx_cat1.h
+++ b/include/zephyr/dt-bindings/pwm/pwm_ifx_cat1.h
@@ -3,9 +3,12 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PWM_PWM_IFX_CAT1_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PWM_PWM_IFX_CAT1_H_
 /**
  * Divider Type
  */
 #define CY_SYSCLK_DIV_8_BIT  0
 #define CY_SYSCLK_DIV_16_BIT 1
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PWM_PWM_IFX_CAT1_H_ */
diff --git a/include/zephyr/dt-bindings/pwm/stm32_pwm.h b/include/zephyr/dt-bindings/pwm/stm32_pwm.h
index 34180afc92af..12f937885316 100644
--- a/include/zephyr/dt-bindings/pwm/stm32_pwm.h
+++ b/include/zephyr/dt-bindings/pwm/stm32_pwm.h
@@ -3,8 +3,8 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_STM32_PWM_H_
-#define ZEPHYR_INCLUDE_DT_BINDINGS_STM32_PWM_H_
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PWM_STM32_PWM_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PWM_STM32_PWM_H_
 
 /**
  * @name custom PWM complementary flags for output pins
@@ -27,4 +27,4 @@
 /** @endcond */
 /** @} */
 
-#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PWM_STM32_H_ */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PWM_STM32_PWM_H_ */