From 0ade6f0c55ee27a51489f0754b4f0444de623047 Mon Sep 17 00:00:00 2001
From: Xiaochen Shen <xiaochen.shen@intel.com>
Date: Tue, 9 Aug 2016 15:26:17 +0800
Subject: [PATCH] config-linux: add support for Intel RDT/CAT in runtime-spec

Add support for Intel Resource Director Technology (RDT) / Cache Allocation
Technology (CAT). Add L3 cache resource constraints in Linux-specific
configuration.

This is the prerequisite of this runc proposal:
https://github.com/opencontainers/runc/issues/433

For more information about Intel RDT/CAT, please refer to:
https://github.com/opencontainers/runc/issues/433

Signed-off-by: Xiaochen Shen <xiaochen.shen@intel.com>
---
 config-linux.md    | 27 +++++++++++++++++++++++++++
 specs-go/config.go | 11 +++++++++++
 2 files changed, 38 insertions(+)

diff --git a/config-linux.md b/config-linux.md
index 22a58b2e2..75372e167 100644
--- a/config-linux.md
+++ b/config-linux.md
@@ -464,6 +464,30 @@ The following parameters can be specified to setup the controller:
    }
 ```
 
+## Intel RDT
+
+`intelRdt` represents the L3 cache resource constraints in Intel Xeon platforms.
+It is part of `resources` field of the Linux configuration.
+
+Intel Cache Allocation Technology (CAT) is a sub-feature of Resource Director Technology (RDT).
+Currently L3 Cache is the only resource that is supported in Intel RDT.
+
+For more information, see section 17.17 of [Intel Software Developer Manual] [intel-sdm] and [Intel RDT/CAT] [intel-rdt-cat].
+
+The following parameters can be specified for the container:
+
+* **`l3CacheSchema`** *(string, optional)* - specifies the schema for L3 cache id and capacity bitmask (CBM)
+* **`l3CacheCpus`** *(string, optional)* - specifies the bitmask of the CPUs that are bound to the schema
+
+###### Example
+
+```json
+   "intelRdt": {
+        "l3CacheSchema": "L3:0=ffff0;1=fffff",
+        "L3CacheCpus": "00000000,00000000,00000000,00000000,00000000,00000000"
+   }
+```
+
 ## Sysctl
 
 `sysctl` allows kernel parameters to be modified at runtime for the container.
@@ -605,3 +629,6 @@ Its value is either slave, private, or shared.
 [random.4]: http://man7.org/linux/man-pages/man4/random.4.html
 [tty.4]: http://man7.org/linux/man-pages/man4/tty.4.html
 [zero.4]: http://man7.org/linux/man-pages/man4/zero.4.html
+
+[intel-sdm]: http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf
+[intel-rdt-cat]: https://software.intel.com/en-us/articles/introduction-to-cache-allocation-technology
diff --git a/specs-go/config.go b/specs-go/config.go
index 4a1612264..5c8af1fc4 100644
--- a/specs-go/config.go
+++ b/specs-go/config.go
@@ -299,6 +299,15 @@ type Network struct {
 	Priorities []InterfacePriority `json:"priorities,omitempty"`
 }
 
+// Intel RDT: Intel Xeon platforms shared resource control
+type IntelRdt struct {
+	// The schema for L3 cache id and capacity bitmask (CBM)
+	// Format: "L3:<cache_id0>=<cbm0>;<cache_id1>=<cbm1>;..."
+	L3CacheSchema *string `json:"l3CacheSchema,omitempty"`
+	// The bitmask of the CPUs that are bound to the schema
+	L3CacheCpus *string `json:"l3CacheCpus,omitempty"`
+}
+
 // Resources has container runtime resource constraints
 type Resources struct {
 	// Devices configures the device whitelist.
@@ -319,6 +328,8 @@ type Resources struct {
 	HugepageLimits []HugepageLimit `json:"hugepageLimits,omitempty"`
 	// Network restriction configuration
 	Network *Network `json:"network,omitempty"`
+	// IntelRdt restriction configuration
+	IntelRdt *IntelRdt `json:"intelRdt,omitempty"`
 }
 
 // Device represents the mknod information for a Linux special device file