Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

SDRAM read/write example #23

Open
quantrpeter opened this issue Oct 29, 2023 · 1 comment
Open

SDRAM read/write example #23

quantrpeter opened this issue Oct 29, 2023 · 1 comment

Comments

@quantrpeter
Copy link

hi, is there any SDRAM read/write example? thanks

@caffiend13
Copy link

caffiend13 commented Sep 5, 2024

I used the SDR SDRAM Advanced Controller from the Lattice site, then modified it with the correct timing parameters and changed it from doing 4 burst read/writes of 4 bits each to one burst of 16 bits. Then I wrote my own module to trigger the r/w enable. Of any example SDR SDRAM controller I've tried, this was the only one I got to work.

You will need to fuss with it, but it will work (and you will be forced to read and re-read the SDRAM data sheet, which isn't a bad thing).

The one thing that I did not understand before was the initialization procedure. Most controller examples use SDRAMs that only need two refresh cycles during initialization. The one on the iCESugar-Pro needs at least 8. So you will need to modify the Lattice design to do that.

https://www.latticesemi.com/products/designsoftwareandip/intellectualproperty/referencedesigns/referencedesign04/sdr-sdram-controller-advanced

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

No branches or pull requests

2 participants