You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
I used the SDR SDRAM Advanced Controller from the Lattice site, then modified it with the correct timing parameters and changed it from doing 4 burst read/writes of 4 bits each to one burst of 16 bits. Then I wrote my own module to trigger the r/w enable. Of any example SDR SDRAM controller I've tried, this was the only one I got to work.
You will need to fuss with it, but it will work (and you will be forced to read and re-read the SDRAM data sheet, which isn't a bad thing).
The one thing that I did not understand before was the initialization procedure. Most controller examples use SDRAMs that only need two refresh cycles during initialization. The one on the iCESugar-Pro needs at least 8. So you will need to modify the Lattice design to do that.
hi, is there any SDRAM read/write example? thanks
The text was updated successfully, but these errors were encountered: