From 909e6ed69317ceef97f3172ad63b10b85ebbf486 Mon Sep 17 00:00:00 2001 From: Chris Ranc Date: Wed, 21 Mar 2018 14:57:56 -0400 Subject: [PATCH 1/3] added support to specify SPI blk to use available spi hardware as opposed to purely software SPI --- mfrc522.py | 380 +++++++++++++++++++++++++++-------------------------- 1 file changed, 193 insertions(+), 187 deletions(-) diff --git a/mfrc522.py b/mfrc522.py index 1833d75..73bd786 100644 --- a/mfrc522.py +++ b/mfrc522.py @@ -4,226 +4,232 @@ class MFRC522: - OK = 0 - NOTAGERR = 1 - ERR = 2 - - REQIDL = 0x26 - REQALL = 0x52 - AUTHENT1A = 0x60 - AUTHENT1B = 0x61 - - def __init__(self, sck, mosi, miso, rst, cs): - - self.sck = Pin(sck, Pin.OUT) - self.mosi = Pin(mosi, Pin.OUT) - self.miso = Pin(miso) - self.rst = Pin(rst, Pin.OUT) - self.cs = Pin(cs, Pin.OUT) - - self.rst.value(0) - self.cs.value(1) - - board = uname()[0] - - if board == 'WiPy' or board == 'LoPy' or board == 'FiPy': - self.spi = SPI(0) - self.spi.init(SPI.MASTER, baudrate=1000000, pins=(self.sck, self.mosi, self.miso)) - elif board == 'esp8266': - self.spi = SPI(baudrate=100000, polarity=0, phase=0, sck=self.sck, mosi=self.mosi, miso=self.miso) - self.spi.init() - else: - raise RuntimeError("Unsupported platform") - - self.rst.value(1) - self.init() - - def _wreg(self, reg, val): - - self.cs.value(0) - self.spi.write(b'%c' % int(0xff & ((reg << 1) & 0x7e))) - self.spi.write(b'%c' % int(0xff & val)) - self.cs.value(1) - - def _rreg(self, reg): - - self.cs.value(0) - self.spi.write(b'%c' % int(0xff & (((reg << 1) & 0x7e) | 0x80))) - val = self.spi.read(1) - self.cs.value(1) - - return val[0] - - def _sflags(self, reg, mask): - self._wreg(reg, self._rreg(reg) | mask) - - def _cflags(self, reg, mask): - self._wreg(reg, self._rreg(reg) & (~mask)) - - def _tocard(self, cmd, send): + OK = 0 + NOTAGERR = 1 + ERR = 2 + + REQIDL = 0x26 + REQALL = 0x52 + AUTHENT1A = 0x60 + AUTHENT1B = 0x61 + + def __init__(self, rst, cs, spiblk=None, sck=None, mosi=None, miso=None): + if spiblk == None and (sck != mosi != miso): + self.sck = Pin(sck, Pin.OUT) + self.mosi = Pin(mosi, Pin.OUT) + self.miso = Pin(miso) + self.rst = Pin(rst, Pin.OUT) + self.cs = Pin(cs, Pin.OUT) + + self.rst.value(0) + self.cs.value(1) + + board = uname()[0] + + if board == 'WiPy' or board == 'LoPy' or board == 'FiPy': + if spiblk == None: + self.spi = SPI(0) + else: + self.spi = SPI(spiblk) + self.spi.init(SPI.MASTER, baudrate=1000000, pins=(self.sck, self.mosi, self.miso)) + elif board == 'esp8266': + if spiblk == None: + self.spi = SPI(baudrate=100000, polarity=0, phase=0, sck=self.sck, mosi=self.mosi, miso=self.miso) + else: + self.spi = SPI(spiblk, baudrate=100000, polarity=0, phase=0) + self.spi.init() + else: + raise RuntimeError("Unsupported platform") + + self.rst.value(1) + self.init() + + def _wreg(self, reg, val): + + self.cs.value(0) + self.spi.write(b'%c' % int(0xff & ((reg << 1) & 0x7e))) + self.spi.write(b'%c' % int(0xff & val)) + self.cs.value(1) + + def _rreg(self, reg): + + self.cs.value(0) + self.spi.write(b'%c' % int(0xff & (((reg << 1) & 0x7e) | 0x80))) + val = self.spi.read(1) + self.cs.value(1) + + return val[0] + + def _sflags(self, reg, mask): + self._wreg(reg, self._rreg(reg) | mask) + + def _cflags(self, reg, mask): + self._wreg(reg, self._rreg(reg) & (~mask)) + + def _tocard(self, cmd, send): + + recv = [] + bits = irq_en = wait_irq = n = 0 + stat = self.ERR + + if cmd == 0x0E: + irq_en = 0x12 + wait_irq = 0x10 + elif cmd == 0x0C: + irq_en = 0x77 + wait_irq = 0x30 - recv = [] - bits = irq_en = wait_irq = n = 0 - stat = self.ERR + self._wreg(0x02, irq_en | 0x80) + self._cflags(0x04, 0x80) + self._sflags(0x0A, 0x80) + self._wreg(0x01, 0x00) - if cmd == 0x0E: - irq_en = 0x12 - wait_irq = 0x10 - elif cmd == 0x0C: - irq_en = 0x77 - wait_irq = 0x30 + for c in send: + self._wreg(0x09, c) + self._wreg(0x01, cmd) + + if cmd == 0x0C: + self._sflags(0x0D, 0x80) + + i = 2000 + while True: + n = self._rreg(0x04) + i -= 1 + if ~((i != 0) and ~(n & 0x01) and ~(n & wait_irq)): + break - self._wreg(0x02, irq_en | 0x80) - self._cflags(0x04, 0x80) - self._sflags(0x0A, 0x80) - self._wreg(0x01, 0x00) + self._cflags(0x0D, 0x80) + + if i: + if (self._rreg(0x06) & 0x1B) == 0x00: + stat = self.OK + + if n & irq_en & 0x01: + stat = self.NOTAGERR + elif cmd == 0x0C: + n = self._rreg(0x0A) + lbits = self._rreg(0x0C) & 0x07 + if lbits != 0: + bits = (n - 1) * 8 + lbits + else: + bits = n * 8 - for c in send: - self._wreg(0x09, c) - self._wreg(0x01, cmd) + if n == 0: + n = 1 + elif n > 16: + n = 16 - if cmd == 0x0C: - self._sflags(0x0D, 0x80) + for _ in range(n): + recv.append(self._rreg(0x09)) + else: + stat = self.ERR - i = 2000 - while True: - n = self._rreg(0x04) - i -= 1 - if ~((i != 0) and ~(n & 0x01) and ~(n & wait_irq)): - break + return stat, recv, bits - self._cflags(0x0D, 0x80) + def _crc(self, data): - if i: - if (self._rreg(0x06) & 0x1B) == 0x00: - stat = self.OK + self._cflags(0x05, 0x04) + self._sflags(0x0A, 0x80) - if n & irq_en & 0x01: - stat = self.NOTAGERR - elif cmd == 0x0C: - n = self._rreg(0x0A) - lbits = self._rreg(0x0C) & 0x07 - if lbits != 0: - bits = (n - 1) * 8 + lbits - else: - bits = n * 8 + for c in data: + self._wreg(0x09, c) - if n == 0: - n = 1 - elif n > 16: - n = 16 + self._wreg(0x01, 0x03) - for _ in range(n): - recv.append(self._rreg(0x09)) - else: - stat = self.ERR + i = 0xFF + while True: + n = self._rreg(0x05) + i -= 1 + if not ((i != 0) and not (n & 0x04)): + break - return stat, recv, bits + return [self._rreg(0x22), self._rreg(0x21)] - def _crc(self, data): + def init(self): - self._cflags(0x05, 0x04) - self._sflags(0x0A, 0x80) + self.reset() + self._wreg(0x2A, 0x8D) + self._wreg(0x2B, 0x3E) + self._wreg(0x2D, 30) + self._wreg(0x2C, 0) + self._wreg(0x15, 0x40) + self._wreg(0x11, 0x3D) + self.antenna_on() - for c in data: - self._wreg(0x09, c) + def reset(self): + self._wreg(0x01, 0x0F) - self._wreg(0x01, 0x03) + def antenna_on(self, on=True): - i = 0xFF - while True: - n = self._rreg(0x05) - i -= 1 - if not ((i != 0) and not (n & 0x04)): - break + if on and ~(self._rreg(0x14) & 0x03): + self._sflags(0x14, 0x03) + else: + self._cflags(0x14, 0x03) - return [self._rreg(0x22), self._rreg(0x21)] + def request(self, mode): - def init(self): + self._wreg(0x0D, 0x07) + (stat, recv, bits) = self._tocard(0x0C, [mode]) - self.reset() - self._wreg(0x2A, 0x8D) - self._wreg(0x2B, 0x3E) - self._wreg(0x2D, 30) - self._wreg(0x2C, 0) - self._wreg(0x15, 0x40) - self._wreg(0x11, 0x3D) - self.antenna_on() + if (stat != self.OK) | (bits != 0x10): + stat = self.ERR - def reset(self): - self._wreg(0x01, 0x0F) + return stat, bits - def antenna_on(self, on=True): + def anticoll(self): - if on and ~(self._rreg(0x14) & 0x03): - self._sflags(0x14, 0x03) - else: - self._cflags(0x14, 0x03) + ser_chk = 0 + ser = [0x93, 0x20] - def request(self, mode): + self._wreg(0x0D, 0x00) + (stat, recv, bits) = self._tocard(0x0C, ser) - self._wreg(0x0D, 0x07) - (stat, recv, bits) = self._tocard(0x0C, [mode]) + if stat == self.OK: + if len(recv) == 5: + for i in range(4): + ser_chk = ser_chk ^ recv[i] + if ser_chk != recv[4]: + stat = self.ERR + else: + stat = self.ERR - if (stat != self.OK) | (bits != 0x10): - stat = self.ERR + return stat, recv - return stat, bits + def select_tag(self, ser): - def anticoll(self): + buf = [0x93, 0x70] + ser[:5] + buf += self._crc(buf) + (stat, recv, bits) = self._tocard(0x0C, buf) + return self.OK if (stat == self.OK) and (bits == 0x18) else self.ERR - ser_chk = 0 - ser = [0x93, 0x20] + def auth(self, mode, addr, sect, ser): + return self._tocard(0x0E, [mode, addr] + sect + ser[:4])[0] - self._wreg(0x0D, 0x00) - (stat, recv, bits) = self._tocard(0x0C, ser) + def stop_crypto1(self): + self._cflags(0x08, 0x08) - if stat == self.OK: - if len(recv) == 5: - for i in range(4): - ser_chk = ser_chk ^ recv[i] - if ser_chk != recv[4]: - stat = self.ERR - else: - stat = self.ERR + def read(self, addr): - return stat, recv + data = [0x30, addr] + data += self._crc(data) + (stat, recv, _) = self._tocard(0x0C, data) + return recv if stat == self.OK else None - def select_tag(self, ser): + def write(self, addr, data): - buf = [0x93, 0x70] + ser[:5] - buf += self._crc(buf) - (stat, recv, bits) = self._tocard(0x0C, buf) - return self.OK if (stat == self.OK) and (bits == 0x18) else self.ERR + buf = [0xA0, addr] + buf += self._crc(buf) + (stat, recv, bits) = self._tocard(0x0C, buf) - def auth(self, mode, addr, sect, ser): - return self._tocard(0x0E, [mode, addr] + sect + ser[:4])[0] + if not (stat == self.OK) or not (bits == 4) or not ((recv[0] & 0x0F) == 0x0A): + stat = self.ERR + else: + buf = [] + for i in range(16): + buf.append(data[i]) + buf += self._crc(buf) + (stat, recv, bits) = self._tocard(0x0C, buf) + if not (stat == self.OK) or not (bits == 4) or not ((recv[0] & 0x0F) == 0x0A): + stat = self.ERR - def stop_crypto1(self): - self._cflags(0x08, 0x08) - - def read(self, addr): - - data = [0x30, addr] - data += self._crc(data) - (stat, recv, _) = self._tocard(0x0C, data) - return recv if stat == self.OK else None - - def write(self, addr, data): - - buf = [0xA0, addr] - buf += self._crc(buf) - (stat, recv, bits) = self._tocard(0x0C, buf) - - if not (stat == self.OK) or not (bits == 4) or not ((recv[0] & 0x0F) == 0x0A): - stat = self.ERR - else: - buf = [] - for i in range(16): - buf.append(data[i]) - buf += self._crc(buf) - (stat, recv, bits) = self._tocard(0x0C, buf) - if not (stat == self.OK) or not (bits == 4) or not ((recv[0] & 0x0F) == 0x0A): - stat = self.ERR - - return stat + return stat From d23e5751574c66d8d5cbf34558172858529dafff Mon Sep 17 00:00:00 2001 From: Chris Ranc Date: Sun, 25 Mar 2018 11:44:39 -0400 Subject: [PATCH 2/3] fixed error with baud rate for esp and updated read and write examples --- examples/read.py | 12 +- examples/write.py | 7 +- mfrc522.py | 386 +++++++++++++++++++++++----------------------- 3 files changed, 206 insertions(+), 199 deletions(-) diff --git a/examples/read.py b/examples/read.py index 783d554..101e943 100644 --- a/examples/read.py +++ b/examples/read.py @@ -2,12 +2,15 @@ from os import uname -def do_read(): +def do_read( esp=None): if uname()[0] == 'WiPy': rdr = mfrc522.MFRC522("GP14", "GP16", "GP15", "GP22", "GP17") - elif uname()[0] == 'esp8266': - rdr = mfrc522.MFRC522(0, 2, 4, 5, 14) + elif uname()[0] == 'esp8266' and esp != None: + if esp==1: + rdr = mfrc522.MFRC522(rst=2,cs=16,spiblk=1) + else: + rdr = mfrc522.MFRC522(rst=2,cs=16,sck=14,mosi=13,miso=12) else: raise RuntimeError("Unsupported platform") @@ -43,4 +46,5 @@ def do_read(): print("Failed to select tag") except KeyboardInterrupt: - print("Bye") \ No newline at end of file + print("Bye") + diff --git a/examples/write.py b/examples/write.py index 7878d83..08fbff7 100644 --- a/examples/write.py +++ b/examples/write.py @@ -2,12 +2,15 @@ from os import uname -def do_write(): +def do_write(esp=None): if uname()[0] == 'WiPy': rdr = mfrc522.MFRC522("GP14", "GP16", "GP15", "GP22", "GP17") elif uname()[0] == 'esp8266': - rdr = mfrc522.MFRC522(0, 2, 4, 5, 14) + if esp == 1: + rdr = mfrc522.MFRC522(rst=2,cs=16,spiblk=1) + else: + rdr = mfrc522.MFRC522(rst=2,cs=16,sck=14,mosi=13,miso=12) else: raise RuntimeError("Unsupported platform") diff --git a/mfrc522.py b/mfrc522.py index 73bd786..56df011 100644 --- a/mfrc522.py +++ b/mfrc522.py @@ -4,232 +4,232 @@ class MFRC522: - OK = 0 - NOTAGERR = 1 - ERR = 2 - - REQIDL = 0x26 - REQALL = 0x52 - AUTHENT1A = 0x60 - AUTHENT1B = 0x61 - - def __init__(self, rst, cs, spiblk=None, sck=None, mosi=None, miso=None): - if spiblk == None and (sck != mosi != miso): - self.sck = Pin(sck, Pin.OUT) - self.mosi = Pin(mosi, Pin.OUT) - self.miso = Pin(miso) - self.rst = Pin(rst, Pin.OUT) - self.cs = Pin(cs, Pin.OUT) - - self.rst.value(0) - self.cs.value(1) - - board = uname()[0] - - if board == 'WiPy' or board == 'LoPy' or board == 'FiPy': - if spiblk == None: - self.spi = SPI(0) - else: - self.spi = SPI(spiblk) - self.spi.init(SPI.MASTER, baudrate=1000000, pins=(self.sck, self.mosi, self.miso)) - elif board == 'esp8266': - if spiblk == None: - self.spi = SPI(baudrate=100000, polarity=0, phase=0, sck=self.sck, mosi=self.mosi, miso=self.miso) - else: - self.spi = SPI(spiblk, baudrate=100000, polarity=0, phase=0) - self.spi.init() - else: - raise RuntimeError("Unsupported platform") - - self.rst.value(1) - self.init() - - def _wreg(self, reg, val): - - self.cs.value(0) - self.spi.write(b'%c' % int(0xff & ((reg << 1) & 0x7e))) - self.spi.write(b'%c' % int(0xff & val)) - self.cs.value(1) - - def _rreg(self, reg): - - self.cs.value(0) - self.spi.write(b'%c' % int(0xff & (((reg << 1) & 0x7e) | 0x80))) - val = self.spi.read(1) - self.cs.value(1) - - return val[0] - - def _sflags(self, reg, mask): - self._wreg(reg, self._rreg(reg) | mask) - - def _cflags(self, reg, mask): - self._wreg(reg, self._rreg(reg) & (~mask)) - - def _tocard(self, cmd, send): - - recv = [] - bits = irq_en = wait_irq = n = 0 - stat = self.ERR - - if cmd == 0x0E: - irq_en = 0x12 - wait_irq = 0x10 - elif cmd == 0x0C: - irq_en = 0x77 - wait_irq = 0x30 + OK = 0 + NOTAGERR = 1 + ERR = 2 + + REQIDL = 0x26 + REQALL = 0x52 + AUTHENT1A = 0x60 + AUTHENT1B = 0x61 + + def __init__(self, rst, cs, spiblk=None, sck=None, mosi=None, miso=None): + if spiblk == None and (sck != mosi != miso): + self.sck = Pin(sck, Pin.OUT) + self.mosi = Pin(mosi, Pin.OUT) + self.miso = Pin(miso) + self.rst = Pin(rst, Pin.OUT) + self.cs = Pin(cs, Pin.OUT) + + self.rst.value(0) + self.cs.value(1) + + board = uname()[0] + + if board == 'WiPy' or board == 'LoPy' or board == 'FiPy': + if spiblk == None: + self.spi = SPI(0) + else: + self.spi = SPI(spiblk) + self.spi.init(SPI.MASTER, baudrate=1000000, pins=(self.sck, self.mosi, self.miso)) + elif board == 'esp8266': + if spiblk == None: + self.spi = SPI(baudrate=1000000, polarity=0, phase=0, sck=self.sck, mosi=self.mosi, miso=self.miso) + else: + self.spi = SPI(spiblk, baudrate=1000000, polarity=0, phase=0) + #self.spi.init() + else: + raise RuntimeError("Unsupported platform") + + self.rst.value(1) + self.init() + + def _wreg(self, reg, val): + + self.cs.value(0) + self.spi.write(b'%c' % int(0xff & ((reg << 1) & 0x7e))) + self.spi.write(b'%c' % int(0xff & val)) + self.cs.value(1) + + def _rreg(self, reg): + + self.cs.value(0) + self.spi.write(b'%c' % int(0xff & (((reg << 1) & 0x7e) | 0x80))) + val = self.spi.read(1) + self.cs.value(1) + + return val[0] + + def _sflags(self, reg, mask): + self._wreg(reg, self._rreg(reg) | mask) + + def _cflags(self, reg, mask): + self._wreg(reg, self._rreg(reg) & (~mask)) + + def _tocard(self, cmd, send): + + recv = [] + bits = irq_en = wait_irq = n = 0 + stat = self.ERR + + if cmd == 0x0E: + irq_en = 0x12 + wait_irq = 0x10 + elif cmd == 0x0C: + irq_en = 0x77 + wait_irq = 0x30 - self._wreg(0x02, irq_en | 0x80) - self._cflags(0x04, 0x80) - self._sflags(0x0A, 0x80) - self._wreg(0x01, 0x00) + self._wreg(0x02, irq_en | 0x80) + self._cflags(0x04, 0x80) + self._sflags(0x0A, 0x80) + self._wreg(0x01, 0x00) - for c in send: - self._wreg(0x09, c) - self._wreg(0x01, cmd) - - if cmd == 0x0C: - self._sflags(0x0D, 0x80) - - i = 2000 - while True: - n = self._rreg(0x04) - i -= 1 - if ~((i != 0) and ~(n & 0x01) and ~(n & wait_irq)): - break + for c in send: + self._wreg(0x09, c) + self._wreg(0x01, cmd) + + if cmd == 0x0C: + self._sflags(0x0D, 0x80) + + i = 2000 + while True: + n = self._rreg(0x04) + i -= 1 + if ~((i != 0) and ~(n & 0x01) and ~(n & wait_irq)): + break - self._cflags(0x0D, 0x80) - - if i: - if (self._rreg(0x06) & 0x1B) == 0x00: - stat = self.OK - - if n & irq_en & 0x01: - stat = self.NOTAGERR - elif cmd == 0x0C: - n = self._rreg(0x0A) - lbits = self._rreg(0x0C) & 0x07 - if lbits != 0: - bits = (n - 1) * 8 + lbits - else: - bits = n * 8 + self._cflags(0x0D, 0x80) + + if i: + if (self._rreg(0x06) & 0x1B) == 0x00: + stat = self.OK + + if n & irq_en & 0x01: + stat = self.NOTAGERR + elif cmd == 0x0C: + n = self._rreg(0x0A) + lbits = self._rreg(0x0C) & 0x07 + if lbits != 0: + bits = (n - 1) * 8 + lbits + else: + bits = n * 8 - if n == 0: - n = 1 - elif n > 16: - n = 16 + if n == 0: + n = 1 + elif n > 16: + n = 16 - for _ in range(n): - recv.append(self._rreg(0x09)) - else: - stat = self.ERR + for _ in range(n): + recv.append(self._rreg(0x09)) + else: + stat = self.ERR - return stat, recv, bits + return stat, recv, bits - def _crc(self, data): + def _crc(self, data): - self._cflags(0x05, 0x04) - self._sflags(0x0A, 0x80) + self._cflags(0x05, 0x04) + self._sflags(0x0A, 0x80) - for c in data: - self._wreg(0x09, c) + for c in data: + self._wreg(0x09, c) - self._wreg(0x01, 0x03) + self._wreg(0x01, 0x03) - i = 0xFF - while True: - n = self._rreg(0x05) - i -= 1 - if not ((i != 0) and not (n & 0x04)): - break + i = 0xFF + while True: + n = self._rreg(0x05) + i -= 1 + if not ((i != 0) and not (n & 0x04)): + break - return [self._rreg(0x22), self._rreg(0x21)] + return [self._rreg(0x22), self._rreg(0x21)] - def init(self): + def init(self): - self.reset() - self._wreg(0x2A, 0x8D) - self._wreg(0x2B, 0x3E) - self._wreg(0x2D, 30) - self._wreg(0x2C, 0) - self._wreg(0x15, 0x40) - self._wreg(0x11, 0x3D) - self.antenna_on() + self.reset() + self._wreg(0x2A, 0x8D) + self._wreg(0x2B, 0x3E) + self._wreg(0x2D, 30) + self._wreg(0x2C, 0) + self._wreg(0x15, 0x40) + self._wreg(0x11, 0x3D) + self.antenna_on() - def reset(self): - self._wreg(0x01, 0x0F) + def reset(self): + self._wreg(0x01, 0x0F) - def antenna_on(self, on=True): + def antenna_on(self, on=True): - if on and ~(self._rreg(0x14) & 0x03): - self._sflags(0x14, 0x03) - else: - self._cflags(0x14, 0x03) + if on and ~(self._rreg(0x14) & 0x03): + self._sflags(0x14, 0x03) + else: + self._cflags(0x14, 0x03) - def request(self, mode): + def request(self, mode): - self._wreg(0x0D, 0x07) - (stat, recv, bits) = self._tocard(0x0C, [mode]) + self._wreg(0x0D, 0x07) + (stat, recv, bits) = self._tocard(0x0C, [mode]) - if (stat != self.OK) | (bits != 0x10): - stat = self.ERR + if (stat != self.OK) | (bits != 0x10): + stat = self.ERR - return stat, bits + return stat, bits - def anticoll(self): + def anticoll(self): - ser_chk = 0 - ser = [0x93, 0x20] + ser_chk = 0 + ser = [0x93, 0x20] - self._wreg(0x0D, 0x00) - (stat, recv, bits) = self._tocard(0x0C, ser) + self._wreg(0x0D, 0x00) + (stat, recv, bits) = self._tocard(0x0C, ser) - if stat == self.OK: - if len(recv) == 5: - for i in range(4): - ser_chk = ser_chk ^ recv[i] - if ser_chk != recv[4]: - stat = self.ERR - else: - stat = self.ERR + if stat == self.OK: + if len(recv) == 5: + for i in range(4): + ser_chk = ser_chk ^ recv[i] + if ser_chk != recv[4]: + stat = self.ERR + else: + stat = self.ERR - return stat, recv + return stat, recv - def select_tag(self, ser): + def select_tag(self, ser): - buf = [0x93, 0x70] + ser[:5] - buf += self._crc(buf) - (stat, recv, bits) = self._tocard(0x0C, buf) - return self.OK if (stat == self.OK) and (bits == 0x18) else self.ERR + buf = [0x93, 0x70] + ser[:5] + buf += self._crc(buf) + (stat, recv, bits) = self._tocard(0x0C, buf) + return self.OK if (stat == self.OK) and (bits == 0x18) else self.ERR - def auth(self, mode, addr, sect, ser): - return self._tocard(0x0E, [mode, addr] + sect + ser[:4])[0] + def auth(self, mode, addr, sect, ser): + return self._tocard(0x0E, [mode, addr] + sect + ser[:4])[0] - def stop_crypto1(self): - self._cflags(0x08, 0x08) + def stop_crypto1(self): + self._cflags(0x08, 0x08) - def read(self, addr): + def read(self, addr): - data = [0x30, addr] - data += self._crc(data) - (stat, recv, _) = self._tocard(0x0C, data) - return recv if stat == self.OK else None + data = [0x30, addr] + data += self._crc(data) + (stat, recv, _) = self._tocard(0x0C, data) + return recv if stat == self.OK else None - def write(self, addr, data): + def write(self, addr, data): - buf = [0xA0, addr] - buf += self._crc(buf) - (stat, recv, bits) = self._tocard(0x0C, buf) + buf = [0xA0, addr] + buf += self._crc(buf) + (stat, recv, bits) = self._tocard(0x0C, buf) - if not (stat == self.OK) or not (bits == 4) or not ((recv[0] & 0x0F) == 0x0A): - stat = self.ERR - else: - buf = [] - for i in range(16): - buf.append(data[i]) - buf += self._crc(buf) - (stat, recv, bits) = self._tocard(0x0C, buf) - if not (stat == self.OK) or not (bits == 4) or not ((recv[0] & 0x0F) == 0x0A): - stat = self.ERR + if not (stat == self.OK) or not (bits == 4) or not ((recv[0] & 0x0F) == 0x0A): + stat = self.ERR + else: + buf = [] + for i in range(16): + buf.append(data[i]) + buf += self._crc(buf) + (stat, recv, bits) = self._tocard(0x0C, buf) + if not (stat == self.OK) or not (bits == 4) or not ((recv[0] & 0x0F) == 0x0A): + stat = self.ERR - return stat + return stat From 25bf0e0750b31534de6931351a248f88665feb2c Mon Sep 17 00:00:00 2001 From: Chris Ranc Date: Sun, 25 Mar 2018 11:53:02 -0400 Subject: [PATCH 3/3] update README for hardware pins pi explanation --- README.md | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/README.md b/README.md index ff50f49..d89300b 100644 --- a/README.md +++ b/README.md @@ -18,18 +18,22 @@ I used the following pins for my setup: | Signal | GPIO ESP8266 | GPIO WiPy | Note | | --------- | ------------ | -------------- | ------------------------------------ | -| sck | 0 | "GP14" | | -| mosi | 2 | "GP16" | | -| miso | 4 | "GP15" | | -| rst | 5 | "GP22" | | -| cs | 14 | "GP14" |Labeled SDA on most RFID-RC522 boards | - +| sck | 14 | "GP14" |For hardware sck (esp) | +| mosi | 13 | "GP16" |For hardware mosi (esp) | +| miso | 12 | "GP15" |For hardware miso (esp) | +| rst | 2 | "GP22" | | +| cs | 16 | "GP14" |Labeled SDA on most RFID-RC522 boards | + +Note for the hardware spi on the esp8266 the sck, mosi, and miso pins don't need to be specified for initalization, +only spiblk needs to be set to 1. In software mode they will need to be specified and spblk can be left unset. + Now enter the REPL you could run one of the two exmaples: For detecting, authenticating and reading from a card: import read - read.do_read() + read.do_read() #for software + read.do_read(1) #for esp hardware This will wait for a MifareClassic 1k card. As soon the card is detected, it is authenticated, and 16 bytes are read from address 0x08.