16:08:29.667 Running test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_CreateBreakPropagateMask_int()
Supported ISAs:
  AdvSimd:   True
  Aes:       True
  ArmBase:   True
  Crc32:     True
  Dp:        True
  Rdm:       False
  Sha1:      True
  Sha256:    True
  Sve:       True

Beginning scenario: RunBasicScenario_UnsafeRead
****** START compiling JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:RunBasicScenario_Load():this (MethodHash=8627947d)
Generating code for Windows arm64
OPTIONS: Tier-0 compilation (set DOTNET_TieredCompilation=0 to disable)
OPTIONS: compCodeOpt = BLENDED_CODE
OPTIONS: compDbgCode = false
OPTIONS: compDbgInfo = true
OPTIONS: compDbgEnC  = false
OPTIONS: compProcedureSplitting   = false
OPTIONS: compProcedureSplittingEH = false
IL to import:
IL_0000  72 bd 01 00 70    ldstr        0x700001BD
IL_0005  28 c0 00 00 0a    call         0xA0000C0
IL_000a  1f 1f             ldc.i4.s     0x1F
IL_000c  28 e8 00 00 0a    call         0xA0000E8
IL_0011  0a                stloc.0     
IL_0012  06                ldloc.0     
IL_0013  02                ldarg.0     
IL_0014  7c 02 0b 00 04    ldflda       0x4000B02
IL_0019  28 1e 74 00 06    call         0x600741E
IL_001e  28 e9 00 00 0a    call         0xA0000E9
IL_0023  06                ldloc.0     
IL_0024  02                ldarg.0     
IL_0025  7c 02 0b 00 04    ldflda       0x4000B02
IL_002a  28 1f 74 00 06    call         0x600741F
IL_002f  28 e9 00 00 0a    call         0xA0000E9
IL_0034  28 e3 01 00 0a    call         0xA0001E3
IL_0039  0b                stloc.1     
IL_003a  02                ldarg.0     
IL_003b  7c 02 0b 00 04    ldflda       0x4000B02
IL_0040  28 20 74 00 06    call         0x6007420
IL_0045  07                ldloc.1     
IL_0046  28 40 00 00 2b    call         0x2B000040
IL_004b  02                ldarg.0     
IL_004c  02                ldarg.0     
IL_004d  7c 02 0b 00 04    ldflda       0x4000B02
IL_0052  28 1e 74 00 06    call         0x600741E
IL_0057  02                ldarg.0     
IL_0058  7c 02 0b 00 04    ldflda       0x4000B02
IL_005d  28 1f 74 00 06    call         0x600741F
IL_0062  02                ldarg.0     
IL_0063  7c 02 0b 00 04    ldflda       0x4000B02
IL_0068  28 20 74 00 06    call         0x6007420
IL_006d  72 bd 01 00 70    ldstr        0x700001BD
IL_0072  28 ae 1f 00 06    call         0x6001FAE
IL_0077  2a                ret         

lvaSetClass: setting class for V00 to (00007FFAC2047010) JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int 
'this'    passed in register x0
Parameter V00 ABI info: [00..08) reg x0
Notify VM instruction set (AdvSimd) must be supported.
 Found Vector<int>
Notify VM instruction set (VectorT128) must be supported.

lvaGrabTemp returning 3 (V03 tmp0) (a long lifetime temp) called for OutgoingArgSpace.

Local V03 should not be enregistered because: it is address exposed
; Initial local variable assignments
;
;  V00 this              ref  this class-hnd <JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int>
;  V01 loc0           simd16  HFA(simd16)  <System.Numerics.Vector`1[int]>
;  V02 loc1           simd16  HFA(simd16)  <System.Numerics.Vector`1[int]>
;  V03 OutArgs        struct <0> do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
*************** In compInitDebuggingInfo() for JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:RunBasicScenario_Load():this
getVars() returned cVars = 0, extendOthers = true
info.compVarScopesCount = 3
    	VarNum 	LVNum 	      Name 	Beg 	End
 0: 	00h 	00h 	  V00 this 	000h   	078h
 1: 	01h 	01h 	  V01 loc0 	000h   	078h
 2: 	02h 	02h 	  V02 loc1 	000h   	078h
info.compStmtOffsetsCount    = 0
info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE )
*************** In fgFindBasicBlocks() for JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:RunBasicScenario_Load():this
Marked V01 as a single def local
Marked V02 as a single def local
Jump targets:
  none
New Basic Block BB01 [0000] created.
BB01 [0000] [000..078)
CLFLG_MINOPT set for method JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:RunBasicScenario_Load():this
IL Code Size,Instr  120,  35, Basic Block count   1, Local Variable Num,Ref count   4, 12 for method JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:RunBasicScenario_Load():this
IL Code Size,Instr  120,  35, Basic Block count   1, Local Variable Num,Ref count   4, 12 for method JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:RunBasicScenario_Load():this
OPTIONS: opts.MinOpts() == true
Basic block list for 'JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:RunBasicScenario_Load():this'

---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   [IL range]   [jump]                            [EH region]        [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    [000..078)                           (return)                     
---------------------------------------------------------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Pre-import

*************** Finishing PHASE Pre-import
Trees after Pre-import

---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   [IL range]   [jump]                            [EH region]        [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    [000..078)                           (return)                     
---------------------------------------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [0000] [000..078) (return), preds={} succs={}

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist

*************** Starting PHASE Profile incorporation
not optimizing, so not incorporating any profile data

*************** Finishing PHASE Profile incorporation [no changes]

*************** Starting PHASE Importation

impImportBlockPending for BB01

Importing BB01 (PC=000) of 'JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:RunBasicScenario_Load():this'
    [ 0]   0 (0x000) ldstr 700001BD
    [ 1]   5 (0x005) call 0A0000C0
In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0


STMT00000 ( 0x000[E-] ... ??? )
               [000001] --C-G------                         *  CALL      void   TestLibrary.TestFramework:BeginScenario(System.String)
               [000000] ----------- arg0                    \--*  CNS_STR   ref   <string constant>

    [ 0]  10 (0x00a) ldc.i4.s 31
    [ 1]  12 (0x00c) call 0A0000E8
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Named Intrinsic System.Runtime.Intrinsics.Arm.Sve.CreateTrueMaskInt32: Notify VM instruction set (Sve) must be supported.
Recognized
 Found Vector<int>
 Found Vector<int>

    [ 1]  17 (0x011) stloc.0

STMT00001 ( 0x00A[E-] ... ??? )
               [000005] DA---------                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V01 loc0         
               [000004] -----------                         \--*  HWINTRINSIC simd16 int ConvertMaskToVector
               [000003] -----------                            \--*  HWINTRINSIC mask   int CreateTrueMaskInt32
               [000002] -----------                               \--*  CNS_INT   int    31

    [ 0]  18 (0x012) ldloc.0
    [ 1]  19 (0x013) ldarg.0
    [ 2]  20 (0x014) ldflda 04000B02
    [ 2]  25 (0x019) call 0600741E
In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0

    [ 2]  30 (0x01e) call 0A0000E9
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Named Intrinsic System.Runtime.Intrinsics.Arm.Sve.LoadVector: Recognized
 Found Vector<int>
 Found Vector<int>
 Found Vector<int>

    [ 1]  35 (0x023) ldloc.0
    [ 2]  36 (0x024) ldarg.0
    [ 3]  37 (0x025) ldflda 04000B02
    [ 3]  42 (0x02a) call 0600741F
In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0

lvaGrabTemp returning 4 (V04 tmp1) called for non-inline candidate call.


STMT00002 ( 0x012[E-] ... ??? )
               [000017] DACXG------                         *  STORE_LCL_VAR simd16 V04 tmp1         
               [000010] --CXG------                         \--*  HWINTRINSIC simd16 int LoadVector
               [000012] -----------                            +--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000011] -----------                            |  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000006] -----------                            |  \--*  LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0         
               [000009] --CXG------                            \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
               [000008] ---X------- this                          \--*  FIELD_ADDR byref  JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:_dataTable
               [000007] -----------                                  \--*  LCL_VAR   ref    V00 this         
Marked V04 as a single def temp

    [ 3]  47 (0x02f) call 0A0000E9
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Named Intrinsic System.Runtime.Intrinsics.Arm.Sve.LoadVector: Recognized
 Found Vector<int>
 Found Vector<int>
 Found Vector<int>

    [ 2]  52 (0x034) call 0A0001E3
In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16
Named Intrinsic System.Runtime.Intrinsics.Arm.Sve.CreateBreakPropagateMask: Recognized
 Found Vector<int>
 Found Vector<int>
 Found Vector<int>
 Found Vector<int>

    [ 1]  57 (0x039) stloc.1

STMT00003 ( ??? ... ??? )
               [000028] DACXG------                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V02 loc1         
               [000027] --CXG------                         \--*  HWINTRINSIC simd16 int ConvertMaskToVector
               [000022] --CXG------                            \--*  HWINTRINSIC mask   int CreateBreakPropagateMask
               [000024] -----------                               +--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000023] -----------                               |  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000018] -----------                               |  \--*  LCL_VAR   simd16 V04 tmp1         
               [000026] --CXG------                               \--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000025] -----------                                  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000019] --CXG------                                  \--*  HWINTRINSIC simd16 int LoadVector
               [000021] -----------                                     +--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000020] -----------                                     |  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000013] -----------                                     |  \--*  LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0         
               [000016] --CXG------                                     \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
               [000015] ---X------- this                                   \--*  FIELD_ADDR byref  JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:_dataTable
               [000014] -----------                                           \--*  LCL_VAR   ref    V00 this         

    [ 0]  58 (0x03a) ldarg.0
    [ 1]  59 (0x03b) ldflda 04000B02
    [ 1]  64 (0x040) call 06007420
In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0

    [ 1]  69 (0x045) ldloc.1
    [ 2]  70 (0x046) call 2B000040
In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0
Named Intrinsic System.Runtime.CompilerServices.Unsafe.Write: Recognized


STMT00004 ( 0x03A[E-] ... ??? )
               [000033] -ACXG------                         *  STOREIND  simd16 (copy)
               [000031] --CXG------                         +--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
               [000030] ---X------- this                    |  \--*  FIELD_ADDR byref  JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:_dataTable
               [000029] -----------                         |     \--*  LCL_VAR   ref    V00 this         
               [000032] -----------                         \--*  LCL_VAR   simd16<System.Numerics.Vector`1> V02 loc1         

    [ 0]  75 (0x04b) ldarg.0
    [ 1]  76 (0x04c) ldarg.0
    [ 2]  77 (0x04d) ldflda 04000B02
    [ 2]  82 (0x052) call 0600741E
In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0

    [ 2]  87 (0x057) ldarg.0
    [ 3]  88 (0x058) ldflda 04000B02
    [ 3]  93 (0x05d) call 0600741F
In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0

lvaGrabTemp returning 5 (V05 tmp2) called for non-inline candidate call.


STMT00005 ( 0x04B[E-] ... ??? )
               [000041] DACXG------                         *  STORE_LCL_VAR long   V05 tmp2         
               [000037] --CXG------                         \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
               [000036] ---X------- this                       \--*  FIELD_ADDR byref  JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:_dataTable
               [000035] -----------                               \--*  LCL_VAR   ref    V00 this         
Marked V05 as a single def temp

    [ 3]  98 (0x062) ldarg.0
    [ 4]  99 (0x063) ldflda 04000B02
    [ 4] 104 (0x068) call 06007420
In Compiler::impImportCall: opcode is call, kind=0, callRetType is long, structSize is 0

lvaGrabTemp returning 6 (V06 tmp3) called for non-inline candidate call.


STMT00006 ( ??? ... ??? )
               [000046] DACXG------                         *  STORE_LCL_VAR long   V06 tmp3         
               [000040] --CXG------                         \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
               [000039] ---X------- this                       \--*  FIELD_ADDR byref  JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:_dataTable
               [000038] -----------                               \--*  LCL_VAR   ref    V00 this         
Marked V06 as a single def temp

    [ 4] 109 (0x06d) ldstr 700001BD
    [ 5] 114 (0x072) call 06001FAE
In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0


STMT00007 ( ??? ... ??? )
               [000049] --CXG------                         *  CALL      void   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:ValidateResult(ulong,ulong,ulong,System.String):this
               [000034] ----------- this                    +--*  LCL_VAR   ref    V00 this         
               [000042] ----------- arg1                    +--*  LCL_VAR   long   V05 tmp2         
               [000047] ----------- arg2                    +--*  LCL_VAR   long   V06 tmp3         
               [000045] --CXG------ arg3                    +--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
               [000044] ---X------- this                    |  \--*  FIELD_ADDR byref  JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:_dataTable
               [000043] -----------                         |     \--*  LCL_VAR   ref    V00 this         
               [000048] ----------- arg4                    \--*  CNS_STR   ref   <string constant>

    [ 0] 119 (0x077) ret

STMT00008 ( 0x077[E-] ... ??? )
               [000050] -----------                         *  RETURN    void  

*************** Finishing PHASE Importation
Trees after Importation

---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   [IL range]   [jump]                            [EH region]        [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    [000..078)                           (return)                     i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [0000] [000..078) (return), preds={} succs={}

***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x011 )
               [000001] --C-G------                         *  CALL      void   TestLibrary.TestFramework:BeginScenario(System.String)
               [000000] ----------- arg0                    \--*  CNS_STR   ref   <string constant>

***** BB01 [0000]
STMT00001 ( 0x00A[E-] ... ??? )
               [000005] DA---------                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V01 loc0         
               [000004] -----------                         \--*  HWINTRINSIC simd16 int ConvertMaskToVector
               [000003] -----------                            \--*  HWINTRINSIC mask   int CreateTrueMaskInt32
               [000002] -----------                               \--*  CNS_INT   int    31

***** BB01 [0000]
STMT00002 ( 0x012[E-] ... 0x039 )
               [000017] DACXG------                         *  STORE_LCL_VAR simd16 V04 tmp1         
               [000010] --CXG------                         \--*  HWINTRINSIC simd16 int LoadVector
               [000012] -----------                            +--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000011] -----------                            |  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000006] -----------                            |  \--*  LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0         
               [000009] --CXG------                            \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
               [000008] ---X------- this                          \--*  FIELD_ADDR byref  JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:_dataTable
               [000007] -----------                                  \--*  LCL_VAR   ref    V00 this         

***** BB01 [0000]
STMT00003 ( ??? ... ??? )
               [000028] DACXG------                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V02 loc1         
               [000027] --CXG------                         \--*  HWINTRINSIC simd16 int ConvertMaskToVector
               [000022] --CXG------                            \--*  HWINTRINSIC mask   int CreateBreakPropagateMask
               [000024] -----------                               +--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000023] -----------                               |  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000018] -----------                               |  \--*  LCL_VAR   simd16 V04 tmp1         
               [000026] --CXG------                               \--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000025] -----------                                  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000019] --CXG------                                  \--*  HWINTRINSIC simd16 int LoadVector
               [000021] -----------                                     +--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000020] -----------                                     |  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000013] -----------                                     |  \--*  LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0         
               [000016] --CXG------                                     \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
               [000015] ---X------- this                                   \--*  FIELD_ADDR byref  JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:_dataTable
               [000014] -----------                                           \--*  LCL_VAR   ref    V00 this         

***** BB01 [0000]
STMT00004 ( 0x03A[E-] ... 0x077 )
               [000033] -ACXG------                         *  STOREIND  simd16 (copy)
               [000031] --CXG------                         +--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
               [000030] ---X------- this                    |  \--*  FIELD_ADDR byref  JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:_dataTable
               [000029] -----------                         |     \--*  LCL_VAR   ref    V00 this         
               [000032] -----------                         \--*  LCL_VAR   simd16<System.Numerics.Vector`1> V02 loc1         

***** BB01 [0000]
STMT00005 ( 0x04B[E-] ... ??? )
               [000041] DACXG------                         *  STORE_LCL_VAR long   V05 tmp2         
               [000037] --CXG------                         \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
               [000036] ---X------- this                       \--*  FIELD_ADDR byref  JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:_dataTable
               [000035] -----------                               \--*  LCL_VAR   ref    V00 this         

***** BB01 [0000]
STMT00006 ( ??? ... ??? )
               [000046] DACXG------                         *  STORE_LCL_VAR long   V06 tmp3         
               [000040] --CXG------                         \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
               [000039] ---X------- this                       \--*  FIELD_ADDR byref  JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:_dataTable
               [000038] -----------                               \--*  LCL_VAR   ref    V00 this         

***** BB01 [0000]
STMT00007 ( ??? ... ??? )
               [000049] --CXG------                         *  CALL      void   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:ValidateResult(ulong,ulong,ulong,System.String):this
               [000034] ----------- this                    +--*  LCL_VAR   ref    V00 this         
               [000042] ----------- arg1                    +--*  LCL_VAR   long   V05 tmp2         
               [000047] ----------- arg2                    +--*  LCL_VAR   long   V06 tmp3         
               [000045] --CXG------ arg3                    +--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
               [000044] ---X------- this                    |  \--*  FIELD_ADDR byref  JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:_dataTable
               [000043] -----------                         |     \--*  LCL_VAR   ref    V00 this         
               [000048] ----------- arg4                    \--*  CNS_STR   ref   <string constant>

***** BB01 [0000]
STMT00008 ( 0x077[E-] ... ??? )
               [000050] -----------                         *  RETURN    void  

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]

*************** Starting PHASE Expand patchpoints

 -- no patchpoints to transform

*************** Finishing PHASE Expand patchpoints [no changes]

*************** Starting PHASE Indirect call transform

 -- no candidates to transform

*************** Finishing PHASE Indirect call transform [no changes]

*************** Starting PHASE Post-import

*************** Finishing PHASE Post-import [no changes]

*************** Starting PHASE Morph - Init

New BlockSet epoch 1, # of blocks (including unused BB00): 2, bitset array size: 1 (short)

*************** Finishing PHASE Morph - Init [no changes]

*************** Starting PHASE Morph - Inlining

*************** Finishing PHASE Morph - Inlining [no changes]

*************** Starting PHASE Allocate Objects
no newobjs in this method; punting

*************** Finishing PHASE Allocate Objects [no changes]

*************** Starting PHASE Morph - Add internal blocks

*************** After fgAddInternal()

---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   [IL range]   [jump]                            [EH region]        [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    [000..078)                           (return)                     i
---------------------------------------------------------------------------------------------------------------------------------------------------------------------

***************  Exception Handling table is empty

*************** Finishing PHASE Morph - Add internal blocks [no changes]

*************** Starting PHASE Add Swift error returns

*************** Finishing PHASE Add Swift error returns [no changes]

*************** Starting PHASE Remove empty try

*************** In fgRemoveEmptyTry()
No EH in this method, nothing to remove.

*************** Finishing PHASE Remove empty try [no changes]

*************** Starting PHASE Remove empty finally
No EH in this method, nothing to remove.

*************** Finishing PHASE Remove empty finally [no changes]

*************** Starting PHASE Merge callfinally chains
No EH in this method, nothing to merge.

*************** Finishing PHASE Merge callfinally chains [no changes]

*************** Starting PHASE Clone finally
No EH in this method, no cloning.

*************** Finishing PHASE Clone finally [no changes]

*************** Starting PHASE Morph - Promote Structs
  promotion opt flag not enabled

*************** Finishing PHASE Morph - Promote Structs [no changes]

*************** Starting PHASE Morph - Structs/AddrExp
LocalAddressVisitor visiting statement:
STMT00000 ( 0x000[E-] ... 0x011 )
               [000001] --C-G------                         *  CALL      void   TestLibrary.TestFramework:BeginScenario(System.String)
               [000000] ----------- arg0                    \--*  CNS_STR   ref   <string constant>

LocalAddressVisitor visiting statement:
STMT00001 ( 0x00A[E-] ... ??? )
               [000005] DA---------                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V01 loc0         
               [000004] -----------                         \--*  HWINTRINSIC simd16 int ConvertMaskToVector
               [000003] -----------                            \--*  HWINTRINSIC mask   int CreateTrueMaskInt32
               [000002] -----------                               \--*  CNS_INT   int    31

LocalAddressVisitor visiting statement:
STMT00002 ( 0x012[E-] ... 0x039 )
               [000017] DACXG------                         *  STORE_LCL_VAR simd16 V04 tmp1         
               [000010] --CXG------                         \--*  HWINTRINSIC simd16 int LoadVector
               [000012] -----------                            +--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000011] -----------                            |  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000006] -----------                            |  \--*  LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0         
               [000009] --CXG------                            \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
               [000008] ---X------- this                          \--*  FIELD_ADDR byref  JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:_dataTable
               [000007] -----------                                  \--*  LCL_VAR   ref    V00 this         

LocalAddressVisitor visiting statement:
STMT00003 ( ??? ... ??? )
               [000028] DACXG------                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V02 loc1         
               [000027] --CXG------                         \--*  HWINTRINSIC simd16 int ConvertMaskToVector
               [000022] --CXG------                            \--*  HWINTRINSIC mask   int CreateBreakPropagateMask
               [000024] -----------                               +--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000023] -----------                               |  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000018] -----------                               |  \--*  LCL_VAR   simd16 V04 tmp1         
               [000026] --CXG------                               \--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000025] -----------                                  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000019] --CXG------                                  \--*  HWINTRINSIC simd16 int LoadVector
               [000021] -----------                                     +--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000020] -----------                                     |  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000013] -----------                                     |  \--*  LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0         
               [000016] --CXG------                                     \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
               [000015] ---X------- this                                   \--*  FIELD_ADDR byref  JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:_dataTable
               [000014] -----------                                           \--*  LCL_VAR   ref    V00 this         

LocalAddressVisitor visiting statement:
STMT00004 ( 0x03A[E-] ... 0x077 )
               [000033] -ACXG------                         *  STOREIND  simd16 (copy)
               [000031] --CXG------                         +--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
               [000030] ---X------- this                    |  \--*  FIELD_ADDR byref  JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:_dataTable
               [000029] -----------                         |     \--*  LCL_VAR   ref    V00 this         
               [000032] -----------                         \--*  LCL_VAR   simd16<System.Numerics.Vector`1> V02 loc1         

LocalAddressVisitor visiting statement:
STMT00005 ( 0x04B[E-] ... ??? )
               [000041] DACXG------                         *  STORE_LCL_VAR long   V05 tmp2         
               [000037] --CXG------                         \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
               [000036] ---X------- this                       \--*  FIELD_ADDR byref  JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:_dataTable
               [000035] -----------                               \--*  LCL_VAR   ref    V00 this         

LocalAddressVisitor visiting statement:
STMT00006 ( ??? ... ??? )
               [000046] DACXG------                         *  STORE_LCL_VAR long   V06 tmp3         
               [000040] --CXG------                         \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
               [000039] ---X------- this                       \--*  FIELD_ADDR byref  JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:_dataTable
               [000038] -----------                               \--*  LCL_VAR   ref    V00 this         

LocalAddressVisitor visiting statement:
STMT00007 ( ??? ... ??? )
               [000049] --CXG------                         *  CALL      void   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:ValidateResult(ulong,ulong,ulong,System.String):this
               [000034] ----------- this                    +--*  LCL_VAR   ref    V00 this         
               [000042] ----------- arg1                    +--*  LCL_VAR   long   V05 tmp2         
               [000047] ----------- arg2                    +--*  LCL_VAR   long   V06 tmp3         
               [000045] --CXG------ arg3                    +--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
               [000044] ---X------- this                    |  \--*  FIELD_ADDR byref  JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:_dataTable
               [000043] -----------                         |     \--*  LCL_VAR   ref    V00 this         
               [000048] ----------- arg4                    \--*  CNS_STR   ref   <string constant>

LocalAddressVisitor visiting statement:
STMT00008 ( 0x077[E-] ... ??? )
               [000050] -----------                         *  RETURN    void  


*************** Finishing PHASE Morph - Structs/AddrExp [no changes]

*************** Starting PHASE Early liveness

*************** Finishing PHASE Early liveness [no changes]

*************** Starting PHASE Forward Substitution

*************** Finishing PHASE Forward Substitution [no changes]

*************** Starting PHASE Physical promotion

*************** Finishing PHASE Physical promotion [no changes]

*************** Starting PHASE Identify candidates for implicit byref copy omission

*************** Finishing PHASE Identify candidates for implicit byref copy omission [no changes]

*************** Starting PHASE Morph - ByRefs

*************** Finishing PHASE Morph - ByRefs [no changes]

*************** Starting PHASE Morph - Global
compEnregLocals() is false, setting doNotEnreg flag for all locals.
Local V00 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set

Local V01 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set

Local V02 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set

Local V03 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set

Local V04 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set

Local V05 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set

Local V06 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set

Morphing BB01

fgMorphTree BB01, STMT00000 (before)
               [000001] --C-G------                         *  CALL      void   TestLibrary.TestFramework:BeginScenario(System.String)
               [000000] ----------- arg0                    \--*  CNS_STR   ref   <string constant>
Initializing arg info for 1.CALL:
Argument 0 ABI info: [00..08) reg x0
Args for call [000001] CALL after AddFinalArgsAndDetermineABIInfo:
CallArg[[000000].CNS_STR ref (By value), 1 reg: x0]

Morphing args for 1.CALL:

Sorting the arguments:
Deferred argument ('x0'):
               [000051] H----+-----                         *  CNS_INT(h) ref     'RunBasicScenario_Load'
Moved to late list

Register placement order:    x0 
Args for [000001].CALL after fgMorphArgs:
CallArg[[000051].CNS_INT ref (By value), 1 reg: x0, isLate, processed]
OutgoingArgsStackSize is 0


fgMorphTree BB01, STMT00000 (after)
               [000001] --CXG+-----                         *  CALL      void   TestLibrary.TestFramework:BeginScenario(System.String)
               [000051] H----+----- arg0 in x0              \--*  CNS_INT(h) ref     'RunBasicScenario_Load'

fgMorphTree BB01, STMT00001 (before)
               [000005] DA---------                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V01 loc0         
               [000004] -----------                         \--*  HWINTRINSIC simd16 int ConvertMaskToVector
               [000003] -----------                            \--*  HWINTRINSIC mask   int CreateTrueMaskInt32
               [000002] -----------                               \--*  CNS_INT   int    31
MorphCopyBlock:
PrepareDst for [000005] have found a local var V01.
block store to morph:
               [000005] DA---------                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V01 loc0         
               [000004] -----+-----                         \--*  HWINTRINSIC simd16 int ConvertMaskToVector
               [000003] -----+-----                            \--*  HWINTRINSIC mask   int CreateTrueMaskInt32
               [000002] -----+-N---                               \--*  CNS_INT   int    31
 src is not an L-value this requires a CopyBlock.
MorphCopyBlock (after):
               [000005] DA---------                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V01 loc0         
               [000004] -----+-----                         \--*  HWINTRINSIC simd16 int ConvertMaskToVector
               [000003] -----+-----                            \--*  HWINTRINSIC mask   int CreateTrueMaskInt32
               [000002] -----+-N---                               \--*  CNS_INT   int    31

fgMorphTree BB01, STMT00002 (before)
               [000017] DACXG------                         *  STORE_LCL_VAR simd16 V04 tmp1         
               [000010] --CXG------                         \--*  HWINTRINSIC simd16 int LoadVector
               [000012] -----------                            +--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000011] -----------                            |  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000006] -----------                            |  \--*  LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0         
               [000009] --CXG------                            \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
               [000008] ---X------- this                          \--*  FIELD_ADDR byref  JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:_dataTable
               [000007] -----------                                  \--*  LCL_VAR   ref    V00 this         
Initializing arg info for 9.CALL:
Argument 0 ABI info: [00..08) reg x0
Args for call [000009] CALL after AddFinalArgsAndDetermineABIInfo:
CallArg[[000008].FIELD_ADDR byref (By value), 1 reg: x0, wellKnown[ThisPointer]]

Morphing args for 9.CALL:
Before explicit null check morphing:
               [000008] ---X-------                         *  FIELD_ADDR byref  JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:_dataTable
               [000007] -----------                         \--*  LCL_VAR   ref    V00 this         
After adding explicit null check:
               [000057] ---X-O-----                         *  COMMA     byref 
               [000053] ---X-O-----                         +--*  NULLCHECK byte  
               [000052] -----------                         |  \--*  LCL_VAR   ref    V00 this         
               [000056] -----O-----                         \--*  ADD       byref 
               [000054] -----------                            +--*  LCL_VAR   ref    V00 this         
               [000055] -----------                            \--*  CNS_INT   long   80 Fseq[_dataTable]

Final value of Compiler::fgMorphFieldAddr after morphing:
               [000057] ---X-+-N---                         *  COMMA     byref 
               [000053] ---X-+-----                         +--*  NULLCHECK byte  
               [000052] -----+-----                         |  \--*  LCL_VAR   ref    V00 this         
               [000056] -----+-----                         \--*  ADD       byref 
               [000054] -----+-----                            +--*  LCL_VAR   ref    V00 this         
               [000055] -----+-----                            \--*  CNS_INT   long   80 Fseq[_dataTable]

Sorting the arguments:
Deferred argument ('x0'):
               [000057] ---X-+-N---                         *  COMMA     byref 
               [000053] ---X-+-----                         +--*  NULLCHECK byte  
               [000052] -----+-----                         |  \--*  LCL_VAR   ref    V00 this         
               [000056] -----+-----                         \--*  ADD       byref 
               [000054] -----+-----                            +--*  LCL_VAR   ref    V00 this         
               [000055] -----+-----                            \--*  CNS_INT   long   80 Fseq[_dataTable]
Moved to late list

Register placement order:    x0 
Args for [000009].CALL after fgMorphArgs:
CallArg[[000057].COMMA byref (By value), 1 reg: x0, isLate, processed, wellKnown[ThisPointer]]
OutgoingArgsStackSize is 0

MorphCopyBlock:
PrepareDst for [000017] have found a local var V04.
block store to morph:
               [000017] DACXGO-----                         *  STORE_LCL_VAR simd16 V04 tmp1         
               [000010] --CXG+-----                         \--*  HWINTRINSIC simd16 int LoadVector
               [000012] -----+-----                            +--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000011] -----+-----                            |  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000006] -----+-----                            |  \--*  LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0         
               [000009] --CXG+-----                            \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
               [000057] ---X-+-N--- this in x0                    \--*  COMMA     byref 
               [000053] ---X-+-----                                  +--*  NULLCHECK byte  
               [000052] -----+-----                                  |  \--*  LCL_VAR   ref    V00 this         
               [000056] -----+-----                                  \--*  ADD       byref 
               [000054] -----+-----                                     +--*  LCL_VAR   ref    V00 this         
               [000055] -----+-----                                     \--*  CNS_INT   long   80 Fseq[_dataTable]
 src is not an L-value this requires a CopyBlock.
MorphCopyBlock (after):
               [000017] DACXGO-----                         *  STORE_LCL_VAR simd16 V04 tmp1         
               [000010] --CXG+-----                         \--*  HWINTRINSIC simd16 int LoadVector
               [000012] -----+-----                            +--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000011] -----+-----                            |  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000006] -----+-----                            |  \--*  LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0         
               [000009] --CXG+-----                            \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
               [000057] ---X-+-N--- this in x0                    \--*  COMMA     byref 
               [000053] ---X-+-----                                  +--*  NULLCHECK byte  
               [000052] -----+-----                                  |  \--*  LCL_VAR   ref    V00 this         
               [000056] -----+-----                                  \--*  ADD       byref 
               [000054] -----+-----                                     +--*  LCL_VAR   ref    V00 this         
               [000055] -----+-----                                     \--*  CNS_INT   long   80 Fseq[_dataTable]

fgMorphTree BB01, STMT00002 (after)
               [000017] DACXG+-----                         *  STORE_LCL_VAR simd16 V04 tmp1         
               [000010] --CXG+-----                         \--*  HWINTRINSIC simd16 int LoadVector
               [000012] -----+-----                            +--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000011] -----+-----                            |  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000006] -----+-----                            |  \--*  LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0         
               [000009] --CXG+-----                            \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
               [000057] ---X-+-N--- this in x0                    \--*  COMMA     byref 
               [000053] ---X-+-----                                  +--*  NULLCHECK byte  
               [000052] -----+-----                                  |  \--*  LCL_VAR   ref    V00 this         
               [000056] -----+-----                                  \--*  ADD       byref 
               [000054] -----+-----                                     +--*  LCL_VAR   ref    V00 this         
               [000055] -----+-----                                     \--*  CNS_INT   long   80 Fseq[_dataTable]

fgMorphTree BB01, STMT00003 (before)
               [000028] DACXG------                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V02 loc1         
               [000027] --CXG------                         \--*  HWINTRINSIC simd16 int ConvertMaskToVector
               [000022] --CXG------                            \--*  HWINTRINSIC mask   int CreateBreakPropagateMask
               [000024] -----------                               +--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000023] -----------                               |  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000018] -----------                               |  \--*  LCL_VAR   simd16 V04 tmp1         
               [000026] --CXG------                               \--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000025] -----------                                  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000019] --CXG------                                  \--*  HWINTRINSIC simd16 int LoadVector
               [000021] -----------                                     +--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000020] -----------                                     |  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000013] -----------                                     |  \--*  LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0         
               [000016] --CXG------                                     \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
               [000015] ---X------- this                                   \--*  FIELD_ADDR byref  JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:_dataTable
               [000014] -----------                                           \--*  LCL_VAR   ref    V00 this         
Initializing arg info for 16.CALL:
Argument 0 ABI info: [00..08) reg x0
Args for call [000016] CALL after AddFinalArgsAndDetermineABIInfo:
CallArg[[000015].FIELD_ADDR byref (By value), 1 reg: x0, wellKnown[ThisPointer]]

Morphing args for 16.CALL:
Before explicit null check morphing:
               [000015] ---X-------                         *  FIELD_ADDR byref  JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:_dataTable
               [000014] -----------                         \--*  LCL_VAR   ref    V00 this         
After adding explicit null check:
               [000063] ---X-O-----                         *  COMMA     byref 
               [000059] ---X-O-----                         +--*  NULLCHECK byte  
               [000058] -----------                         |  \--*  LCL_VAR   ref    V00 this         
               [000062] -----O-----                         \--*  ADD       byref 
               [000060] -----------                            +--*  LCL_VAR   ref    V00 this         
               [000061] -----------                            \--*  CNS_INT   long   80 Fseq[_dataTable]

Final value of Compiler::fgMorphFieldAddr after morphing:
               [000063] ---X-+-N---                         *  COMMA     byref 
               [000059] ---X-+-----                         +--*  NULLCHECK byte  
               [000058] -----+-----                         |  \--*  LCL_VAR   ref    V00 this         
               [000062] -----+-----                         \--*  ADD       byref 
               [000060] -----+-----                            +--*  LCL_VAR   ref    V00 this         
               [000061] -----+-----                            \--*  CNS_INT   long   80 Fseq[_dataTable]

Sorting the arguments:
Deferred argument ('x0'):
               [000063] ---X-+-N---                         *  COMMA     byref 
               [000059] ---X-+-----                         +--*  NULLCHECK byte  
               [000058] -----+-----                         |  \--*  LCL_VAR   ref    V00 this         
               [000062] -----+-----                         \--*  ADD       byref 
               [000060] -----+-----                            +--*  LCL_VAR   ref    V00 this         
               [000061] -----+-----                            \--*  CNS_INT   long   80 Fseq[_dataTable]
Moved to late list

Register placement order:    x0 
Args for [000016].CALL after fgMorphArgs:
CallArg[[000063].COMMA byref (By value), 1 reg: x0, isLate, processed, wellKnown[ThisPointer]]
OutgoingArgsStackSize is 0

MorphCopyBlock:
PrepareDst for [000028] have found a local var V02.
block store to morph:
               [000028] DACXGO-----                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V02 loc1         
               [000027] --CXG+-----                         \--*  HWINTRINSIC simd16 int ConvertMaskToVector
               [000022] --CXG+-----                            \--*  HWINTRINSIC mask   int CreateBreakPropagateMask
               [000024] -----+-----                               +--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000023] -----+-----                               |  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000018] -----+-----                               |  \--*  LCL_VAR   simd16 V04 tmp1         
               [000026] --CXG+-----                               \--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000025] -----+-----                                  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000019] --CXG+-----                                  \--*  HWINTRINSIC simd16 int LoadVector
               [000021] -----+-----                                     +--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000020] -----+-----                                     |  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000013] -----+-----                                     |  \--*  LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0         
               [000016] --CXG+-----                                     \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
               [000063] ---X-+-N--- this in x0                             \--*  COMMA     byref 
               [000059] ---X-+-----                                           +--*  NULLCHECK byte  
               [000058] -----+-----                                           |  \--*  LCL_VAR   ref    V00 this         
               [000062] -----+-----                                           \--*  ADD       byref 
               [000060] -----+-----                                              +--*  LCL_VAR   ref    V00 this         
               [000061] -----+-----                                              \--*  CNS_INT   long   80 Fseq[_dataTable]
 src is not an L-value this requires a CopyBlock.
MorphCopyBlock (after):
               [000028] DACXGO-----                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V02 loc1         
               [000027] --CXG+-----                         \--*  HWINTRINSIC simd16 int ConvertMaskToVector
               [000022] --CXG+-----                            \--*  HWINTRINSIC mask   int CreateBreakPropagateMask
               [000024] -----+-----                               +--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000023] -----+-----                               |  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000018] -----+-----                               |  \--*  LCL_VAR   simd16 V04 tmp1         
               [000026] --CXG+-----                               \--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000025] -----+-----                                  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000019] --CXG+-----                                  \--*  HWINTRINSIC simd16 int LoadVector
               [000021] -----+-----                                     +--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000020] -----+-----                                     |  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000013] -----+-----                                     |  \--*  LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0         
               [000016] --CXG+-----                                     \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
               [000063] ---X-+-N--- this in x0                             \--*  COMMA     byref 
               [000059] ---X-+-----                                           +--*  NULLCHECK byte  
               [000058] -----+-----                                           |  \--*  LCL_VAR   ref    V00 this         
               [000062] -----+-----                                           \--*  ADD       byref 
               [000060] -----+-----                                              +--*  LCL_VAR   ref    V00 this         
               [000061] -----+-----                                              \--*  CNS_INT   long   80 Fseq[_dataTable]

fgMorphTree BB01, STMT00003 (after)
               [000028] DACXG+-----                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V02 loc1         
               [000027] --CXG+-----                         \--*  HWINTRINSIC simd16 int ConvertMaskToVector
               [000022] --CXG+-----                            \--*  HWINTRINSIC mask   int CreateBreakPropagateMask
               [000024] -----+-----                               +--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000023] -----+-----                               |  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000018] -----+-----                               |  \--*  LCL_VAR   simd16 V04 tmp1         
               [000026] --CXG+-----                               \--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000025] -----+-----                                  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000019] --CXG+-----                                  \--*  HWINTRINSIC simd16 int LoadVector
               [000021] -----+-----                                     +--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000020] -----+-----                                     |  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000013] -----+-----                                     |  \--*  LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0         
               [000016] --CXG+-----                                     \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
               [000063] ---X-+-N--- this in x0                             \--*  COMMA     byref 
               [000059] ---X-+-----                                           +--*  NULLCHECK byte  
               [000058] -----+-----                                           |  \--*  LCL_VAR   ref    V00 this         
               [000062] -----+-----                                           \--*  ADD       byref 
               [000060] -----+-----                                              +--*  LCL_VAR   ref    V00 this         
               [000061] -----+-----                                              \--*  CNS_INT   long   80 Fseq[_dataTable]

fgMorphTree BB01, STMT00004 (before)
               [000033] -ACXG------                         *  STOREIND  simd16 (copy)
               [000031] --CXG------                         +--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
               [000030] ---X------- this                    |  \--*  FIELD_ADDR byref  JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:_dataTable
               [000029] -----------                         |     \--*  LCL_VAR   ref    V00 this         
               [000032] -----------                         \--*  LCL_VAR   simd16<System.Numerics.Vector`1> V02 loc1         
Initializing arg info for 31.CALL:
Argument 0 ABI info: [00..08) reg x0
Args for call [000031] CALL after AddFinalArgsAndDetermineABIInfo:
CallArg[[000030].FIELD_ADDR byref (By value), 1 reg: x0, wellKnown[ThisPointer]]

Morphing args for 31.CALL:
Before explicit null check morphing:
               [000030] ---X-------                         *  FIELD_ADDR byref  JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:_dataTable
               [000029] -----------                         \--*  LCL_VAR   ref    V00 this         
After adding explicit null check:
               [000069] ---X-O-----                         *  COMMA     byref 
               [000065] ---X-O-----                         +--*  NULLCHECK byte  
               [000064] -----------                         |  \--*  LCL_VAR   ref    V00 this         
               [000068] -----O-----                         \--*  ADD       byref 
               [000066] -----------                            +--*  LCL_VAR   ref    V00 this         
               [000067] -----------                            \--*  CNS_INT   long   80 Fseq[_dataTable]

Final value of Compiler::fgMorphFieldAddr after morphing:
               [000069] ---X-+-N---                         *  COMMA     byref 
               [000065] ---X-+-----                         +--*  NULLCHECK byte  
               [000064] -----+-----                         |  \--*  LCL_VAR   ref    V00 this         
               [000068] -----+-----                         \--*  ADD       byref 
               [000066] -----+-----                            +--*  LCL_VAR   ref    V00 this         
               [000067] -----+-----                            \--*  CNS_INT   long   80 Fseq[_dataTable]

Sorting the arguments:
Deferred argument ('x0'):
               [000069] ---X-+-N---                         *  COMMA     byref 
               [000065] ---X-+-----                         +--*  NULLCHECK byte  
               [000064] -----+-----                         |  \--*  LCL_VAR   ref    V00 this         
               [000068] -----+-----                         \--*  ADD       byref 
               [000066] -----+-----                            +--*  LCL_VAR   ref    V00 this         
               [000067] -----+-----                            \--*  CNS_INT   long   80 Fseq[_dataTable]
Moved to late list

Register placement order:    x0 
Args for [000031].CALL after fgMorphArgs:
CallArg[[000069].COMMA byref (By value), 1 reg: x0, isLate, processed, wellKnown[ThisPointer]]
OutgoingArgsStackSize is 0

MorphCopyBlock:
PrepareDst for [000033] have not found a local var.
block store to morph:
               [000033] -ACXGO-----                         *  STOREIND  simd16 (copy)
               [000031] --CXG+-----                         +--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
               [000069] ---X-+-N--- this in x0              |  \--*  COMMA     byref 
               [000065] ---X-+-----                         |     +--*  NULLCHECK byte  
               [000064] -----+-----                         |     |  \--*  LCL_VAR   ref    V00 this         
               [000068] -----+-----                         |     \--*  ADD       byref 
               [000066] -----+-----                         |        +--*  LCL_VAR   ref    V00 this         
               [000067] -----+-----                         |        \--*  CNS_INT   long   80 Fseq[_dataTable]
               [000032] -----+-----                         \--*  LCL_VAR   simd16<System.Numerics.Vector`1> V02 loc1         
 with no promoted structs this requires a CopyBlock.
MorphCopyBlock (after):
               [000033] -ACXGO-----                         *  STOREIND  simd16 (copy)
               [000031] --CXG+-----                         +--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
               [000069] ---X-+-N--- this in x0              |  \--*  COMMA     byref 
               [000065] ---X-+-----                         |     +--*  NULLCHECK byte  
               [000064] -----+-----                         |     |  \--*  LCL_VAR   ref    V00 this         
               [000068] -----+-----                         |     \--*  ADD       byref 
               [000066] -----+-----                         |        +--*  LCL_VAR   ref    V00 this         
               [000067] -----+-----                         |        \--*  CNS_INT   long   80 Fseq[_dataTable]
               [000032] -----+-----                         \--*  LCL_VAR   simd16<System.Numerics.Vector`1> V02 loc1         

fgMorphTree BB01, STMT00004 (after)
               [000033] -ACXG+-----                         *  STOREIND  simd16 (copy)
               [000031] --CXG+-----                         +--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
               [000069] ---X-+-N--- this in x0              |  \--*  COMMA     byref 
               [000065] ---X-+-----                         |     +--*  NULLCHECK byte  
               [000064] -----+-----                         |     |  \--*  LCL_VAR   ref    V00 this         
               [000068] -----+-----                         |     \--*  ADD       byref 
               [000066] -----+-----                         |        +--*  LCL_VAR   ref    V00 this         
               [000067] -----+-----                         |        \--*  CNS_INT   long   80 Fseq[_dataTable]
               [000032] -----+-----                         \--*  LCL_VAR   simd16<System.Numerics.Vector`1> V02 loc1         

fgMorphTree BB01, STMT00005 (before)
               [000041] DACXG------                         *  STORE_LCL_VAR long   V05 tmp2         
               [000037] --CXG------                         \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
               [000036] ---X------- this                       \--*  FIELD_ADDR byref  JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:_dataTable
               [000035] -----------                               \--*  LCL_VAR   ref    V00 this         
Initializing arg info for 37.CALL:
Argument 0 ABI info: [00..08) reg x0
Args for call [000037] CALL after AddFinalArgsAndDetermineABIInfo:
CallArg[[000036].FIELD_ADDR byref (By value), 1 reg: x0, wellKnown[ThisPointer]]

Morphing args for 37.CALL:
Before explicit null check morphing:
               [000036] ---X-------                         *  FIELD_ADDR byref  JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:_dataTable
               [000035] -----------                         \--*  LCL_VAR   ref    V00 this         
After adding explicit null check:
               [000075] ---X-O-----                         *  COMMA     byref 
               [000071] ---X-O-----                         +--*  NULLCHECK byte  
               [000070] -----------                         |  \--*  LCL_VAR   ref    V00 this         
               [000074] -----O-----                         \--*  ADD       byref 
               [000072] -----------                            +--*  LCL_VAR   ref    V00 this         
               [000073] -----------                            \--*  CNS_INT   long   80 Fseq[_dataTable]

Final value of Compiler::fgMorphFieldAddr after morphing:
               [000075] ---X-+-N---                         *  COMMA     byref 
               [000071] ---X-+-----                         +--*  NULLCHECK byte  
               [000070] -----+-----                         |  \--*  LCL_VAR   ref    V00 this         
               [000074] -----+-----                         \--*  ADD       byref 
               [000072] -----+-----                            +--*  LCL_VAR   ref    V00 this         
               [000073] -----+-----                            \--*  CNS_INT   long   80 Fseq[_dataTable]

Sorting the arguments:
Deferred argument ('x0'):
               [000075] ---X-+-N---                         *  COMMA     byref 
               [000071] ---X-+-----                         +--*  NULLCHECK byte  
               [000070] -----+-----                         |  \--*  LCL_VAR   ref    V00 this         
               [000074] -----+-----                         \--*  ADD       byref 
               [000072] -----+-----                            +--*  LCL_VAR   ref    V00 this         
               [000073] -----+-----                            \--*  CNS_INT   long   80 Fseq[_dataTable]
Moved to late list

Register placement order:    x0 
Args for [000037].CALL after fgMorphArgs:
CallArg[[000075].COMMA byref (By value), 1 reg: x0, isLate, processed, wellKnown[ThisPointer]]
OutgoingArgsStackSize is 0


fgMorphTree BB01, STMT00005 (after)
               [000041] DACXG+-----                         *  STORE_LCL_VAR long   V05 tmp2         
               [000037] --CXG+-----                         \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
               [000075] ---X-+-N--- this in x0                 \--*  COMMA     byref 
               [000071] ---X-+-----                               +--*  NULLCHECK byte  
               [000070] -----+-----                               |  \--*  LCL_VAR   ref    V00 this         
               [000074] -----+-----                               \--*  ADD       byref 
               [000072] -----+-----                                  +--*  LCL_VAR   ref    V00 this         
               [000073] -----+-----                                  \--*  CNS_INT   long   80 Fseq[_dataTable]

fgMorphTree BB01, STMT00006 (before)
               [000046] DACXG------                         *  STORE_LCL_VAR long   V06 tmp3         
               [000040] --CXG------                         \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
               [000039] ---X------- this                       \--*  FIELD_ADDR byref  JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:_dataTable
               [000038] -----------                               \--*  LCL_VAR   ref    V00 this         
Initializing arg info for 40.CALL:
Argument 0 ABI info: [00..08) reg x0
Args for call [000040] CALL after AddFinalArgsAndDetermineABIInfo:
CallArg[[000039].FIELD_ADDR byref (By value), 1 reg: x0, wellKnown[ThisPointer]]

Morphing args for 40.CALL:
Before explicit null check morphing:
               [000039] ---X-------                         *  FIELD_ADDR byref  JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:_dataTable
               [000038] -----------                         \--*  LCL_VAR   ref    V00 this         
After adding explicit null check:
               [000081] ---X-O-----                         *  COMMA     byref 
               [000077] ---X-O-----                         +--*  NULLCHECK byte  
               [000076] -----------                         |  \--*  LCL_VAR   ref    V00 this         
               [000080] -----O-----                         \--*  ADD       byref 
               [000078] -----------                            +--*  LCL_VAR   ref    V00 this         
               [000079] -----------                            \--*  CNS_INT   long   80 Fseq[_dataTable]

Final value of Compiler::fgMorphFieldAddr after morphing:
               [000081] ---X-+-N---                         *  COMMA     byref 
               [000077] ---X-+-----                         +--*  NULLCHECK byte  
               [000076] -----+-----                         |  \--*  LCL_VAR   ref    V00 this         
               [000080] -----+-----                         \--*  ADD       byref 
               [000078] -----+-----                            +--*  LCL_VAR   ref    V00 this         
               [000079] -----+-----                            \--*  CNS_INT   long   80 Fseq[_dataTable]

Sorting the arguments:
Deferred argument ('x0'):
               [000081] ---X-+-N---                         *  COMMA     byref 
               [000077] ---X-+-----                         +--*  NULLCHECK byte  
               [000076] -----+-----                         |  \--*  LCL_VAR   ref    V00 this         
               [000080] -----+-----                         \--*  ADD       byref 
               [000078] -----+-----                            +--*  LCL_VAR   ref    V00 this         
               [000079] -----+-----                            \--*  CNS_INT   long   80 Fseq[_dataTable]
Moved to late list

Register placement order:    x0 
Args for [000040].CALL after fgMorphArgs:
CallArg[[000081].COMMA byref (By value), 1 reg: x0, isLate, processed, wellKnown[ThisPointer]]
OutgoingArgsStackSize is 0


fgMorphTree BB01, STMT00006 (after)
               [000046] DACXG+-----                         *  STORE_LCL_VAR long   V06 tmp3         
               [000040] --CXG+-----                         \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
               [000081] ---X-+-N--- this in x0                 \--*  COMMA     byref 
               [000077] ---X-+-----                               +--*  NULLCHECK byte  
               [000076] -----+-----                               |  \--*  LCL_VAR   ref    V00 this         
               [000080] -----+-----                               \--*  ADD       byref 
               [000078] -----+-----                                  +--*  LCL_VAR   ref    V00 this         
               [000079] -----+-----                                  \--*  CNS_INT   long   80 Fseq[_dataTable]

fgMorphTree BB01, STMT00007 (before)
               [000049] --CXG------                         *  CALL      void   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:ValidateResult(ulong,ulong,ulong,System.String):this
               [000034] ----------- this                    +--*  LCL_VAR   ref    V00 this         
               [000042] ----------- arg1                    +--*  LCL_VAR   long   V05 tmp2         
               [000047] ----------- arg2                    +--*  LCL_VAR   long   V06 tmp3         
               [000045] --CXG------ arg3                    +--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
               [000044] ---X------- this                    |  \--*  FIELD_ADDR byref  JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:_dataTable
               [000043] -----------                         |     \--*  LCL_VAR   ref    V00 this         
               [000048] ----------- arg4                    \--*  CNS_STR   ref   <string constant>
Initializing arg info for 49.CALL:
Argument 0 ABI info: [00..08) reg x0
Argument 1 ABI info: [00..08) reg x1
Argument 2 ABI info: [00..08) reg x2
Argument 3 ABI info: [00..08) reg x3
Argument 4 ABI info: [00..08) reg x4
Args for call [000049] CALL after AddFinalArgsAndDetermineABIInfo:
CallArg[[000034].LCL_VAR ref (By value), 1 reg: x0, wellKnown[ThisPointer]]
CallArg[[000042].LCL_VAR long (By value), 1 reg: x1]
CallArg[[000047].LCL_VAR long (By value), 1 reg: x2]
CallArg[[000045].CALL long (By value), 1 reg: x3]
CallArg[[000048].CNS_STR ref (By value), 1 reg: x4]

Morphing args for 49.CALL:
Initializing arg info for 45.CALL:
Argument 0 ABI info: [00..08) reg x0
Args for call [000045] CALL after AddFinalArgsAndDetermineABIInfo:
CallArg[[000044].FIELD_ADDR byref (By value), 1 reg: x0, wellKnown[ThisPointer]]

Morphing args for 45.CALL:
Before explicit null check morphing:
               [000044] ---X-------                         *  FIELD_ADDR byref  JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:_dataTable
               [000043] -----------                         \--*  LCL_VAR   ref    V00 this         
After adding explicit null check:
               [000087] ---X-O-----                         *  COMMA     byref 
               [000083] ---X-O-----                         +--*  NULLCHECK byte  
               [000082] -----------                         |  \--*  LCL_VAR   ref    V00 this         
               [000086] -----O-----                         \--*  ADD       byref 
               [000084] -----------                            +--*  LCL_VAR   ref    V00 this         
               [000085] -----------                            \--*  CNS_INT   long   80 Fseq[_dataTable]

Final value of Compiler::fgMorphFieldAddr after morphing:
               [000087] ---X-+-N---                         *  COMMA     byref 
               [000083] ---X-+-----                         +--*  NULLCHECK byte  
               [000082] -----+-----                         |  \--*  LCL_VAR   ref    V00 this         
               [000086] -----+-----                         \--*  ADD       byref 
               [000084] -----+-----                            +--*  LCL_VAR   ref    V00 this         
               [000085] -----+-----                            \--*  CNS_INT   long   80 Fseq[_dataTable]

Sorting the arguments:
Deferred argument ('x0'):
               [000087] ---X-+-N---                         *  COMMA     byref 
               [000083] ---X-+-----                         +--*  NULLCHECK byte  
               [000082] -----+-----                         |  \--*  LCL_VAR   ref    V00 this         
               [000086] -----+-----                         \--*  ADD       byref 
               [000084] -----+-----                            +--*  LCL_VAR   ref    V00 this         
               [000085] -----+-----                            \--*  CNS_INT   long   80 Fseq[_dataTable]
Moved to late list

Register placement order:    x0 
Args for [000045].CALL after fgMorphArgs:
CallArg[[000087].COMMA byref (By value), 1 reg: x0, isLate, processed, wellKnown[ThisPointer]]
OutgoingArgsStackSize is 0


Sorting the arguments:
Argument with 'side effect'...
               [000045] --CXG+-----                         *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
               [000087] ---X-+-N--- this in x0              \--*  COMMA     byref 
               [000083] ---X-+-----                            +--*  NULLCHECK byte  
               [000082] -----+-----                            |  \--*  LCL_VAR   ref    V00 this         
               [000086] -----+-----                            \--*  ADD       byref 
               [000084] -----+-----                               +--*  LCL_VAR   ref    V00 this         
               [000085] -----+-----                               \--*  CNS_INT   long   80 Fseq[_dataTable]

lvaGrabTemp returning 7 (V07 tmp4) called for argument with side effect.

  Evaluate to a temp:
               [000089] DACXGO-----                         *  STORE_LCL_VAR long   V07 tmp4         
               [000045] --CXG+-----                         \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
               [000087] ---X-+-N--- this in x0                 \--*  COMMA     byref 
               [000083] ---X-+-----                               +--*  NULLCHECK byte  
               [000082] -----+-----                               |  \--*  LCL_VAR   ref    V00 this         
               [000086] -----+-----                               \--*  ADD       byref 
               [000084] -----+-----                                  +--*  LCL_VAR   ref    V00 this         
               [000085] -----+-----                                  \--*  CNS_INT   long   80 Fseq[_dataTable]
Deferred argument ('x1'):
               [000042] -----+-----                         *  LCL_VAR   long   V05 tmp2         
Moved to late list
Deferred argument ('x2'):
               [000047] -----+-----                         *  LCL_VAR   long   V06 tmp3         
Moved to late list
Deferred argument ('x0'):
               [000034] -----+-----                         *  LCL_VAR   ref    V00 this         
Moved to late list
Deferred argument ('x4'):
               [000088] H----+-----                         *  CNS_INT(h) ref     'RunBasicScenario_Load'
Moved to late list

Register placement order:    x3 x1 x2 x0 x4 
Args for [000049].CALL after fgMorphArgs:
CallArg[[000034].LCL_VAR ref (By value), 1 reg: x0, isLate, processed, wellKnown[ThisPointer]]
CallArg[[000042].LCL_VAR long (By value), 1 reg: x1, isLate, processed]
CallArg[[000047].LCL_VAR long (By value), 1 reg: x2, isLate, processed]
CallArg[[000090].LCL_VAR long (By value), 1 reg: x3, isLate, processed]
CallArg[[000088].CNS_INT ref (By value), 1 reg: x4, isLate, processed]
OutgoingArgsStackSize is 0


fgMorphTree BB01, STMT00007 (after)
               [000049] -ACXG+-----                         *  CALL      void   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:ValidateResult(ulong,ulong,ulong,System.String):this
               [000089] DACXGO----- arg3 setup              +--*  STORE_LCL_VAR long   V07 tmp4         
               [000045] --CXG+-----                         |  \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
               [000087] ---X-+-N--- this in x0              |     \--*  COMMA     byref 
               [000083] ---X-+-----                         |        +--*  NULLCHECK byte  
               [000082] -----+-----                         |        |  \--*  LCL_VAR   ref    V00 this         
               [000086] -----+-----                         |        \--*  ADD       byref 
               [000084] -----+-----                         |           +--*  LCL_VAR   ref    V00 this         
               [000085] -----+-----                         |           \--*  CNS_INT   long   80 Fseq[_dataTable]
               [000090] ----------- arg3 in x3              +--*  LCL_VAR   long   V07 tmp4         
               [000042] -----+----- arg1 in x1              +--*  LCL_VAR   long   V05 tmp2         
               [000047] -----+----- arg2 in x2              +--*  LCL_VAR   long   V06 tmp3         
               [000034] -----+----- this in x0              +--*  LCL_VAR   ref    V00 this         
               [000088] H----+----- arg4 in x4              \--*  CNS_INT(h) ref     'RunBasicScenario_Load'

fgMorphTree BB01, STMT00008 (before)
               [000050] -----------                         *  RETURN    void  

*************** Finishing PHASE Morph - Global
Trees after Morph - Global

---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   [IL range]   [jump]                            [EH region]        [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    [000..078)                           (return)                     i hascall gcsafe nullcheck
---------------------------------------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [0000] [000..078) (return), preds={} succs={}

***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x011 )
               [000001] --CXG+-----                         *  CALL      void   TestLibrary.TestFramework:BeginScenario(System.String)
               [000051] H----+----- arg0 in x0              \--*  CNS_INT(h) ref     'RunBasicScenario_Load'

***** BB01 [0000]
STMT00001 ( 0x00A[E-] ... ??? )
               [000005] DA---+-----                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V01 loc0         
               [000004] -----+-----                         \--*  HWINTRINSIC simd16 int ConvertMaskToVector
               [000003] -----+-----                            \--*  HWINTRINSIC mask   int CreateTrueMaskInt32
               [000002] -----+-N---                               \--*  CNS_INT   int    31

***** BB01 [0000]
STMT00002 ( 0x012[E-] ... 0x039 )
               [000017] DACXG+-----                         *  STORE_LCL_VAR simd16 V04 tmp1         
               [000010] --CXG+-----                         \--*  HWINTRINSIC simd16 int LoadVector
               [000012] -----+-----                            +--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000011] -----+-----                            |  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000006] -----+-----                            |  \--*  LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0         
               [000009] --CXG+-----                            \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
               [000057] ---X-+-N--- this in x0                    \--*  COMMA     byref 
               [000053] ---X-+-----                                  +--*  NULLCHECK byte  
               [000052] -----+-----                                  |  \--*  LCL_VAR   ref    V00 this         
               [000056] -----+-----                                  \--*  ADD       byref 
               [000054] -----+-----                                     +--*  LCL_VAR   ref    V00 this         
               [000055] -----+-----                                     \--*  CNS_INT   long   80 Fseq[_dataTable]

***** BB01 [0000]
STMT00003 ( ??? ... ??? )
               [000028] DACXG+-----                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V02 loc1         
               [000027] --CXG+-----                         \--*  HWINTRINSIC simd16 int ConvertMaskToVector
               [000022] --CXG+-----                            \--*  HWINTRINSIC mask   int CreateBreakPropagateMask
               [000024] -----+-----                               +--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000023] -----+-----                               |  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000018] -----+-----                               |  \--*  LCL_VAR   simd16 V04 tmp1         
               [000026] --CXG+-----                               \--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000025] -----+-----                                  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000019] --CXG+-----                                  \--*  HWINTRINSIC simd16 int LoadVector
               [000021] -----+-----                                     +--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000020] -----+-----                                     |  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000013] -----+-----                                     |  \--*  LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0         
               [000016] --CXG+-----                                     \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
               [000063] ---X-+-N--- this in x0                             \--*  COMMA     byref 
               [000059] ---X-+-----                                           +--*  NULLCHECK byte  
               [000058] -----+-----                                           |  \--*  LCL_VAR   ref    V00 this         
               [000062] -----+-----                                           \--*  ADD       byref 
               [000060] -----+-----                                              +--*  LCL_VAR   ref    V00 this         
               [000061] -----+-----                                              \--*  CNS_INT   long   80 Fseq[_dataTable]

***** BB01 [0000]
STMT00004 ( 0x03A[E-] ... 0x077 )
               [000033] -ACXG+-----                         *  STOREIND  simd16 (copy)
               [000031] --CXG+-----                         +--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
               [000069] ---X-+-N--- this in x0              |  \--*  COMMA     byref 
               [000065] ---X-+-----                         |     +--*  NULLCHECK byte  
               [000064] -----+-----                         |     |  \--*  LCL_VAR   ref    V00 this         
               [000068] -----+-----                         |     \--*  ADD       byref 
               [000066] -----+-----                         |        +--*  LCL_VAR   ref    V00 this         
               [000067] -----+-----                         |        \--*  CNS_INT   long   80 Fseq[_dataTable]
               [000032] -----+-----                         \--*  LCL_VAR   simd16<System.Numerics.Vector`1> V02 loc1         

***** BB01 [0000]
STMT00005 ( 0x04B[E-] ... ??? )
               [000041] DACXG+-----                         *  STORE_LCL_VAR long   V05 tmp2         
               [000037] --CXG+-----                         \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
               [000075] ---X-+-N--- this in x0                 \--*  COMMA     byref 
               [000071] ---X-+-----                               +--*  NULLCHECK byte  
               [000070] -----+-----                               |  \--*  LCL_VAR   ref    V00 this         
               [000074] -----+-----                               \--*  ADD       byref 
               [000072] -----+-----                                  +--*  LCL_VAR   ref    V00 this         
               [000073] -----+-----                                  \--*  CNS_INT   long   80 Fseq[_dataTable]

***** BB01 [0000]
STMT00006 ( ??? ... ??? )
               [000046] DACXG+-----                         *  STORE_LCL_VAR long   V06 tmp3         
               [000040] --CXG+-----                         \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
               [000081] ---X-+-N--- this in x0                 \--*  COMMA     byref 
               [000077] ---X-+-----                               +--*  NULLCHECK byte  
               [000076] -----+-----                               |  \--*  LCL_VAR   ref    V00 this         
               [000080] -----+-----                               \--*  ADD       byref 
               [000078] -----+-----                                  +--*  LCL_VAR   ref    V00 this         
               [000079] -----+-----                                  \--*  CNS_INT   long   80 Fseq[_dataTable]

***** BB01 [0000]
STMT00007 ( ??? ... ??? )
               [000049] -ACXG+-----                         *  CALL      void   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:ValidateResult(ulong,ulong,ulong,System.String):this
               [000089] DACXGO----- arg3 setup              +--*  STORE_LCL_VAR long   V07 tmp4         
               [000045] --CXG+-----                         |  \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
               [000087] ---X-+-N--- this in x0              |     \--*  COMMA     byref 
               [000083] ---X-+-----                         |        +--*  NULLCHECK byte  
               [000082] -----+-----                         |        |  \--*  LCL_VAR   ref    V00 this         
               [000086] -----+-----                         |        \--*  ADD       byref 
               [000084] -----+-----                         |           +--*  LCL_VAR   ref    V00 this         
               [000085] -----+-----                         |           \--*  CNS_INT   long   80 Fseq[_dataTable]
               [000090] ----------- arg3 in x3              +--*  LCL_VAR   long   V07 tmp4         
               [000042] -----+----- arg1 in x1              +--*  LCL_VAR   long   V05 tmp2         
               [000047] -----+----- arg2 in x2              +--*  LCL_VAR   long   V06 tmp3         
               [000034] -----+----- this in x0              +--*  LCL_VAR   ref    V00 this         
               [000088] H----+----- arg4 in x4              \--*  CNS_INT(h) ref     'RunBasicScenario_Load'

***** BB01 [0000]
STMT00008 ( 0x077[E-] ... ??? )
               [000050] -----+-----                         *  RETURN    void  

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]

*************** Starting PHASE Post-Morph

*************** In fgMarkDemotedImplicitByRefArgs()

*************** Finishing PHASE Post-Morph
Trees after Post-Morph

---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   [IL range]   [jump]                            [EH region]        [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    [000..078)                           (return)                     i hascall gcsafe nullcheck
---------------------------------------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [0000] [000..078) (return), preds={} succs={}

***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x011 )
               [000001] --CXG+-----                         *  CALL      void   TestLibrary.TestFramework:BeginScenario(System.String)
               [000051] H----+----- arg0 in x0              \--*  CNS_INT(h) ref     'RunBasicScenario_Load'

***** BB01 [0000]
STMT00001 ( 0x00A[E-] ... ??? )
               [000005] DA---+-----                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V01 loc0         
               [000004] -----+-----                         \--*  HWINTRINSIC simd16 int ConvertMaskToVector
               [000003] -----+-----                            \--*  HWINTRINSIC mask   int CreateTrueMaskInt32
               [000002] -----+-N---                               \--*  CNS_INT   int    31

***** BB01 [0000]
STMT00002 ( 0x012[E-] ... 0x039 )
               [000017] DACXG+-----                         *  STORE_LCL_VAR simd16 V04 tmp1         
               [000010] --CXG+-----                         \--*  HWINTRINSIC simd16 int LoadVector
               [000012] -----+-----                            +--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000011] -----+-----                            |  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000006] -----+-----                            |  \--*  LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0         
               [000009] --CXG+-----                            \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
               [000057] ---X-+-N--- this in x0                    \--*  COMMA     byref 
               [000053] ---X-+-----                                  +--*  NULLCHECK byte  
               [000052] -----+-----                                  |  \--*  LCL_VAR   ref    V00 this         
               [000056] -----+-----                                  \--*  ADD       byref 
               [000054] -----+-----                                     +--*  LCL_VAR   ref    V00 this         
               [000055] -----+-----                                     \--*  CNS_INT   long   80 Fseq[_dataTable]

***** BB01 [0000]
STMT00003 ( ??? ... ??? )
               [000028] DACXG+-----                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V02 loc1         
               [000027] --CXG+-----                         \--*  HWINTRINSIC simd16 int ConvertMaskToVector
               [000022] --CXG+-----                            \--*  HWINTRINSIC mask   int CreateBreakPropagateMask
               [000024] -----+-----                               +--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000023] -----+-----                               |  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000018] -----+-----                               |  \--*  LCL_VAR   simd16 V04 tmp1         
               [000026] --CXG+-----                               \--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000025] -----+-----                                  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000019] --CXG+-----                                  \--*  HWINTRINSIC simd16 int LoadVector
               [000021] -----+-----                                     +--*  HWINTRINSIC mask   int ConvertVectorToMask
               [000020] -----+-----                                     |  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
               [000013] -----+-----                                     |  \--*  LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0         
               [000016] --CXG+-----                                     \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
               [000063] ---X-+-N--- this in x0                             \--*  COMMA     byref 
               [000059] ---X-+-----                                           +--*  NULLCHECK byte  
               [000058] -----+-----                                           |  \--*  LCL_VAR   ref    V00 this         
               [000062] -----+-----                                           \--*  ADD       byref 
               [000060] -----+-----                                              +--*  LCL_VAR   ref    V00 this         
               [000061] -----+-----                                              \--*  CNS_INT   long   80 Fseq[_dataTable]

***** BB01 [0000]
STMT00004 ( 0x03A[E-] ... 0x077 )
               [000033] -ACXG+-----                         *  STOREIND  simd16 (copy)
               [000031] --CXG+-----                         +--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
               [000069] ---X-+-N--- this in x0              |  \--*  COMMA     byref 
               [000065] ---X-+-----                         |     +--*  NULLCHECK byte  
               [000064] -----+-----                         |     |  \--*  LCL_VAR   ref    V00 this         
               [000068] -----+-----                         |     \--*  ADD       byref 
               [000066] -----+-----                         |        +--*  LCL_VAR   ref    V00 this         
               [000067] -----+-----                         |        \--*  CNS_INT   long   80 Fseq[_dataTable]
               [000032] -----+-----                         \--*  LCL_VAR   simd16<System.Numerics.Vector`1> V02 loc1         

***** BB01 [0000]
STMT00005 ( 0x04B[E-] ... ??? )
               [000041] DACXG+-----                         *  STORE_LCL_VAR long   V05 tmp2         
               [000037] --CXG+-----                         \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
               [000075] ---X-+-N--- this in x0                 \--*  COMMA     byref 
               [000071] ---X-+-----                               +--*  NULLCHECK byte  
               [000070] -----+-----                               |  \--*  LCL_VAR   ref    V00 this         
               [000074] -----+-----                               \--*  ADD       byref 
               [000072] -----+-----                                  +--*  LCL_VAR   ref    V00 this         
               [000073] -----+-----                                  \--*  CNS_INT   long   80 Fseq[_dataTable]

***** BB01 [0000]
STMT00006 ( ??? ... ??? )
               [000046] DACXG+-----                         *  STORE_LCL_VAR long   V06 tmp3         
               [000040] --CXG+-----                         \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
               [000081] ---X-+-N--- this in x0                 \--*  COMMA     byref 
               [000077] ---X-+-----                               +--*  NULLCHECK byte  
               [000076] -----+-----                               |  \--*  LCL_VAR   ref    V00 this         
               [000080] -----+-----                               \--*  ADD       byref 
               [000078] -----+-----                                  +--*  LCL_VAR   ref    V00 this         
               [000079] -----+-----                                  \--*  CNS_INT   long   80 Fseq[_dataTable]

***** BB01 [0000]
STMT00007 ( ??? ... ??? )
               [000049] -ACXG+-----                         *  CALL      void   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:ValidateResult(ulong,ulong,ulong,System.String):this
               [000089] DACXGO----- arg3 setup              +--*  STORE_LCL_VAR long   V07 tmp4         
               [000045] --CXG+-----                         |  \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
               [000087] ---X-+-N--- this in x0              |     \--*  COMMA     byref 
               [000083] ---X-+-----                         |        +--*  NULLCHECK byte  
               [000082] -----+-----                         |        |  \--*  LCL_VAR   ref    V00 this         
               [000086] -----+-----                         |        \--*  ADD       byref 
               [000084] -----+-----                         |           +--*  LCL_VAR   ref    V00 this         
               [000085] -----+-----                         |           \--*  CNS_INT   long   80 Fseq[_dataTable]
               [000090] ----------- arg3 in x3              +--*  LCL_VAR   long   V07 tmp4         
               [000042] -----+----- arg1 in x1              +--*  LCL_VAR   long   V05 tmp2         
               [000047] -----+----- arg2 in x2              +--*  LCL_VAR   long   V06 tmp3         
               [000034] -----+----- this in x0              +--*  LCL_VAR   ref    V00 this         
               [000088] H----+----- arg4 in x4              \--*  CNS_INT(h) ref     'RunBasicScenario_Load'

***** BB01 [0000]
STMT00008 ( 0x077[E-] ... ??? )
               [000050] -----+-----                         *  RETURN    void  

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]

*************** Starting PHASE GS Cookie
No GS security needed

*************** Finishing PHASE GS Cookie [no changes]

*************** Starting PHASE Compute block weights

---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   [IL range]   [jump]                            [EH region]        [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    [000..078)                           (return)                     i hascall gcsafe nullcheck
---------------------------------------------------------------------------------------------------------------------------------------------------------------------

 -- no profile data, so using default called count

*************** Finishing PHASE Compute block weights [no changes]

*************** Starting PHASE Create EH funclets

*************** Finishing PHASE Create EH funclets [no changes]

*************** Starting PHASE Morph array ops
No multi-dimensional array references in the function

*************** Finishing PHASE Morph array ops [no changes]

*************** Starting PHASE Mark local vars

*************** In lvaMarkLocalVars()
*** lvaComputeRefCounts ***

*************** Finishing PHASE Mark local vars [no changes]

*************** Starting PHASE Find oper order
*************** In fgFindOperOrder()

*************** Finishing PHASE Find oper order
Trees after Find oper order

---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   [IL range]   [jump]                            [EH region]        [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    [000..078)                           (return)                     i hascall gcsafe nullcheck
---------------------------------------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [0000] [000..078) (return), preds={} succs={}

***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x011 )
     ( 17, 15) [000001] --CXG------                         *  CALL      void   TestLibrary.TestFramework:BeginScenario(System.String)
     (  3, 12) [000051] H---------- arg0 in x0              \--*  CNS_INT(h) ref     'RunBasicScenario_Load'

***** BB01 [0000]
STMT00001 ( 0x00A[E-] ... ??? )
     (  7,  7) [000005] DA---------                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V01 loc0         
     (  3,  4) [000004] -----------                         \--*  HWINTRINSIC simd16 int ConvertMaskToVector
     (  2,  3) [000003] -----------                            \--*  HWINTRINSIC mask   int CreateTrueMaskInt32
     (  1,  2) [000002] -------N---                               \--*  CNS_INT   int    31

***** BB01 [0000]
STMT00002 ( 0x012[E-] ... 0x039 )
     ( 33, 19) [000017] DACXGO-----                         *  STORE_LCL_VAR simd16 V04 tmp1         
     ( 29, 16) [000010] --CXGO--R--                         \--*  HWINTRINSIC simd16 int LoadVector
     (  5,  4) [000012] --------R--                            +--*  HWINTRINSIC mask   int ConvertVectorToMask
     (  1,  1) [000011] -----------                            |  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
     (  3,  2) [000006] -----------                            |  \--*  LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0         
     ( 23, 11) [000009] --CXGO-----                            \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
     (  9,  8) [000057] ---X-O-N--- this in x0                    \--*  COMMA     byref 
     (  4,  3) [000053] ---X-O-----                                  +--*  NULLCHECK byte  
     (  3,  2) [000052] -----------                                  |  \--*  LCL_VAR   ref    V00 this         
     (  5,  5) [000056] -----O-----                                  \--*  ADD       byref 
     (  3,  2) [000054] -----------                                     +--*  LCL_VAR   ref    V00 this         
     (  1,  2) [000055] -----------                                     \--*  CNS_INT   long   80 Fseq[_dataTable]

***** BB01 [0000]
STMT00003 ( ??? ... ??? )
     ( 42, 27) [000028] DACXGO-----                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V02 loc1         
     ( 38, 24) [000027] --CXGO-----                         \--*  HWINTRINSIC simd16 int ConvertMaskToVector
     ( 37, 23) [000022] --CXGO--R--                            \--*  HWINTRINSIC mask   int CreateBreakPropagateMask
     (  5,  4) [000024] --------R--                               +--*  HWINTRINSIC mask   int ConvertVectorToMask
     (  1,  1) [000023] -----------                               |  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
     (  3,  2) [000018] -----------                               |  \--*  LCL_VAR   simd16 V04 tmp1         
     ( 31, 18) [000026] --CXGO--R--                               \--*  HWINTRINSIC mask   int ConvertVectorToMask
     (  1,  1) [000025] -----------                                  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
     ( 29, 16) [000019] --CXGO--R--                                  \--*  HWINTRINSIC simd16 int LoadVector
     (  5,  4) [000021] --------R--                                     +--*  HWINTRINSIC mask   int ConvertVectorToMask
     (  1,  1) [000020] -----------                                     |  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
     (  3,  2) [000013] -----------                                     |  \--*  LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0         
     ( 23, 11) [000016] --CXGO-----                                     \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
     (  9,  8) [000063] ---X-O-N--- this in x0                             \--*  COMMA     byref 
     (  4,  3) [000059] ---X-O-----                                           +--*  NULLCHECK byte  
     (  3,  2) [000058] -----------                                           |  \--*  LCL_VAR   ref    V00 this         
     (  5,  5) [000062] -----O-----                                           \--*  ADD       byref 
     (  3,  2) [000060] -----------                                              +--*  LCL_VAR   ref    V00 this         
     (  1,  2) [000061] -----------                                              \--*  CNS_INT   long   80 Fseq[_dataTable]

***** BB01 [0000]
STMT00004 ( 0x03A[E-] ... 0x077 )
     ( 30, 16) [000033] -ACXGO-----                         *  STOREIND  simd16 (copy)
     ( 23, 11) [000031] --CXGO-----                         +--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
     (  9,  8) [000069] ---X-O-N--- this in x0              |  \--*  COMMA     byref 
     (  4,  3) [000065] ---X-O-----                         |     +--*  NULLCHECK byte  
     (  3,  2) [000064] -----------                         |     |  \--*  LCL_VAR   ref    V00 this         
     (  5,  5) [000068] -----O-----                         |     \--*  ADD       byref 
     (  3,  2) [000066] -----------                         |        +--*  LCL_VAR   ref    V00 this         
     (  1,  2) [000067] -----------                         |        \--*  CNS_INT   long   80 Fseq[_dataTable]
     (  3,  2) [000032] -----------                         \--*  LCL_VAR   simd16<System.Numerics.Vector`1> V02 loc1         

***** BB01 [0000]
STMT00005 ( 0x04B[E-] ... ??? )
     ( 27, 14) [000041] DACXGO-----                         *  STORE_LCL_VAR long   V05 tmp2         
     ( 23, 11) [000037] --CXGO-----                         \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
     (  9,  8) [000075] ---X-O-N--- this in x0                 \--*  COMMA     byref 
     (  4,  3) [000071] ---X-O-----                               +--*  NULLCHECK byte  
     (  3,  2) [000070] -----------                               |  \--*  LCL_VAR   ref    V00 this         
     (  5,  5) [000074] -----O-----                               \--*  ADD       byref 
     (  3,  2) [000072] -----------                                  +--*  LCL_VAR   ref    V00 this         
     (  1,  2) [000073] -----------                                  \--*  CNS_INT   long   80 Fseq[_dataTable]

***** BB01 [0000]
STMT00006 ( ??? ... ??? )
     ( 27, 14) [000046] DACXGO-----                         *  STORE_LCL_VAR long   V06 tmp3         
     ( 23, 11) [000040] --CXGO-----                         \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
     (  9,  8) [000081] ---X-O-N--- this in x0                 \--*  COMMA     byref 
     (  4,  3) [000077] ---X-O-----                               +--*  NULLCHECK byte  
     (  3,  2) [000076] -----------                               |  \--*  LCL_VAR   ref    V00 this         
     (  5,  5) [000080] -----O-----                               \--*  ADD       byref 
     (  3,  2) [000078] -----------                                  +--*  LCL_VAR   ref    V00 this         
     (  1,  2) [000079] -----------                                  \--*  CNS_INT   long   80 Fseq[_dataTable]

***** BB01 [0000]
STMT00007 ( ??? ... ??? )
     ( 59, 42) [000049] -ACXGO-----                         *  CALL      void   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:ValidateResult(ulong,ulong,ulong,System.String):this
     ( 27, 14) [000089] DACXGO----- arg3 setup              +--*  STORE_LCL_VAR long   V07 tmp4         
     ( 23, 11) [000045] --CXGO-----                         |  \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
     (  9,  8) [000087] ---X-O-N--- this in x0              |     \--*  COMMA     byref 
     (  4,  3) [000083] ---X-O-----                         |        +--*  NULLCHECK byte  
     (  3,  2) [000082] -----------                         |        |  \--*  LCL_VAR   ref    V00 this         
     (  5,  5) [000086] -----O-----                         |        \--*  ADD       byref 
     (  3,  2) [000084] -----------                         |           +--*  LCL_VAR   ref    V00 this         
     (  1,  2) [000085] -----------                         |           \--*  CNS_INT   long   80 Fseq[_dataTable]
     (  3,  2) [000090] ----------- arg3 in x3              +--*  LCL_VAR   long   V07 tmp4         
     (  3,  2) [000042] ----------- arg1 in x1              +--*  LCL_VAR   long   V05 tmp2         
     (  3,  2) [000047] ----------- arg2 in x2              +--*  LCL_VAR   long   V06 tmp3         
     (  3,  2) [000034] ----------- this in x0              +--*  LCL_VAR   ref    V00 this         
     (  3, 12) [000088] H---------- arg4 in x4              \--*  CNS_INT(h) ref     'RunBasicScenario_Load'

***** BB01 [0000]
STMT00008 ( 0x077[E-] ... ??? )
     (  0,  0) [000050] -----------                         *  RETURN    void  

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]

*************** Starting PHASE Set block order
*************** In fgSetBlockOrder()
The biggest BB has   19 tree nodes

*************** Finishing PHASE Set block order
Trees after Set block order

---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   [IL range]   [jump]                            [EH region]        [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    [000..078)                           (return)                     i hascall gcsafe nullcheck
---------------------------------------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [0000] [000..078) (return), preds={} succs={}

***** BB01 [0000]
STMT00000 ( 0x000[E-] ... 0x011 )
N002 ( 17, 15) [000001] --CXG------                         *  CALL      void   TestLibrary.TestFramework:BeginScenario(System.String)
N001 (  3, 12) [000051] H---------- arg0 in x0              \--*  CNS_INT(h) ref     'RunBasicScenario_Load'

***** BB01 [0000]
STMT00001 ( 0x00A[E-] ... ??? )
N004 (  7,  7) [000005] DA---------                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V01 loc0         
N003 (  3,  4) [000004] -----------                         \--*  HWINTRINSIC simd16 int ConvertMaskToVector
N002 (  2,  3) [000003] -----------                            \--*  HWINTRINSIC mask   int CreateTrueMaskInt32
N001 (  1,  2) [000002] -------N---                               \--*  CNS_INT   int    31

***** BB01 [0000]
STMT00002 ( 0x012[E-] ... 0x039 )
N012 ( 33, 19) [000017] DACXGO-----                         *  STORE_LCL_VAR simd16 V04 tmp1         
N011 ( 29, 16) [000010] --CXGO--R--                         \--*  HWINTRINSIC simd16 int LoadVector
N010 (  5,  4) [000012] --------R--                            +--*  HWINTRINSIC mask   int ConvertVectorToMask
N009 (  1,  1) [000011] -----------                            |  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
N008 (  3,  2) [000006] -----------                            |  \--*  LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0         
N007 ( 23, 11) [000009] --CXGO-----                            \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
N006 (  9,  8) [000057] ---X-O-N--- this in x0                    \--*  COMMA     byref 
N002 (  4,  3) [000053] ---X-O-----                                  +--*  NULLCHECK byte  
N001 (  3,  2) [000052] -----------                                  |  \--*  LCL_VAR   ref    V00 this         
N005 (  5,  5) [000056] -----O-----                                  \--*  ADD       byref 
N003 (  3,  2) [000054] -----------                                     +--*  LCL_VAR   ref    V00 this         
N004 (  1,  2) [000055] -----------                                     \--*  CNS_INT   long   80 Fseq[_dataTable]

***** BB01 [0000]
STMT00003 ( ??? ... ??? )
N019 ( 42, 27) [000028] DACXGO-----                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V02 loc1         
N018 ( 38, 24) [000027] --CXGO-----                         \--*  HWINTRINSIC simd16 int ConvertMaskToVector
N017 ( 37, 23) [000022] --CXGO--R--                            \--*  HWINTRINSIC mask   int CreateBreakPropagateMask
N016 (  5,  4) [000024] --------R--                               +--*  HWINTRINSIC mask   int ConvertVectorToMask
N015 (  1,  1) [000023] -----------                               |  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
N014 (  3,  2) [000018] -----------                               |  \--*  LCL_VAR   simd16 V04 tmp1         
N013 ( 31, 18) [000026] --CXGO--R--                               \--*  HWINTRINSIC mask   int ConvertVectorToMask
N012 (  1,  1) [000025] -----------                                  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
N011 ( 29, 16) [000019] --CXGO--R--                                  \--*  HWINTRINSIC simd16 int LoadVector
N010 (  5,  4) [000021] --------R--                                     +--*  HWINTRINSIC mask   int ConvertVectorToMask
N009 (  1,  1) [000020] -----------                                     |  +--*  HWINTRINSIC mask   int CreateTrueMaskAll
N008 (  3,  2) [000013] -----------                                     |  \--*  LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0         
N007 ( 23, 11) [000016] --CXGO-----                                     \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
N006 (  9,  8) [000063] ---X-O-N--- this in x0                             \--*  COMMA     byref 
N002 (  4,  3) [000059] ---X-O-----                                           +--*  NULLCHECK byte  
N001 (  3,  2) [000058] -----------                                           |  \--*  LCL_VAR   ref    V00 this         
N005 (  5,  5) [000062] -----O-----                                           \--*  ADD       byref 
N003 (  3,  2) [000060] -----------                                              +--*  LCL_VAR   ref    V00 this         
N004 (  1,  2) [000061] -----------                                              \--*  CNS_INT   long   80 Fseq[_dataTable]

***** BB01 [0000]
STMT00004 ( 0x03A[E-] ... 0x077 )
N009 ( 30, 16) [000033] -ACXGO-----                         *  STOREIND  simd16 (copy)
N007 ( 23, 11) [000031] --CXGO-----                         +--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
N006 (  9,  8) [000069] ---X-O-N--- this in x0              |  \--*  COMMA     byref 
N002 (  4,  3) [000065] ---X-O-----                         |     +--*  NULLCHECK byte  
N001 (  3,  2) [000064] -----------                         |     |  \--*  LCL_VAR   ref    V00 this         
N005 (  5,  5) [000068] -----O-----                         |     \--*  ADD       byref 
N003 (  3,  2) [000066] -----------                         |        +--*  LCL_VAR   ref    V00 this         
N004 (  1,  2) [000067] -----------                         |        \--*  CNS_INT   long   80 Fseq[_dataTable]
N008 (  3,  2) [000032] -----------                         \--*  LCL_VAR   simd16<System.Numerics.Vector`1> V02 loc1         

***** BB01 [0000]
STMT00005 ( 0x04B[E-] ... ??? )
N008 ( 27, 14) [000041] DACXGO-----                         *  STORE_LCL_VAR long   V05 tmp2         
N007 ( 23, 11) [000037] --CXGO-----                         \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
N006 (  9,  8) [000075] ---X-O-N--- this in x0                 \--*  COMMA     byref 
N002 (  4,  3) [000071] ---X-O-----                               +--*  NULLCHECK byte  
N001 (  3,  2) [000070] -----------                               |  \--*  LCL_VAR   ref    V00 this         
N005 (  5,  5) [000074] -----O-----                               \--*  ADD       byref 
N003 (  3,  2) [000072] -----------                                  +--*  LCL_VAR   ref    V00 this         
N004 (  1,  2) [000073] -----------                                  \--*  CNS_INT   long   80 Fseq[_dataTable]

***** BB01 [0000]
STMT00006 ( ??? ... ??? )
N008 ( 27, 14) [000046] DACXGO-----                         *  STORE_LCL_VAR long   V06 tmp3         
N007 ( 23, 11) [000040] --CXGO-----                         \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
N006 (  9,  8) [000081] ---X-O-N--- this in x0                 \--*  COMMA     byref 
N002 (  4,  3) [000077] ---X-O-----                               +--*  NULLCHECK byte  
N001 (  3,  2) [000076] -----------                               |  \--*  LCL_VAR   ref    V00 this         
N005 (  5,  5) [000080] -----O-----                               \--*  ADD       byref 
N003 (  3,  2) [000078] -----------                                  +--*  LCL_VAR   ref    V00 this         
N004 (  1,  2) [000079] -----------                                  \--*  CNS_INT   long   80 Fseq[_dataTable]

***** BB01 [0000]
STMT00007 ( ??? ... ??? )
N014 ( 59, 42) [000049] -ACXGO-----                         *  CALL      void   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:ValidateResult(ulong,ulong,ulong,System.String):this
N008 ( 27, 14) [000089] DACXGO----- arg3 setup              +--*  STORE_LCL_VAR long   V07 tmp4         
N007 ( 23, 11) [000045] --CXGO-----                         |  \--*  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
N006 (  9,  8) [000087] ---X-O-N--- this in x0              |     \--*  COMMA     byref 
N002 (  4,  3) [000083] ---X-O-----                         |        +--*  NULLCHECK byte  
N001 (  3,  2) [000082] -----------                         |        |  \--*  LCL_VAR   ref    V00 this         
N005 (  5,  5) [000086] -----O-----                         |        \--*  ADD       byref 
N003 (  3,  2) [000084] -----------                         |           +--*  LCL_VAR   ref    V00 this         
N004 (  1,  2) [000085] -----------                         |           \--*  CNS_INT   long   80 Fseq[_dataTable]
N009 (  3,  2) [000090] ----------- arg3 in x3              +--*  LCL_VAR   long   V07 tmp4         
N010 (  3,  2) [000042] ----------- arg1 in x1              +--*  LCL_VAR   long   V05 tmp2         
N011 (  3,  2) [000047] ----------- arg2 in x2              +--*  LCL_VAR   long   V06 tmp3         
N012 (  3,  2) [000034] ----------- this in x0              +--*  LCL_VAR   ref    V00 this         
N013 (  3, 12) [000088] H---------- arg4 in x4              \--*  CNS_INT(h) ref     'RunBasicScenario_Load'

***** BB01 [0000]
STMT00008 ( 0x077[E-] ... ??? )
N001 (  0,  0) [000050] -----------                         *  RETURN    void  

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]

*************** Starting PHASE Stress gtSplitTree

*************** Finishing PHASE Stress gtSplitTree [no changes]

*************** Starting PHASE Expand casts

*************** Finishing PHASE Expand casts [no changes]

*************** Starting PHASE Expand runtime lookups

*************** Finishing PHASE Expand runtime lookups [no changes]

*************** Starting PHASE Expand static init
Nothing to expand.

*************** Finishing PHASE Expand static init [no changes]

*************** Starting PHASE Expand TLS access
Nothing to expand.

*************** Finishing PHASE Expand TLS access [no changes]

*************** Starting PHASE Insert GC Polls

*************** Finishing PHASE Insert GC Polls [no changes]

*************** Starting PHASE Create throw helper blocks

*************** Finishing PHASE Create throw helper blocks [no changes]

*************** Starting PHASE Determine first cold block
No procedure splitting will be done for this method

*************** Finishing PHASE Determine first cold block [no changes]

*************** Starting PHASE Rationalize IR

*************** Finishing PHASE Rationalize IR
Trees after Rationalize IR

---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   [IL range]   [jump]                            [EH region]        [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    [000..078)                           (return)                     i LIR hascall gcsafe nullcheck
---------------------------------------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [0000] [000..078) (return), preds={} succs={}
               [000091] -----------                            IL_OFFSET void   INLRT @ 0x000[E-]
N001 (  3, 12) [000051] H----------                   t51 =    CNS_INT(h) ref     'RunBasicScenario_Load'
                                                            /--*  t51    ref    arg0 in x0
N002 ( 17, 15) [000001] --CXG------                         *  CALL      void   TestLibrary.TestFramework:BeginScenario(System.String)
               [000092] -----------                            IL_OFFSET void   INLRT @ 0x00A[E-]
N001 (  1,  2) [000002] -------N---                    t2 =    CNS_INT   int    31
                                                            /--*  t2     int    
N002 (  2,  3) [000003] -----------                    t3 = *  HWINTRINSIC mask   int CreateTrueMaskInt32
                                                            /--*  t3     mask   
N003 (  3,  4) [000004] -----------                    t4 = *  HWINTRINSIC simd16 int ConvertMaskToVector
                                                            /--*  t4     simd16 
N004 (  7,  7) [000005] DA---------                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V01 loc0         
               [000093] -----------                            IL_OFFSET void   INLRT @ 0x012[E-]
N001 (  3,  2) [000052] -----------                   t52 =    LCL_VAR   ref    V00 this         
                                                            /--*  t52    ref    
N002 (  4,  3) [000053] ---X-O-----                         *  NULLCHECK byte  
N003 (  3,  2) [000054] -----------                   t54 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000055] -----------                   t55 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t54    ref    
                                                            +--*  t55    long   
N005 (  5,  5) [000056] -----O-----                   t56 = *  ADD       byref 
                                                            /--*  t56    byref  this in x0
N007 ( 23, 11) [000009] --CXGO-----                    t9 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
N008 (  3,  2) [000006] -----------                    t6 =    LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0         
N009 (  1,  1) [000011] -----------                   t11 =    HWINTRINSIC mask   int CreateTrueMaskAll
                                                            /--*  t11    mask   
                                                            +--*  t6     simd16 
N010 (  5,  4) [000012] -----------                   t12 = *  HWINTRINSIC mask   int ConvertVectorToMask
                                                            /--*  t12    mask   
                                                            +--*  t9     long   
N011 ( 29, 16) [000010] --CXGO-----                   t10 = *  HWINTRINSIC simd16 int LoadVector
                                                            /--*  t10    simd16 
N012 ( 33, 19) [000017] DACXGO-----                         *  STORE_LCL_VAR simd16 V04 tmp1         
N001 (  3,  2) [000058] -----------                   t58 =    LCL_VAR   ref    V00 this         
                                                            /--*  t58    ref    
N002 (  4,  3) [000059] ---X-O-----                         *  NULLCHECK byte  
N003 (  3,  2) [000060] -----------                   t60 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000061] -----------                   t61 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t60    ref    
                                                            +--*  t61    long   
N005 (  5,  5) [000062] -----O-----                   t62 = *  ADD       byref 
                                                            /--*  t62    byref  this in x0
N007 ( 23, 11) [000016] --CXGO-----                   t16 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
N008 (  3,  2) [000013] -----------                   t13 =    LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0         
N009 (  1,  1) [000020] -----------                   t20 =    HWINTRINSIC mask   int CreateTrueMaskAll
                                                            /--*  t20    mask   
                                                            +--*  t13    simd16 
N010 (  5,  4) [000021] -----------                   t21 = *  HWINTRINSIC mask   int ConvertVectorToMask
                                                            /--*  t21    mask   
                                                            +--*  t16    long   
N011 ( 29, 16) [000019] --CXGO-----                   t19 = *  HWINTRINSIC simd16 int LoadVector
N012 (  1,  1) [000025] -----------                   t25 =    HWINTRINSIC mask   int CreateTrueMaskAll
                                                            /--*  t25    mask   
                                                            +--*  t19    simd16 
N013 ( 31, 18) [000026] --CXGO-----                   t26 = *  HWINTRINSIC mask   int ConvertVectorToMask
N014 (  3,  2) [000018] -----------                   t18 =    LCL_VAR   simd16 V04 tmp1         
N015 (  1,  1) [000023] -----------                   t23 =    HWINTRINSIC mask   int CreateTrueMaskAll
                                                            /--*  t23    mask   
                                                            +--*  t18    simd16 
N016 (  5,  4) [000024] -----------                   t24 = *  HWINTRINSIC mask   int ConvertVectorToMask
                                                            /--*  t24    mask   
                                                            +--*  t26    mask   
N017 ( 37, 23) [000022] --CXGO-----                   t22 = *  HWINTRINSIC mask   int CreateBreakPropagateMask
                                                            /--*  t22    mask   
N018 ( 38, 24) [000027] --CXGO-----                   t27 = *  HWINTRINSIC simd16 int ConvertMaskToVector
                                                            /--*  t27    simd16 
N019 ( 42, 27) [000028] DACXGO-----                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V02 loc1         
               [000094] -----------                            IL_OFFSET void   INLRT @ 0x03A[E-]
N001 (  3,  2) [000064] -----------                   t64 =    LCL_VAR   ref    V00 this         
                                                            /--*  t64    ref    
N002 (  4,  3) [000065] ---X-O-----                         *  NULLCHECK byte  
N003 (  3,  2) [000066] -----------                   t66 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000067] -----------                   t67 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t66    ref    
                                                            +--*  t67    long   
N005 (  5,  5) [000068] -----O-----                   t68 = *  ADD       byref 
                                                            /--*  t68    byref  this in x0
N007 ( 23, 11) [000031] --CXGO-----                   t31 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
N008 (  3,  2) [000032] -----------                   t32 =    LCL_VAR   simd16<System.Numerics.Vector`1> V02 loc1         
                                                            /--*  t31    long   
                                                            +--*  t32    simd16 
N009 ( 30, 16) [000033] -ACXGO-----                         *  STOREIND  simd16 (copy)
               [000095] -----------                            IL_OFFSET void   INLRT @ 0x04B[E-]
N001 (  3,  2) [000070] -----------                   t70 =    LCL_VAR   ref    V00 this         
                                                            /--*  t70    ref    
N002 (  4,  3) [000071] ---X-O-----                         *  NULLCHECK byte  
N003 (  3,  2) [000072] -----------                   t72 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000073] -----------                   t73 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t72    ref    
                                                            +--*  t73    long   
N005 (  5,  5) [000074] -----O-----                   t74 = *  ADD       byref 
                                                            /--*  t74    byref  this in x0
N007 ( 23, 11) [000037] --CXGO-----                   t37 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
                                                            /--*  t37    long   
N008 ( 27, 14) [000041] DACXGO-----                         *  STORE_LCL_VAR long   V05 tmp2         
N001 (  3,  2) [000076] -----------                   t76 =    LCL_VAR   ref    V00 this         
                                                            /--*  t76    ref    
N002 (  4,  3) [000077] ---X-O-----                         *  NULLCHECK byte  
N003 (  3,  2) [000078] -----------                   t78 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000079] -----------                   t79 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t78    ref    
                                                            +--*  t79    long   
N005 (  5,  5) [000080] -----O-----                   t80 = *  ADD       byref 
                                                            /--*  t80    byref  this in x0
N007 ( 23, 11) [000040] --CXGO-----                   t40 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
                                                            /--*  t40    long   
N008 ( 27, 14) [000046] DACXGO-----                         *  STORE_LCL_VAR long   V06 tmp3         
N001 (  3,  2) [000082] -----------                   t82 =    LCL_VAR   ref    V00 this         
                                                            /--*  t82    ref    
N002 (  4,  3) [000083] ---X-O-----                         *  NULLCHECK byte  
N003 (  3,  2) [000084] -----------                   t84 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000085] -----------                   t85 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t84    ref    
                                                            +--*  t85    long   
N005 (  5,  5) [000086] -----O-----                   t86 = *  ADD       byref 
                                                            /--*  t86    byref  this in x0
N007 ( 23, 11) [000045] --CXGO-----                   t45 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
                                                            /--*  t45    long   
N008 ( 27, 14) [000089] DACXGO-----                         *  STORE_LCL_VAR long   V07 tmp4         
N009 (  3,  2) [000090] -----------                   t90 =    LCL_VAR   long   V07 tmp4         
N010 (  3,  2) [000042] -----------                   t42 =    LCL_VAR   long   V05 tmp2         
N011 (  3,  2) [000047] -----------                   t47 =    LCL_VAR   long   V06 tmp3         
N012 (  3,  2) [000034] -----------                   t34 =    LCL_VAR   ref    V00 this         
N013 (  3, 12) [000088] H----------                   t88 =    CNS_INT(h) ref     'RunBasicScenario_Load'
                                                            /--*  t90    long   arg3 in x3
                                                            +--*  t42    long   arg1 in x1
                                                            +--*  t47    long   arg2 in x2
                                                            +--*  t34    ref    this in x0
                                                            +--*  t88    ref    arg4 in x4
N014 ( 59, 42) [000049] -ACXGO-----                         *  CALL      void   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:ValidateResult(ulong,ulong,ulong,System.String):this
               [000096] -----------                            IL_OFFSET void   INLRT @ 0x077[E-]
N001 (  0,  0) [000050] -----------                            RETURN    void  

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]

*************** Starting PHASE Lowering nodeinfo
compEnregLocals() is false, setting doNotEnreg flag for all locals.
Local V00 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set

Local V01 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set

Local V02 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set

Local V03 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set

Local V04 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set

Local V05 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set

Local V06 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set

Local V07 should not be enregistered because: opts.compFlags & CLFLG_REGVAR is not set
lowering call (before):
N001 (  3, 12) [000051] H----------                   t51 =    CNS_INT(h) ref     'RunBasicScenario_Load'
                                                            /--*  t51    ref    arg0 in x0
N002 ( 17, 15) [000001] --CXG------                         *  CALL      void   TestLibrary.TestFramework:BeginScenario(System.String)

args:
======

late:
======
lowering arg : N001 (  3, 12) [000051] H----------                         *  CNS_INT(h) ref     'RunBasicScenario_Load'
new node is :                [000097] -----------                         *  PUTARG_REG ref    REG x0

results of lowering call:
N001 (  3, 12) [000098] H----------                   t98 =    CNS_INT(h) long   0x7ffac2114528 ftn
                                                            /--*  t98    long   
N002 (  6, 14) [000099] n---G------                   t99 = *  IND       long  
lowering call (after):
N001 (  3, 12) [000051] H----------                   t51 =    CNS_INT(h) ref     'RunBasicScenario_Load'
                                                            /--*  t51    ref    
               [000097] -----------                   t97 = *  PUTARG_REG ref    REG x0
N001 (  3, 12) [000098] H----------                   t98 =    CNS_INT(h) long   0x7ffac2114528 ftn
                                                            /--*  t98    long   
N002 (  6, 14) [000099] n---G------                   t99 = *  IND       long  
                                                            /--*  t97    ref    arg0 in x0
                                                            +--*  t99    long   control expr
N002 ( 17, 15) [000001] --CXG------                         *  CALL      void   TestLibrary.TestFramework:BeginScenario(System.String)

lowering store lcl var/field (before):
N001 (  1,  2) [000002] -c-----N---                    t2 =    CNS_INT   int    31
                                                            /--*  t2     int    
N002 (  2,  3) [000003] -----------                    t3 = *  HWINTRINSIC mask   int CreateTrueMaskInt32
                                                            /--*  t3     mask   
N003 (  3,  4) [000004] -----------                    t4 = *  HWINTRINSIC simd16 int ConvertMaskToVector
                                                            /--*  t4     simd16 
N004 (  7,  7) [000005] DA---------                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V01 loc0         

lowering store lcl var/field (after):
N001 (  1,  2) [000002] -c-----N---                    t2 =    CNS_INT   int    31
                                                            /--*  t2     int    
N002 (  2,  3) [000003] -----------                    t3 = *  HWINTRINSIC mask   int CreateTrueMaskInt32
                                                            /--*  t3     mask   
N003 (  3,  4) [000004] -----------                    t4 = *  HWINTRINSIC simd16 int ConvertMaskToVector
                                                            /--*  t4     simd16 
N004 (  7,  7) [000005] DA---------                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V01 loc0         

lowering call (before):
N003 (  3,  2) [000054] -----------                   t54 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000055] -c---------                   t55 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t54    ref    
                                                            +--*  t55    long   
N005 (  5,  5) [000056] -----O-----                   t56 = *  ADD       byref 
                                                            /--*  t56    byref  this in x0
N007 ( 23, 11) [000009] --CXGO-----                    t9 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this

args:
======

late:
======
lowering arg : N005 (  5,  5) [000056] -----O-----                         *  ADD       byref 
new node is :                [000100] -----O-----                         *  PUTARG_REG byref  REG x0

results of lowering call:
N001 (  3, 12) [000101] H----------                  t101 =    CNS_INT(h) long   0x7ffac1def648 ftn
                                                            /--*  t101   long   
N002 (  6, 14) [000102] n---G------                  t102 = *  IND       long  
lowering call (after):
N003 (  3,  2) [000054] -----------                   t54 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000055] -c---------                   t55 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t54    ref    
                                                            +--*  t55    long   
N005 (  5,  5) [000056] -----O-----                   t56 = *  ADD       byref 
                                                            /--*  t56    byref  
               [000100] -----O-----                  t100 = *  PUTARG_REG byref  REG x0
N001 (  3, 12) [000101] H----------                  t101 =    CNS_INT(h) long   0x7ffac1def648 ftn
                                                            /--*  t101   long   
N002 (  6, 14) [000102] n---G------                  t102 = *  IND       long  
                                                            /--*  t100   byref  this in x0
                                                            +--*  t102   long   control expr
N007 ( 23, 11) [000009] --CXGO-----                    t9 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this

lowering store lcl var/field (before):
N003 (  3,  2) [000054] -----------                   t54 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000055] -c---------                   t55 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t54    ref    
                                                            +--*  t55    long   
N005 (  5,  5) [000056] -----O-----                   t56 = *  ADD       byref 
                                                            /--*  t56    byref  
               [000100] -----O-----                  t100 = *  PUTARG_REG byref  REG x0
N001 (  3, 12) [000101] H----------                  t101 =    CNS_INT(h) long   0x7ffac1def648 ftn
                                                            /--*  t101   long   
N002 (  6, 14) [000102] n---G------                  t102 = *  IND       long  
                                                            /--*  t100   byref  this in x0
                                                            +--*  t102   long   control expr
N007 ( 23, 11) [000009] --CXGO-----                    t9 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
N008 (  3,  2) [000006] -----------                    t6 =    LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0         
N009 (  1,  1) [000011] -----------                   t11 =    HWINTRINSIC mask   int CreateTrueMaskAll
                                                            /--*  t11    mask   
                                                            +--*  t6     simd16 
N010 (  5,  4) [000012] -----------                   t12 = *  HWINTRINSIC mask   int ConvertVectorToMask
                                                            /--*  t12    mask   
                                                            +--*  t9     long   
N011 ( 29, 16) [000010] --CXGO-----                   t10 = *  HWINTRINSIC simd16 int LoadVector
                                                            /--*  t10    simd16 
N012 ( 33, 19) [000017] DACXGO-----                         *  STORE_LCL_VAR simd16 V04 tmp1         

lowering store lcl var/field (after):
N003 (  3,  2) [000054] -----------                   t54 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000055] -c---------                   t55 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t54    ref    
                                                            +--*  t55    long   
N005 (  5,  5) [000056] -----O-----                   t56 = *  ADD       byref 
                                                            /--*  t56    byref  
               [000100] -----O-----                  t100 = *  PUTARG_REG byref  REG x0
N001 (  3, 12) [000101] H----------                  t101 =    CNS_INT(h) long   0x7ffac1def648 ftn
                                                            /--*  t101   long   
N002 (  6, 14) [000102] n---G------                  t102 = *  IND       long  
                                                            /--*  t100   byref  this in x0
                                                            +--*  t102   long   control expr
N007 ( 23, 11) [000009] --CXGO-----                    t9 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
N008 (  3,  2) [000006] -----------                    t6 =    LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0         
N009 (  1,  1) [000011] -----------                   t11 =    HWINTRINSIC mask   int CreateTrueMaskAll
                                                            /--*  t11    mask   
                                                            +--*  t6     simd16 
N010 (  5,  4) [000012] -----------                   t12 = *  HWINTRINSIC mask   int ConvertVectorToMask
                                                            /--*  t12    mask   
                                                            +--*  t9     long   
N011 ( 29, 16) [000010] --CXGO-----                   t10 = *  HWINTRINSIC simd16 int LoadVector
                                                            /--*  t10    simd16 
N012 ( 33, 19) [000017] DACXGO-----                         *  STORE_LCL_VAR simd16 V04 tmp1         

lowering call (before):
N003 (  3,  2) [000060] -----------                   t60 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000061] -c---------                   t61 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t60    ref    
                                                            +--*  t61    long   
N005 (  5,  5) [000062] -----O-----                   t62 = *  ADD       byref 
                                                            /--*  t62    byref  this in x0
N007 ( 23, 11) [000016] --CXGO-----                   t16 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this

args:
======

late:
======
lowering arg : N005 (  5,  5) [000062] -----O-----                         *  ADD       byref 
new node is :                [000103] -----O-----                         *  PUTARG_REG byref  REG x0

results of lowering call:
N001 (  3, 12) [000104] H----------                  t104 =    CNS_INT(h) long   0x7ffac1def660 ftn
                                                            /--*  t104   long   
N002 (  6, 14) [000105] n---G------                  t105 = *  IND       long  
lowering call (after):
N003 (  3,  2) [000060] -----------                   t60 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000061] -c---------                   t61 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t60    ref    
                                                            +--*  t61    long   
N005 (  5,  5) [000062] -----O-----                   t62 = *  ADD       byref 
                                                            /--*  t62    byref  
               [000103] -----O-----                  t103 = *  PUTARG_REG byref  REG x0
N001 (  3, 12) [000104] H----------                  t104 =    CNS_INT(h) long   0x7ffac1def660 ftn
                                                            /--*  t104   long   
N002 (  6, 14) [000105] n---G------                  t105 = *  IND       long  
                                                            /--*  t103   byref  this in x0
                                                            +--*  t105   long   control expr
N007 ( 23, 11) [000016] --CXGO-----                   t16 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this

lowering EmbeddedMasked HWIntrinisic (before):
N003 (  3,  2) [000060] -----------                   t60 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000061] -c---------                   t61 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t60    ref    
                                                            +--*  t61    long   
N005 (  5,  5) [000062] -----O-----                   t62 = *  ADD       byref 
                                                            /--*  t62    byref  
               [000103] -----O-----                  t103 = *  PUTARG_REG byref  REG x0
N001 (  3, 12) [000104] H----------                  t104 =    CNS_INT(h) long   0x7ffac1def660 ftn
                                                            /--*  t104   long   
N002 (  6, 14) [000105] n---G------                  t105 = *  IND       long  
                                                            /--*  t103   byref  this in x0
                                                            +--*  t105   long   control expr
N007 ( 23, 11) [000016] --CXGO-----                   t16 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
N008 (  3,  2) [000013] -----------                   t13 =    LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0         
N009 (  1,  1) [000020] -----------                   t20 =    HWINTRINSIC mask   int CreateTrueMaskAll
                                                            /--*  t20    mask   
                                                            +--*  t13    simd16 
N010 (  5,  4) [000021] -----------                   t21 = *  HWINTRINSIC mask   int ConvertVectorToMask
                                                            /--*  t21    mask   
                                                            +--*  t16    long   
N011 ( 29, 16) [000019] --CXGO-----                   t19 = *  HWINTRINSIC simd16 int LoadVector
N012 (  1,  1) [000025] -----------                   t25 =    HWINTRINSIC mask   int CreateTrueMaskAll
                                                            /--*  t25    mask   
                                                            +--*  t19    simd16 
N013 ( 31, 18) [000026] --CXGO-----                   t26 = *  HWINTRINSIC mask   int ConvertVectorToMask
N014 (  3,  2) [000018] -----------                   t18 =    LCL_VAR   simd16 V04 tmp1         
N015 (  1,  1) [000023] -----------                   t23 =    HWINTRINSIC mask   int CreateTrueMaskAll
                                                            /--*  t23    mask   
                                                            +--*  t18    simd16 
N016 (  5,  4) [000024] -----------                   t24 = *  HWINTRINSIC mask   int ConvertVectorToMask
                                                            /--*  t24    mask   
                                                            +--*  t26    mask   
N017 ( 37, 23) [000022] --CXGO-----                   t22 = *  HWINTRINSIC mask   int CreateBreakPropagateMask

lowering EmbeddedMasked HWIntrinisic (after):
N003 (  3,  2) [000060] -----------                   t60 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000061] -c---------                   t61 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t60    ref    
                                                            +--*  t61    long   
N005 (  5,  5) [000062] -----O-----                   t62 = *  ADD       byref 
                                                            /--*  t62    byref  
               [000103] -----O-----                  t103 = *  PUTARG_REG byref  REG x0
N001 (  3, 12) [000104] H----------                  t104 =    CNS_INT(h) long   0x7ffac1def660 ftn
                                                            /--*  t104   long   
N002 (  6, 14) [000105] n---G------                  t105 = *  IND       long  
                                                            /--*  t103   byref  this in x0
                                                            +--*  t105   long   control expr
N007 ( 23, 11) [000016] --CXGO-----                   t16 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
N008 (  3,  2) [000013] -----------                   t13 =    LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0         
N009 (  1,  1) [000020] -----------                   t20 =    HWINTRINSIC mask   int CreateTrueMaskAll
                                                            /--*  t20    mask   
                                                            +--*  t13    simd16 
N010 (  5,  4) [000021] -----------                   t21 = *  HWINTRINSIC mask   int ConvertVectorToMask
                                                            /--*  t21    mask   
                                                            +--*  t16    long   
N011 ( 29, 16) [000019] --CXGO-----                   t19 = *  HWINTRINSIC simd16 int LoadVector
N012 (  1,  1) [000025] -----------                   t25 =    HWINTRINSIC mask   int CreateTrueMaskAll
                                                            /--*  t25    mask   
                                                            +--*  t19    simd16 
N013 ( 31, 18) [000026] --CXGO-----                   t26 = *  HWINTRINSIC mask   int ConvertVectorToMask
N014 (  3,  2) [000018] -----------                   t18 =    LCL_VAR   simd16 V04 tmp1         
N015 (  1,  1) [000023] -----------                   t23 =    HWINTRINSIC mask   int CreateTrueMaskAll
                                                            /--*  t23    mask   
                                                            +--*  t18    simd16 
N016 (  5,  4) [000024] -----------                   t24 = *  HWINTRINSIC mask   int ConvertVectorToMask
               [000106] -----------                  t106 =    HWINTRINSIC mask   int CreateTrueMaskAll
               [000107] -----------                  t107 =    CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000>
                                                            /--*  t24    mask   
                                                            +--*  t26    mask   
N017 ( 37, 23) [000022] --CXGO-----                   t22 = *  HWINTRINSIC mask   int CreateBreakPropagateMask
                                                            /--*  t106   mask   
                                                            +--*  t22    mask   
                                                            +--*  t107   simd16 
               [000108] --CXGO-----                  t108 = *  HWINTRINSIC mask   int ConditionalSelect

lowering store lcl var/field (before):
N003 (  3,  2) [000060] -----------                   t60 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000061] -c---------                   t61 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t60    ref    
                                                            +--*  t61    long   
N005 (  5,  5) [000062] -----O-----                   t62 = *  ADD       byref 
                                                            /--*  t62    byref  
               [000103] -----O-----                  t103 = *  PUTARG_REG byref  REG x0
N001 (  3, 12) [000104] H----------                  t104 =    CNS_INT(h) long   0x7ffac1def660 ftn
                                                            /--*  t104   long   
N002 (  6, 14) [000105] n---G------                  t105 = *  IND       long  
                                                            /--*  t103   byref  this in x0
                                                            +--*  t105   long   control expr
N007 ( 23, 11) [000016] --CXGO-----                   t16 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
N008 (  3,  2) [000013] -----------                   t13 =    LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0         
N009 (  1,  1) [000020] -----------                   t20 =    HWINTRINSIC mask   int CreateTrueMaskAll
                                                            /--*  t20    mask   
                                                            +--*  t13    simd16 
N010 (  5,  4) [000021] -----------                   t21 = *  HWINTRINSIC mask   int ConvertVectorToMask
                                                            /--*  t21    mask   
                                                            +--*  t16    long   
N011 ( 29, 16) [000019] --CXGO-----                   t19 = *  HWINTRINSIC simd16 int LoadVector
N012 (  1,  1) [000025] -----------                   t25 =    HWINTRINSIC mask   int CreateTrueMaskAll
                                                            /--*  t25    mask   
                                                            +--*  t19    simd16 
N013 ( 31, 18) [000026] --CXGO-----                   t26 = *  HWINTRINSIC mask   int ConvertVectorToMask
N014 (  3,  2) [000018] -----------                   t18 =    LCL_VAR   simd16 V04 tmp1         
N015 (  1,  1) [000023] -----------                   t23 =    HWINTRINSIC mask   int CreateTrueMaskAll
                                                            /--*  t23    mask   
                                                            +--*  t18    simd16 
N016 (  5,  4) [000024] -----------                   t24 = *  HWINTRINSIC mask   int ConvertVectorToMask
               [000106] -----------                  t106 =    HWINTRINSIC mask   int CreateTrueMaskAll
               [000107] -c---------                  t107 =    CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000>
                                                            /--*  t24    mask   
                                                            +--*  t26    mask   
N017 ( 37, 23) [000022] -cCXGO-----                   t22 = *  HWINTRINSIC mask   int CreateBreakPropagateMask
                                                            /--*  t106   mask   
                                                            +--*  t22    mask   
                                                            +--*  t107   simd16 
               [000108] --CXGO-----                  t108 = *  HWINTRINSIC mask   int ConditionalSelect
                                                            /--*  t108   mask   
N018 ( 38, 24) [000027] --CXGO-----                   t27 = *  HWINTRINSIC simd16 int ConvertMaskToVector
                                                            /--*  t27    simd16 
N019 ( 42, 27) [000028] DACXGO-----                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V02 loc1         

lowering store lcl var/field (after):
N003 (  3,  2) [000060] -----------                   t60 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000061] -c---------                   t61 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t60    ref    
                                                            +--*  t61    long   
N005 (  5,  5) [000062] -----O-----                   t62 = *  ADD       byref 
                                                            /--*  t62    byref  
               [000103] -----O-----                  t103 = *  PUTARG_REG byref  REG x0
N001 (  3, 12) [000104] H----------                  t104 =    CNS_INT(h) long   0x7ffac1def660 ftn
                                                            /--*  t104   long   
N002 (  6, 14) [000105] n---G------                  t105 = *  IND       long  
                                                            /--*  t103   byref  this in x0
                                                            +--*  t105   long   control expr
N007 ( 23, 11) [000016] --CXGO-----                   t16 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
N008 (  3,  2) [000013] -----------                   t13 =    LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0         
N009 (  1,  1) [000020] -----------                   t20 =    HWINTRINSIC mask   int CreateTrueMaskAll
                                                            /--*  t20    mask   
                                                            +--*  t13    simd16 
N010 (  5,  4) [000021] -----------                   t21 = *  HWINTRINSIC mask   int ConvertVectorToMask
                                                            /--*  t21    mask   
                                                            +--*  t16    long   
N011 ( 29, 16) [000019] --CXGO-----                   t19 = *  HWINTRINSIC simd16 int LoadVector
N012 (  1,  1) [000025] -----------                   t25 =    HWINTRINSIC mask   int CreateTrueMaskAll
                                                            /--*  t25    mask   
                                                            +--*  t19    simd16 
N013 ( 31, 18) [000026] --CXGO-----                   t26 = *  HWINTRINSIC mask   int ConvertVectorToMask
N014 (  3,  2) [000018] -----------                   t18 =    LCL_VAR   simd16 V04 tmp1         
N015 (  1,  1) [000023] -----------                   t23 =    HWINTRINSIC mask   int CreateTrueMaskAll
                                                            /--*  t23    mask   
                                                            +--*  t18    simd16 
N016 (  5,  4) [000024] -----------                   t24 = *  HWINTRINSIC mask   int ConvertVectorToMask
               [000106] -----------                  t106 =    HWINTRINSIC mask   int CreateTrueMaskAll
               [000107] -c---------                  t107 =    CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000>
                                                            /--*  t24    mask   
                                                            +--*  t26    mask   
N017 ( 37, 23) [000022] -cCXGO-----                   t22 = *  HWINTRINSIC mask   int CreateBreakPropagateMask
                                                            /--*  t106   mask   
                                                            +--*  t22    mask   
                                                            +--*  t107   simd16 
               [000108] --CXGO-----                  t108 = *  HWINTRINSIC mask   int ConditionalSelect
                                                            /--*  t108   mask   
N018 ( 38, 24) [000027] --CXGO-----                   t27 = *  HWINTRINSIC simd16 int ConvertMaskToVector
                                                            /--*  t27    simd16 
N019 ( 42, 27) [000028] DACXGO-----                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V02 loc1         

lowering call (before):
N003 (  3,  2) [000066] -----------                   t66 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000067] -c---------                   t67 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t66    ref    
                                                            +--*  t67    long   
N005 (  5,  5) [000068] -----O-----                   t68 = *  ADD       byref 
                                                            /--*  t68    byref  this in x0
N007 ( 23, 11) [000031] --CXGO-----                   t31 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this

args:
======

late:
======
lowering arg : N005 (  5,  5) [000068] -----O-----                         *  ADD       byref 
new node is :                [000109] -----O-----                         *  PUTARG_REG byref  REG x0

results of lowering call:
N001 (  3, 12) [000110] H----------                  t110 =    CNS_INT(h) long   0x7ffac1def678 ftn
                                                            /--*  t110   long   
N002 (  6, 14) [000111] n---G------                  t111 = *  IND       long  
lowering call (after):
N003 (  3,  2) [000066] -----------                   t66 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000067] -c---------                   t67 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t66    ref    
                                                            +--*  t67    long   
N005 (  5,  5) [000068] -----O-----                   t68 = *  ADD       byref 
                                                            /--*  t68    byref  
               [000109] -----O-----                  t109 = *  PUTARG_REG byref  REG x0
N001 (  3, 12) [000110] H----------                  t110 =    CNS_INT(h) long   0x7ffac1def678 ftn
                                                            /--*  t110   long   
N002 (  6, 14) [000111] n---G------                  t111 = *  IND       long  
                                                            /--*  t109   byref  this in x0
                                                            +--*  t111   long   control expr
N007 ( 23, 11) [000031] --CXGO-----                   t31 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this

lowering call (before):
N003 (  3,  2) [000072] -----------                   t72 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000073] -c---------                   t73 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t72    ref    
                                                            +--*  t73    long   
N005 (  5,  5) [000074] -----O-----                   t74 = *  ADD       byref 
                                                            /--*  t74    byref  this in x0
N007 ( 23, 11) [000037] --CXGO-----                   t37 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this

args:
======

late:
======
lowering arg : N005 (  5,  5) [000074] -----O-----                         *  ADD       byref 
new node is :                [000112] -----O-----                         *  PUTARG_REG byref  REG x0

results of lowering call:
N001 (  3, 12) [000113] H----------                  t113 =    CNS_INT(h) long   0x7ffac1def648 ftn
                                                            /--*  t113   long   
N002 (  6, 14) [000114] n---G------                  t114 = *  IND       long  
lowering call (after):
N003 (  3,  2) [000072] -----------                   t72 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000073] -c---------                   t73 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t72    ref    
                                                            +--*  t73    long   
N005 (  5,  5) [000074] -----O-----                   t74 = *  ADD       byref 
                                                            /--*  t74    byref  
               [000112] -----O-----                  t112 = *  PUTARG_REG byref  REG x0
N001 (  3, 12) [000113] H----------                  t113 =    CNS_INT(h) long   0x7ffac1def648 ftn
                                                            /--*  t113   long   
N002 (  6, 14) [000114] n---G------                  t114 = *  IND       long  
                                                            /--*  t112   byref  this in x0
                                                            +--*  t114   long   control expr
N007 ( 23, 11) [000037] --CXGO-----                   t37 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this

lowering store lcl var/field (before):
N003 (  3,  2) [000072] -----------                   t72 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000073] -c---------                   t73 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t72    ref    
                                                            +--*  t73    long   
N005 (  5,  5) [000074] -----O-----                   t74 = *  ADD       byref 
                                                            /--*  t74    byref  
               [000112] -----O-----                  t112 = *  PUTARG_REG byref  REG x0
N001 (  3, 12) [000113] H----------                  t113 =    CNS_INT(h) long   0x7ffac1def648 ftn
                                                            /--*  t113   long   
N002 (  6, 14) [000114] n---G------                  t114 = *  IND       long  
                                                            /--*  t112   byref  this in x0
                                                            +--*  t114   long   control expr
N007 ( 23, 11) [000037] --CXGO-----                   t37 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
                                                            /--*  t37    long   
N008 ( 27, 14) [000041] DACXGO-----                         *  STORE_LCL_VAR long   V05 tmp2         

lowering store lcl var/field (after):
N003 (  3,  2) [000072] -----------                   t72 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000073] -c---------                   t73 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t72    ref    
                                                            +--*  t73    long   
N005 (  5,  5) [000074] -----O-----                   t74 = *  ADD       byref 
                                                            /--*  t74    byref  
               [000112] -----O-----                  t112 = *  PUTARG_REG byref  REG x0
N001 (  3, 12) [000113] H----------                  t113 =    CNS_INT(h) long   0x7ffac1def648 ftn
                                                            /--*  t113   long   
N002 (  6, 14) [000114] n---G------                  t114 = *  IND       long  
                                                            /--*  t112   byref  this in x0
                                                            +--*  t114   long   control expr
N007 ( 23, 11) [000037] --CXGO-----                   t37 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
                                                            /--*  t37    long   
N008 ( 27, 14) [000041] DACXGO-----                         *  STORE_LCL_VAR long   V05 tmp2         

lowering call (before):
N003 (  3,  2) [000078] -----------                   t78 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000079] -c---------                   t79 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t78    ref    
                                                            +--*  t79    long   
N005 (  5,  5) [000080] -----O-----                   t80 = *  ADD       byref 
                                                            /--*  t80    byref  this in x0
N007 ( 23, 11) [000040] --CXGO-----                   t40 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this

args:
======

late:
======
lowering arg : N005 (  5,  5) [000080] -----O-----                         *  ADD       byref 
new node is :                [000115] -----O-----                         *  PUTARG_REG byref  REG x0

results of lowering call:
N001 (  3, 12) [000116] H----------                  t116 =    CNS_INT(h) long   0x7ffac1def660 ftn
                                                            /--*  t116   long   
N002 (  6, 14) [000117] n---G------                  t117 = *  IND       long  
lowering call (after):
N003 (  3,  2) [000078] -----------                   t78 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000079] -c---------                   t79 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t78    ref    
                                                            +--*  t79    long   
N005 (  5,  5) [000080] -----O-----                   t80 = *  ADD       byref 
                                                            /--*  t80    byref  
               [000115] -----O-----                  t115 = *  PUTARG_REG byref  REG x0
N001 (  3, 12) [000116] H----------                  t116 =    CNS_INT(h) long   0x7ffac1def660 ftn
                                                            /--*  t116   long   
N002 (  6, 14) [000117] n---G------                  t117 = *  IND       long  
                                                            /--*  t115   byref  this in x0
                                                            +--*  t117   long   control expr
N007 ( 23, 11) [000040] --CXGO-----                   t40 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this

lowering store lcl var/field (before):
N003 (  3,  2) [000078] -----------                   t78 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000079] -c---------                   t79 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t78    ref    
                                                            +--*  t79    long   
N005 (  5,  5) [000080] -----O-----                   t80 = *  ADD       byref 
                                                            /--*  t80    byref  
               [000115] -----O-----                  t115 = *  PUTARG_REG byref  REG x0
N001 (  3, 12) [000116] H----------                  t116 =    CNS_INT(h) long   0x7ffac1def660 ftn
                                                            /--*  t116   long   
N002 (  6, 14) [000117] n---G------                  t117 = *  IND       long  
                                                            /--*  t115   byref  this in x0
                                                            +--*  t117   long   control expr
N007 ( 23, 11) [000040] --CXGO-----                   t40 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
                                                            /--*  t40    long   
N008 ( 27, 14) [000046] DACXGO-----                         *  STORE_LCL_VAR long   V06 tmp3         

lowering store lcl var/field (after):
N003 (  3,  2) [000078] -----------                   t78 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000079] -c---------                   t79 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t78    ref    
                                                            +--*  t79    long   
N005 (  5,  5) [000080] -----O-----                   t80 = *  ADD       byref 
                                                            /--*  t80    byref  
               [000115] -----O-----                  t115 = *  PUTARG_REG byref  REG x0
N001 (  3, 12) [000116] H----------                  t116 =    CNS_INT(h) long   0x7ffac1def660 ftn
                                                            /--*  t116   long   
N002 (  6, 14) [000117] n---G------                  t117 = *  IND       long  
                                                            /--*  t115   byref  this in x0
                                                            +--*  t117   long   control expr
N007 ( 23, 11) [000040] --CXGO-----                   t40 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
                                                            /--*  t40    long   
N008 ( 27, 14) [000046] DACXGO-----                         *  STORE_LCL_VAR long   V06 tmp3         

lowering call (before):
N003 (  3,  2) [000084] -----------                   t84 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000085] -c---------                   t85 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t84    ref    
                                                            +--*  t85    long   
N005 (  5,  5) [000086] -----O-----                   t86 = *  ADD       byref 
                                                            /--*  t86    byref  this in x0
N007 ( 23, 11) [000045] --CXGO-----                   t45 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this

args:
======

late:
======
lowering arg : N005 (  5,  5) [000086] -----O-----                         *  ADD       byref 
new node is :                [000118] -----O-----                         *  PUTARG_REG byref  REG x0

results of lowering call:
N001 (  3, 12) [000119] H----------                  t119 =    CNS_INT(h) long   0x7ffac1def678 ftn
                                                            /--*  t119   long   
N002 (  6, 14) [000120] n---G------                  t120 = *  IND       long  
lowering call (after):
N003 (  3,  2) [000084] -----------                   t84 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000085] -c---------                   t85 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t84    ref    
                                                            +--*  t85    long   
N005 (  5,  5) [000086] -----O-----                   t86 = *  ADD       byref 
                                                            /--*  t86    byref  
               [000118] -----O-----                  t118 = *  PUTARG_REG byref  REG x0
N001 (  3, 12) [000119] H----------                  t119 =    CNS_INT(h) long   0x7ffac1def678 ftn
                                                            /--*  t119   long   
N002 (  6, 14) [000120] n---G------                  t120 = *  IND       long  
                                                            /--*  t118   byref  this in x0
                                                            +--*  t120   long   control expr
N007 ( 23, 11) [000045] --CXGO-----                   t45 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this

lowering store lcl var/field (before):
N003 (  3,  2) [000084] -----------                   t84 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000085] -c---------                   t85 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t84    ref    
                                                            +--*  t85    long   
N005 (  5,  5) [000086] -----O-----                   t86 = *  ADD       byref 
                                                            /--*  t86    byref  
               [000118] -----O-----                  t118 = *  PUTARG_REG byref  REG x0
N001 (  3, 12) [000119] H----------                  t119 =    CNS_INT(h) long   0x7ffac1def678 ftn
                                                            /--*  t119   long   
N002 (  6, 14) [000120] n---G------                  t120 = *  IND       long  
                                                            /--*  t118   byref  this in x0
                                                            +--*  t120   long   control expr
N007 ( 23, 11) [000045] --CXGO-----                   t45 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
                                                            /--*  t45    long   
N008 ( 27, 14) [000089] DACXGO-----                         *  STORE_LCL_VAR long   V07 tmp4         

lowering store lcl var/field (after):
N003 (  3,  2) [000084] -----------                   t84 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000085] -c---------                   t85 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t84    ref    
                                                            +--*  t85    long   
N005 (  5,  5) [000086] -----O-----                   t86 = *  ADD       byref 
                                                            /--*  t86    byref  
               [000118] -----O-----                  t118 = *  PUTARG_REG byref  REG x0
N001 (  3, 12) [000119] H----------                  t119 =    CNS_INT(h) long   0x7ffac1def678 ftn
                                                            /--*  t119   long   
N002 (  6, 14) [000120] n---G------                  t120 = *  IND       long  
                                                            /--*  t118   byref  this in x0
                                                            +--*  t120   long   control expr
N007 ( 23, 11) [000045] --CXGO-----                   t45 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
                                                            /--*  t45    long   
N008 ( 27, 14) [000089] DACXGO-----                         *  STORE_LCL_VAR long   V07 tmp4         

lowering call (before):
N009 (  3,  2) [000090] -----------                   t90 =    LCL_VAR   long   V07 tmp4         
N010 (  3,  2) [000042] -----------                   t42 =    LCL_VAR   long   V05 tmp2         
N011 (  3,  2) [000047] -----------                   t47 =    LCL_VAR   long   V06 tmp3         
N012 (  3,  2) [000034] -----------                   t34 =    LCL_VAR   ref    V00 this         
N013 (  3, 12) [000088] H----------                   t88 =    CNS_INT(h) ref     'RunBasicScenario_Load'
                                                            /--*  t90    long   arg3 in x3
                                                            +--*  t42    long   arg1 in x1
                                                            +--*  t47    long   arg2 in x2
                                                            +--*  t34    ref    this in x0
                                                            +--*  t88    ref    arg4 in x4
N014 ( 59, 42) [000049] -ACXGO-----                         *  CALL      void   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:ValidateResult(ulong,ulong,ulong,System.String):this

args:
======

late:
======
lowering arg : N009 (  3,  2) [000090] -----------                         *  LCL_VAR   long   V07 tmp4         
new node is :                [000121] -----------                         *  PUTARG_REG long   REG x3

lowering arg : N010 (  3,  2) [000042] -----------                         *  LCL_VAR   long   V05 tmp2         
new node is :                [000122] -----------                         *  PUTARG_REG long   REG x1

lowering arg : N011 (  3,  2) [000047] -----------                         *  LCL_VAR   long   V06 tmp3         
new node is :                [000123] -----------                         *  PUTARG_REG long   REG x2

lowering arg : N012 (  3,  2) [000034] -----------                         *  LCL_VAR   ref    V00 this         
new node is :                [000124] -----------                         *  PUTARG_REG ref    REG x0

lowering arg : N013 (  3, 12) [000088] H----------                         *  CNS_INT(h) ref     'RunBasicScenario_Load'
new node is :                [000125] -----------                         *  PUTARG_REG ref    REG x4

results of lowering call:
N001 (  3, 12) [000126] H----------                  t126 =    CNS_INT(h) long   0x7ffac1def8b8 ftn
                                                            /--*  t126   long   
N002 (  6, 14) [000127] n---G------                  t127 = *  IND       long  
lowering call (after):
N009 (  3,  2) [000090] -----------                   t90 =    LCL_VAR   long   V07 tmp4         
                                                            /--*  t90    long   
               [000121] -----------                  t121 = *  PUTARG_REG long   REG x3
N010 (  3,  2) [000042] -----------                   t42 =    LCL_VAR   long   V05 tmp2         
                                                            /--*  t42    long   
               [000122] -----------                  t122 = *  PUTARG_REG long   REG x1
N011 (  3,  2) [000047] -----------                   t47 =    LCL_VAR   long   V06 tmp3         
                                                            /--*  t47    long   
               [000123] -----------                  t123 = *  PUTARG_REG long   REG x2
N012 (  3,  2) [000034] -----------                   t34 =    LCL_VAR   ref    V00 this         
                                                            /--*  t34    ref    
               [000124] -----------                  t124 = *  PUTARG_REG ref    REG x0
N013 (  3, 12) [000088] H----------                   t88 =    CNS_INT(h) ref     'RunBasicScenario_Load'
                                                            /--*  t88    ref    
               [000125] -----------                  t125 = *  PUTARG_REG ref    REG x4
N001 (  3, 12) [000126] H----------                  t126 =    CNS_INT(h) long   0x7ffac1def8b8 ftn
                                                            /--*  t126   long   
N002 (  6, 14) [000127] n---G------                  t127 = *  IND       long  
                                                            /--*  t121   long   arg3 in x3
                                                            +--*  t122   long   arg1 in x1
                                                            +--*  t123   long   arg2 in x2
                                                            +--*  t124   ref    this in x0
                                                            +--*  t125   ref    arg4 in x4
                                                            +--*  t127   long   control expr
N014 ( 59, 42) [000049] -ACXGO-----                         *  CALL      void   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:ValidateResult(ulong,ulong,ulong,System.String):this

lowering return node
N001 (  0,  0) [000050] -----------                         *  RETURN    void  
============
Lower has completed modifying nodes.

---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   [IL range]   [jump]                            [EH region]        [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    [000..078)                           (return)                     i LIR hascall gcsafe nullcheck
---------------------------------------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [0000] [000..078) (return), preds={} succs={}
               [000091] -----------                            IL_OFFSET void   INLRT @ 0x000[E-]
N001 (  3, 12) [000051] H----------                   t51 =    CNS_INT(h) ref     'RunBasicScenario_Load'
                                                            /--*  t51    ref    
               [000097] -----------                   t97 = *  PUTARG_REG ref    REG x0
N001 (  3, 12) [000098] H----------                   t98 =    CNS_INT(h) long   0x7ffac2114528 ftn
                                                            /--*  t98    long   
N002 (  6, 14) [000099] n---G------                   t99 = *  IND       long  
                                                            /--*  t97    ref    arg0 in x0
                                                            +--*  t99    long   control expr
N002 ( 17, 15) [000001] --CXG------                         *  CALL      void   TestLibrary.TestFramework:BeginScenario(System.String)
               [000092] -----------                            IL_OFFSET void   INLRT @ 0x00A[E-]
N001 (  1,  2) [000002] -c-----N---                    t2 =    CNS_INT   int    31
                                                            /--*  t2     int    
N002 (  2,  3) [000003] -----------                    t3 = *  HWINTRINSIC mask   int CreateTrueMaskInt32
                                                            /--*  t3     mask   
N003 (  3,  4) [000004] -----------                    t4 = *  HWINTRINSIC simd16 int ConvertMaskToVector
                                                            /--*  t4     simd16 
N004 (  7,  7) [000005] DA---------                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V01 loc0         
               [000093] -----------                            IL_OFFSET void   INLRT @ 0x012[E-]
N001 (  3,  2) [000052] -----------                   t52 =    LCL_VAR   ref    V00 this         
                                                            /--*  t52    ref    
N002 (  4,  3) [000053] ---X-O-----                         *  NULLCHECK byte  
N003 (  3,  2) [000054] -----------                   t54 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000055] -c---------                   t55 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t54    ref    
                                                            +--*  t55    long   
N005 (  5,  5) [000056] -----O-----                   t56 = *  ADD       byref 
                                                            /--*  t56    byref  
               [000100] -----O-----                  t100 = *  PUTARG_REG byref  REG x0
N001 (  3, 12) [000101] H----------                  t101 =    CNS_INT(h) long   0x7ffac1def648 ftn
                                                            /--*  t101   long   
N002 (  6, 14) [000102] n---G------                  t102 = *  IND       long  
                                                            /--*  t100   byref  this in x0
                                                            +--*  t102   long   control expr
N007 ( 23, 11) [000009] --CXGO-----                    t9 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
N008 (  3,  2) [000006] -----------                    t6 =    LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0         
N009 (  1,  1) [000011] -----------                   t11 =    HWINTRINSIC mask   int CreateTrueMaskAll
                                                            /--*  t11    mask   
                                                            +--*  t6     simd16 
N010 (  5,  4) [000012] -----------                   t12 = *  HWINTRINSIC mask   int ConvertVectorToMask
                                                            /--*  t12    mask   
                                                            +--*  t9     long   
N011 ( 29, 16) [000010] --CXGO-----                   t10 = *  HWINTRINSIC simd16 int LoadVector
                                                            /--*  t10    simd16 
N012 ( 33, 19) [000017] DACXGO-----                         *  STORE_LCL_VAR simd16 V04 tmp1         
N001 (  3,  2) [000058] -----------                   t58 =    LCL_VAR   ref    V00 this         
                                                            /--*  t58    ref    
N002 (  4,  3) [000059] ---X-O-----                         *  NULLCHECK byte  
N003 (  3,  2) [000060] -----------                   t60 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000061] -c---------                   t61 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t60    ref    
                                                            +--*  t61    long   
N005 (  5,  5) [000062] -----O-----                   t62 = *  ADD       byref 
                                                            /--*  t62    byref  
               [000103] -----O-----                  t103 = *  PUTARG_REG byref  REG x0
N001 (  3, 12) [000104] H----------                  t104 =    CNS_INT(h) long   0x7ffac1def660 ftn
                                                            /--*  t104   long   
N002 (  6, 14) [000105] n---G------                  t105 = *  IND       long  
                                                            /--*  t103   byref  this in x0
                                                            +--*  t105   long   control expr
N007 ( 23, 11) [000016] --CXGO-----                   t16 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
N008 (  3,  2) [000013] -----------                   t13 =    LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0         
N009 (  1,  1) [000020] -----------                   t20 =    HWINTRINSIC mask   int CreateTrueMaskAll
                                                            /--*  t20    mask   
                                                            +--*  t13    simd16 
N010 (  5,  4) [000021] -----------                   t21 = *  HWINTRINSIC mask   int ConvertVectorToMask
                                                            /--*  t21    mask   
                                                            +--*  t16    long   
N011 ( 29, 16) [000019] --CXGO-----                   t19 = *  HWINTRINSIC simd16 int LoadVector
N012 (  1,  1) [000025] -----------                   t25 =    HWINTRINSIC mask   int CreateTrueMaskAll
                                                            /--*  t25    mask   
                                                            +--*  t19    simd16 
N013 ( 31, 18) [000026] --CXGO-----                   t26 = *  HWINTRINSIC mask   int ConvertVectorToMask
N014 (  3,  2) [000018] -----------                   t18 =    LCL_VAR   simd16 V04 tmp1         
N015 (  1,  1) [000023] -----------                   t23 =    HWINTRINSIC mask   int CreateTrueMaskAll
                                                            /--*  t23    mask   
                                                            +--*  t18    simd16 
N016 (  5,  4) [000024] -----------                   t24 = *  HWINTRINSIC mask   int ConvertVectorToMask
               [000106] -----------                  t106 =    HWINTRINSIC mask   int CreateTrueMaskAll
               [000107] -c---------                  t107 =    CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000>
                                                            /--*  t24    mask   
                                                            +--*  t26    mask   
N017 ( 37, 23) [000022] -cCXGO-----                   t22 = *  HWINTRINSIC mask   int CreateBreakPropagateMask
                                                            /--*  t106   mask   
                                                            +--*  t22    mask   
                                                            +--*  t107   simd16 
               [000108] --CXGO-----                  t108 = *  HWINTRINSIC mask   int ConditionalSelect
                                                            /--*  t108   mask   
N018 ( 38, 24) [000027] --CXGO-----                   t27 = *  HWINTRINSIC simd16 int ConvertMaskToVector
                                                            /--*  t27    simd16 
N019 ( 42, 27) [000028] DACXGO-----                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V02 loc1         
               [000094] -----------                            IL_OFFSET void   INLRT @ 0x03A[E-]
N001 (  3,  2) [000064] -----------                   t64 =    LCL_VAR   ref    V00 this         
                                                            /--*  t64    ref    
N002 (  4,  3) [000065] ---X-O-----                         *  NULLCHECK byte  
N003 (  3,  2) [000066] -----------                   t66 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000067] -c---------                   t67 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t66    ref    
                                                            +--*  t67    long   
N005 (  5,  5) [000068] -----O-----                   t68 = *  ADD       byref 
                                                            /--*  t68    byref  
               [000109] -----O-----                  t109 = *  PUTARG_REG byref  REG x0
N001 (  3, 12) [000110] H----------                  t110 =    CNS_INT(h) long   0x7ffac1def678 ftn
                                                            /--*  t110   long   
N002 (  6, 14) [000111] n---G------                  t111 = *  IND       long  
                                                            /--*  t109   byref  this in x0
                                                            +--*  t111   long   control expr
N007 ( 23, 11) [000031] --CXGO-----                   t31 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
N008 (  3,  2) [000032] -----------                   t32 =    LCL_VAR   simd16<System.Numerics.Vector`1> V02 loc1         
                                                            /--*  t31    long   
                                                            +--*  t32    simd16 
N009 ( 30, 16) [000033] -ACXGO-----                         *  STOREIND  simd16 (copy)
               [000095] -----------                            IL_OFFSET void   INLRT @ 0x04B[E-]
N001 (  3,  2) [000070] -----------                   t70 =    LCL_VAR   ref    V00 this         
                                                            /--*  t70    ref    
N002 (  4,  3) [000071] ---X-O-----                         *  NULLCHECK byte  
N003 (  3,  2) [000072] -----------                   t72 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000073] -c---------                   t73 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t72    ref    
                                                            +--*  t73    long   
N005 (  5,  5) [000074] -----O-----                   t74 = *  ADD       byref 
                                                            /--*  t74    byref  
               [000112] -----O-----                  t112 = *  PUTARG_REG byref  REG x0
N001 (  3, 12) [000113] H----------                  t113 =    CNS_INT(h) long   0x7ffac1def648 ftn
                                                            /--*  t113   long   
N002 (  6, 14) [000114] n---G------                  t114 = *  IND       long  
                                                            /--*  t112   byref  this in x0
                                                            +--*  t114   long   control expr
N007 ( 23, 11) [000037] --CXGO-----                   t37 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
                                                            /--*  t37    long   
N008 ( 27, 14) [000041] DACXGO-----                         *  STORE_LCL_VAR long   V05 tmp2         
N001 (  3,  2) [000076] -----------                   t76 =    LCL_VAR   ref    V00 this         
                                                            /--*  t76    ref    
N002 (  4,  3) [000077] ---X-O-----                         *  NULLCHECK byte  
N003 (  3,  2) [000078] -----------                   t78 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000079] -c---------                   t79 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t78    ref    
                                                            +--*  t79    long   
N005 (  5,  5) [000080] -----O-----                   t80 = *  ADD       byref 
                                                            /--*  t80    byref  
               [000115] -----O-----                  t115 = *  PUTARG_REG byref  REG x0
N001 (  3, 12) [000116] H----------                  t116 =    CNS_INT(h) long   0x7ffac1def660 ftn
                                                            /--*  t116   long   
N002 (  6, 14) [000117] n---G------                  t117 = *  IND       long  
                                                            /--*  t115   byref  this in x0
                                                            +--*  t117   long   control expr
N007 ( 23, 11) [000040] --CXGO-----                   t40 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
                                                            /--*  t40    long   
N008 ( 27, 14) [000046] DACXGO-----                         *  STORE_LCL_VAR long   V06 tmp3         
N001 (  3,  2) [000082] -----------                   t82 =    LCL_VAR   ref    V00 this         
                                                            /--*  t82    ref    
N002 (  4,  3) [000083] ---X-O-----                         *  NULLCHECK byte  
N003 (  3,  2) [000084] -----------                   t84 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000085] -c---------                   t85 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t84    ref    
                                                            +--*  t85    long   
N005 (  5,  5) [000086] -----O-----                   t86 = *  ADD       byref 
                                                            /--*  t86    byref  
               [000118] -----O-----                  t118 = *  PUTARG_REG byref  REG x0
N001 (  3, 12) [000119] H----------                  t119 =    CNS_INT(h) long   0x7ffac1def678 ftn
                                                            /--*  t119   long   
N002 (  6, 14) [000120] n---G------                  t120 = *  IND       long  
                                                            /--*  t118   byref  this in x0
                                                            +--*  t120   long   control expr
N007 ( 23, 11) [000045] --CXGO-----                   t45 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
                                                            /--*  t45    long   
N008 ( 27, 14) [000089] DACXGO-----                         *  STORE_LCL_VAR long   V07 tmp4         
N009 (  3,  2) [000090] -----------                   t90 =    LCL_VAR   long   V07 tmp4         
                                                            /--*  t90    long   
               [000121] -----------                  t121 = *  PUTARG_REG long   REG x3
N010 (  3,  2) [000042] -----------                   t42 =    LCL_VAR   long   V05 tmp2         
                                                            /--*  t42    long   
               [000122] -----------                  t122 = *  PUTARG_REG long   REG x1
N011 (  3,  2) [000047] -----------                   t47 =    LCL_VAR   long   V06 tmp3         
                                                            /--*  t47    long   
               [000123] -----------                  t123 = *  PUTARG_REG long   REG x2
N012 (  3,  2) [000034] -----------                   t34 =    LCL_VAR   ref    V00 this         
                                                            /--*  t34    ref    
               [000124] -----------                  t124 = *  PUTARG_REG ref    REG x0
N013 (  3, 12) [000088] H----------                   t88 =    CNS_INT(h) ref     'RunBasicScenario_Load'
                                                            /--*  t88    ref    
               [000125] -----------                  t125 = *  PUTARG_REG ref    REG x4
N001 (  3, 12) [000126] H----------                  t126 =    CNS_INT(h) long   0x7ffac1def8b8 ftn
                                                            /--*  t126   long   
N002 (  6, 14) [000127] n---G------                  t127 = *  IND       long  
                                                            /--*  t121   long   arg3 in x3
                                                            +--*  t122   long   arg1 in x1
                                                            +--*  t123   long   arg2 in x2
                                                            +--*  t124   ref    this in x0
                                                            +--*  t125   ref    arg4 in x4
                                                            +--*  t127   long   control expr
N014 ( 59, 42) [000049] -ACXGO-----                         *  CALL      void   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:ValidateResult(ulong,ulong,ulong,System.String):this
               [000096] -----------                            IL_OFFSET void   INLRT @ 0x077[E-]
N001 (  0,  0) [000050] -----------                            RETURN    void  

-------------------------------------------------------------------------------------------------------------------

*** lvaComputeRefCounts ***

*************** Finishing PHASE Lowering nodeinfo
Trees after Lowering nodeinfo

---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   [IL range]   [jump]                            [EH region]        [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    [000..078)                           (return)                     i LIR hascall gcsafe nullcheck
---------------------------------------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [0000] [000..078) (return), preds={} succs={}
               [000091] -----------                            IL_OFFSET void   INLRT @ 0x000[E-]
N001 (  3, 12) [000051] H----------                   t51 =    CNS_INT(h) ref     'RunBasicScenario_Load'
                                                            /--*  t51    ref    
               [000097] -----------                   t97 = *  PUTARG_REG ref    REG x0
N001 (  3, 12) [000098] H----------                   t98 =    CNS_INT(h) long   0x7ffac2114528 ftn
                                                            /--*  t98    long   
N002 (  6, 14) [000099] n---G------                   t99 = *  IND       long  
                                                            /--*  t97    ref    arg0 in x0
                                                            +--*  t99    long   control expr
N002 ( 17, 15) [000001] --CXG------                         *  CALL      void   TestLibrary.TestFramework:BeginScenario(System.String)
               [000092] -----------                            IL_OFFSET void   INLRT @ 0x00A[E-]
N001 (  1,  2) [000002] -c-----N---                    t2 =    CNS_INT   int    31
                                                            /--*  t2     int    
N002 (  2,  3) [000003] -----------                    t3 = *  HWINTRINSIC mask   int CreateTrueMaskInt32
                                                            /--*  t3     mask   
N003 (  3,  4) [000004] -----------                    t4 = *  HWINTRINSIC simd16 int ConvertMaskToVector
                                                            /--*  t4     simd16 
N004 (  7,  7) [000005] DA---------                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V01 loc0         
               [000093] -----------                            IL_OFFSET void   INLRT @ 0x012[E-]
N001 (  3,  2) [000052] -----------                   t52 =    LCL_VAR   ref    V00 this         
                                                            /--*  t52    ref    
N002 (  4,  3) [000053] ---X-O-----                         *  NULLCHECK byte  
N003 (  3,  2) [000054] -----------                   t54 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000055] -c---------                   t55 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t54    ref    
                                                            +--*  t55    long   
N005 (  5,  5) [000056] -----O-----                   t56 = *  ADD       byref 
                                                            /--*  t56    byref  
               [000100] -----O-----                  t100 = *  PUTARG_REG byref  REG x0
N001 (  3, 12) [000101] H----------                  t101 =    CNS_INT(h) long   0x7ffac1def648 ftn
                                                            /--*  t101   long   
N002 (  6, 14) [000102] n---G------                  t102 = *  IND       long  
                                                            /--*  t100   byref  this in x0
                                                            +--*  t102   long   control expr
N007 ( 23, 11) [000009] --CXGO-----                    t9 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
N008 (  3,  2) [000006] -----------                    t6 =    LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0         
N009 (  1,  1) [000011] -----------                   t11 =    HWINTRINSIC mask   int CreateTrueMaskAll
                                                            /--*  t11    mask   
                                                            +--*  t6     simd16 
N010 (  5,  4) [000012] -----------                   t12 = *  HWINTRINSIC mask   int ConvertVectorToMask
                                                            /--*  t12    mask   
                                                            +--*  t9     long   
N011 ( 29, 16) [000010] --CXGO-----                   t10 = *  HWINTRINSIC simd16 int LoadVector
                                                            /--*  t10    simd16 
N012 ( 33, 19) [000017] DACXGO-----                         *  STORE_LCL_VAR simd16 V04 tmp1         
N001 (  3,  2) [000058] -----------                   t58 =    LCL_VAR   ref    V00 this         
                                                            /--*  t58    ref    
N002 (  4,  3) [000059] ---X-O-----                         *  NULLCHECK byte  
N003 (  3,  2) [000060] -----------                   t60 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000061] -c---------                   t61 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t60    ref    
                                                            +--*  t61    long   
N005 (  5,  5) [000062] -----O-----                   t62 = *  ADD       byref 
                                                            /--*  t62    byref  
               [000103] -----O-----                  t103 = *  PUTARG_REG byref  REG x0
N001 (  3, 12) [000104] H----------                  t104 =    CNS_INT(h) long   0x7ffac1def660 ftn
                                                            /--*  t104   long   
N002 (  6, 14) [000105] n---G------                  t105 = *  IND       long  
                                                            /--*  t103   byref  this in x0
                                                            +--*  t105   long   control expr
N007 ( 23, 11) [000016] --CXGO-----                   t16 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
N008 (  3,  2) [000013] -----------                   t13 =    LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0         
N009 (  1,  1) [000020] -----------                   t20 =    HWINTRINSIC mask   int CreateTrueMaskAll
                                                            /--*  t20    mask   
                                                            +--*  t13    simd16 
N010 (  5,  4) [000021] -----------                   t21 = *  HWINTRINSIC mask   int ConvertVectorToMask
                                                            /--*  t21    mask   
                                                            +--*  t16    long   
N011 ( 29, 16) [000019] --CXGO-----                   t19 = *  HWINTRINSIC simd16 int LoadVector
N012 (  1,  1) [000025] -----------                   t25 =    HWINTRINSIC mask   int CreateTrueMaskAll
                                                            /--*  t25    mask   
                                                            +--*  t19    simd16 
N013 ( 31, 18) [000026] --CXGO-----                   t26 = *  HWINTRINSIC mask   int ConvertVectorToMask
N014 (  3,  2) [000018] -----------                   t18 =    LCL_VAR   simd16 V04 tmp1         
N015 (  1,  1) [000023] -----------                   t23 =    HWINTRINSIC mask   int CreateTrueMaskAll
                                                            /--*  t23    mask   
                                                            +--*  t18    simd16 
N016 (  5,  4) [000024] -----------                   t24 = *  HWINTRINSIC mask   int ConvertVectorToMask
               [000106] -----------                  t106 =    HWINTRINSIC mask   int CreateTrueMaskAll
               [000107] -c---------                  t107 =    CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000>
                                                            /--*  t24    mask   
                                                            +--*  t26    mask   
N017 ( 37, 23) [000022] -cCXGO-----                   t22 = *  HWINTRINSIC mask   int CreateBreakPropagateMask
                                                            /--*  t106   mask   
                                                            +--*  t22    mask   
                                                            +--*  t107   simd16 
               [000108] --CXGO-----                  t108 = *  HWINTRINSIC mask   int ConditionalSelect
                                                            /--*  t108   mask   
N018 ( 38, 24) [000027] --CXGO-----                   t27 = *  HWINTRINSIC simd16 int ConvertMaskToVector
                                                            /--*  t27    simd16 
N019 ( 42, 27) [000028] DACXGO-----                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V02 loc1         
               [000094] -----------                            IL_OFFSET void   INLRT @ 0x03A[E-]
N001 (  3,  2) [000064] -----------                   t64 =    LCL_VAR   ref    V00 this         
                                                            /--*  t64    ref    
N002 (  4,  3) [000065] ---X-O-----                         *  NULLCHECK byte  
N003 (  3,  2) [000066] -----------                   t66 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000067] -c---------                   t67 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t66    ref    
                                                            +--*  t67    long   
N005 (  5,  5) [000068] -----O-----                   t68 = *  ADD       byref 
                                                            /--*  t68    byref  
               [000109] -----O-----                  t109 = *  PUTARG_REG byref  REG x0
N001 (  3, 12) [000110] H----------                  t110 =    CNS_INT(h) long   0x7ffac1def678 ftn
                                                            /--*  t110   long   
N002 (  6, 14) [000111] n---G------                  t111 = *  IND       long  
                                                            /--*  t109   byref  this in x0
                                                            +--*  t111   long   control expr
N007 ( 23, 11) [000031] --CXGO-----                   t31 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
N008 (  3,  2) [000032] -----------                   t32 =    LCL_VAR   simd16<System.Numerics.Vector`1> V02 loc1         
                                                            /--*  t31    long   
                                                            +--*  t32    simd16 
N009 ( 30, 16) [000033] -ACXGO-----                         *  STOREIND  simd16 (copy)
               [000095] -----------                            IL_OFFSET void   INLRT @ 0x04B[E-]
N001 (  3,  2) [000070] -----------                   t70 =    LCL_VAR   ref    V00 this         
                                                            /--*  t70    ref    
N002 (  4,  3) [000071] ---X-O-----                         *  NULLCHECK byte  
N003 (  3,  2) [000072] -----------                   t72 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000073] -c---------                   t73 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t72    ref    
                                                            +--*  t73    long   
N005 (  5,  5) [000074] -----O-----                   t74 = *  ADD       byref 
                                                            /--*  t74    byref  
               [000112] -----O-----                  t112 = *  PUTARG_REG byref  REG x0
N001 (  3, 12) [000113] H----------                  t113 =    CNS_INT(h) long   0x7ffac1def648 ftn
                                                            /--*  t113   long   
N002 (  6, 14) [000114] n---G------                  t114 = *  IND       long  
                                                            /--*  t112   byref  this in x0
                                                            +--*  t114   long   control expr
N007 ( 23, 11) [000037] --CXGO-----                   t37 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
                                                            /--*  t37    long   
N008 ( 27, 14) [000041] DACXGO-----                         *  STORE_LCL_VAR long   V05 tmp2         
N001 (  3,  2) [000076] -----------                   t76 =    LCL_VAR   ref    V00 this         
                                                            /--*  t76    ref    
N002 (  4,  3) [000077] ---X-O-----                         *  NULLCHECK byte  
N003 (  3,  2) [000078] -----------                   t78 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000079] -c---------                   t79 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t78    ref    
                                                            +--*  t79    long   
N005 (  5,  5) [000080] -----O-----                   t80 = *  ADD       byref 
                                                            /--*  t80    byref  
               [000115] -----O-----                  t115 = *  PUTARG_REG byref  REG x0
N001 (  3, 12) [000116] H----------                  t116 =    CNS_INT(h) long   0x7ffac1def660 ftn
                                                            /--*  t116   long   
N002 (  6, 14) [000117] n---G------                  t117 = *  IND       long  
                                                            /--*  t115   byref  this in x0
                                                            +--*  t117   long   control expr
N007 ( 23, 11) [000040] --CXGO-----                   t40 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
                                                            /--*  t40    long   
N008 ( 27, 14) [000046] DACXGO-----                         *  STORE_LCL_VAR long   V06 tmp3         
N001 (  3,  2) [000082] -----------                   t82 =    LCL_VAR   ref    V00 this         
                                                            /--*  t82    ref    
N002 (  4,  3) [000083] ---X-O-----                         *  NULLCHECK byte  
N003 (  3,  2) [000084] -----------                   t84 =    LCL_VAR   ref    V00 this         
N004 (  1,  2) [000085] -c---------                   t85 =    CNS_INT   long   80 Fseq[_dataTable]
                                                            /--*  t84    ref    
                                                            +--*  t85    long   
N005 (  5,  5) [000086] -----O-----                   t86 = *  ADD       byref 
                                                            /--*  t86    byref  
               [000118] -----O-----                  t118 = *  PUTARG_REG byref  REG x0
N001 (  3, 12) [000119] H----------                  t119 =    CNS_INT(h) long   0x7ffac1def678 ftn
                                                            /--*  t119   long   
N002 (  6, 14) [000120] n---G------                  t120 = *  IND       long  
                                                            /--*  t118   byref  this in x0
                                                            +--*  t120   long   control expr
N007 ( 23, 11) [000045] --CXGO-----                   t45 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
                                                            /--*  t45    long   
N008 ( 27, 14) [000089] DACXGO-----                         *  STORE_LCL_VAR long   V07 tmp4         
N009 (  3,  2) [000090] -----------                   t90 =    LCL_VAR   long   V07 tmp4         
                                                            /--*  t90    long   
               [000121] -----------                  t121 = *  PUTARG_REG long   REG x3
N010 (  3,  2) [000042] -----------                   t42 =    LCL_VAR   long   V05 tmp2         
                                                            /--*  t42    long   
               [000122] -----------                  t122 = *  PUTARG_REG long   REG x1
N011 (  3,  2) [000047] -----------                   t47 =    LCL_VAR   long   V06 tmp3         
                                                            /--*  t47    long   
               [000123] -----------                  t123 = *  PUTARG_REG long   REG x2
N012 (  3,  2) [000034] -----------                   t34 =    LCL_VAR   ref    V00 this         
                                                            /--*  t34    ref    
               [000124] -----------                  t124 = *  PUTARG_REG ref    REG x0
N013 (  3, 12) [000088] H----------                   t88 =    CNS_INT(h) ref     'RunBasicScenario_Load'
                                                            /--*  t88    ref    
               [000125] -----------                  t125 = *  PUTARG_REG ref    REG x4
N001 (  3, 12) [000126] H----------                  t126 =    CNS_INT(h) long   0x7ffac1def8b8 ftn
                                                            /--*  t126   long   
N002 (  6, 14) [000127] n---G------                  t127 = *  IND       long  
                                                            /--*  t121   long   arg3 in x3
                                                            +--*  t122   long   arg1 in x1
                                                            +--*  t123   long   arg2 in x2
                                                            +--*  t124   ref    this in x0
                                                            +--*  t125   ref    arg4 in x4
                                                            +--*  t127   long   control expr
N014 ( 59, 42) [000049] -ACXGO-----                         *  CALL      void   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:ValidateResult(ulong,ulong,ulong,System.String):this
               [000096] -----------                            IL_OFFSET void   INLRT @ 0x077[E-]
N001 (  0,  0) [000050] -----------                            RETURN    void  

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]

*************** Starting PHASE Calculate stack level slots

*************** Finishing PHASE Calculate stack level slots [no changes]

*************** Starting PHASE Linear scan register alloc
Clearing modified regs.

buildIntervals ========

-----------------
LIVENESS:
-----------------
BB01
use: {}
def: {}
 in: {}
out: {}

FP callee save candidate vars: None

floatVarCount = 0; hasLoops = false, singleExit = true
; Decided to create an EBP based frame for ETW stackwalking (Debug Code)
*************** In lvaAssignFrameOffsets(REGALLOC_FRAME_LAYOUT)
Setting genSaveFpLrWithAllCalleeSavedRegisters to false
Pad V00 this, size=8, stkOffs=-0x97, pad=7
Assign V00 this, size=8, stkOffs=-0x9f
Pad V01 loc0, size=16, stkOffs=-0xae, pad=15
Assign V01 loc0, size=16, stkOffs=-0xbe
Pad V02 loc1, size=16, stkOffs=-0xcd, pad=15
Assign V02 loc1, size=16, stkOffs=-0xdd
Pad V04 tmp1, size=16, stkOffs=-0xec, pad=15
Assign V04 tmp1, size=16, stkOffs=-0xfc
Pad V05 tmp2, size=8, stkOffs=-0x103, pad=7
Assign V05 tmp2, size=8, stkOffs=-0x10b
Pad V06 tmp3, size=8, stkOffs=-0x112, pad=7
Assign V06 tmp3, size=8, stkOffs=-0x11a
Pad V07 tmp4, size=8, stkOffs=-0x121, pad=7
Assign V07 tmp4, size=8, stkOffs=-0x129
--- delta bump 352 for FP frame
--- virtual stack offset to actual stack offset delta is 352
-- V00 was -159, now 193
-- V01 was -190, now 162
-- V02 was -221, now 131
-- V03 was 0, now 352
-- V04 was -252, now 100
-- V05 was -267, now 85
-- V06 was -282, now 70
-- V07 was -297, now 55

compRsvdRegCheck
  frame size  =    352
  compArgSize =      8
 Returning true (MinOpts)

  Reserved REG_OPT_RSVD (xip1) due to large frame
TUPLE STYLE DUMP BEFORE LSRA
Start LSRA Block Sequence: 
Current block: BB01
Final LSRA Block Sequence:
BB01 (  1   )

BB01 [0000] [000..078) (return), preds={} succs={}
=====
  N000.                    IL_OFFSET INLRT @ 0x000[E-]
  N001. t51             =  CNS_INT(h)  'RunBasicScenario_Load'
  N000. t97             =  PUTARG_REG; t51
  N001. t98             =  CNS_INT(h) 0x7ffac2114528 ftn
  N002. t99             =  IND      ; t98
  N002.                    CALL     ; t97,t99
  N000.                    IL_OFFSET INLRT @ 0x00A[E-]
  N001.                    CNS_INT   31
  N002. t3              =  HWINTRINSIC
  N003. t4              =  HWINTRINSIC; t3
  N004.                    V01 MEM; t4
  N000.                    IL_OFFSET INLRT @ 0x012[E-]
  N001. t52             =  V00 MEM
  N002.                    NULLCHECK; t52
  N003. t54             =  V00 MEM
  N004.                    CNS_INT   80 Fseq[_dataTable]
  N005. t56             =  ADD      ; t54
  N000. t100            =  PUTARG_REG; t56
  N001. t101            =  CNS_INT(h) 0x7ffac1def648 ftn
  N002. t102            =  IND      ; t101
  N007. t9              =  CALL     ; t100,t102
  N008. t6              =  V01 MEM
  N009. t11             =  HWINTRINSIC
  N010. t12             =  HWINTRINSIC; t11,t6
  N011. t10             =  HWINTRINSIC; t12,t9
  N012.                    V04 MEM; t10
  N001. t58             =  V00 MEM
  N002.                    NULLCHECK; t58
  N003. t60             =  V00 MEM
  N004.                    CNS_INT   80 Fseq[_dataTable]
  N005. t62             =  ADD      ; t60
  N000. t103            =  PUTARG_REG; t62
  N001. t104            =  CNS_INT(h) 0x7ffac1def660 ftn
  N002. t105            =  IND      ; t104
  N007. t16             =  CALL     ; t103,t105
  N008. t13             =  V01 MEM
  N009. t20             =  HWINTRINSIC
  N010. t21             =  HWINTRINSIC; t20,t13
  N011. t19             =  HWINTRINSIC; t21,t16
  N012. t25             =  HWINTRINSIC
  N013. t26             =  HWINTRINSIC; t25,t19
  N014. t18             =  V04 MEM
  N015. t23             =  HWINTRINSIC
  N016. t24             =  HWINTRINSIC; t23,t18
  N000. t106            =  HWINTRINSIC
  N000.                    CNS_VEC  <0x00000000, 0x00000000, 0x00000000, 0x00000000>
  N017. t22             =  HWINTRINSIC; t24,t26
  N000. t108            =  HWINTRINSIC; t106,t22
  N018. t27             =  HWINTRINSIC; t108
  N019.                    V02 MEM; t27
  N000.                    IL_OFFSET INLRT @ 0x03A[E-]
  N001. t64             =  V00 MEM
  N002.                    NULLCHECK; t64
  N003. t66             =  V00 MEM
  N004.                    CNS_INT   80 Fseq[_dataTable]
  N005. t68             =  ADD      ; t66
  N000. t109            =  PUTARG_REG; t68
  N001. t110            =  CNS_INT(h) 0x7ffac1def678 ftn
  N002. t111            =  IND      ; t110
  N007. t31             =  CALL     ; t109,t111
  N008. t32             =  V02 MEM
  N009.                    STOREIND ; t31,t32
  N000.                    IL_OFFSET INLRT @ 0x04B[E-]
  N001. t70             =  V00 MEM
  N002.                    NULLCHECK; t70
  N003. t72             =  V00 MEM
  N004.                    CNS_INT   80 Fseq[_dataTable]
  N005. t74             =  ADD      ; t72
  N000. t112            =  PUTARG_REG; t74
  N001. t113            =  CNS_INT(h) 0x7ffac1def648 ftn
  N002. t114            =  IND      ; t113
  N007. t37             =  CALL     ; t112,t114
  N008.                    V05 MEM; t37
  N001. t76             =  V00 MEM
  N002.                    NULLCHECK; t76
  N003. t78             =  V00 MEM
  N004.                    CNS_INT   80 Fseq[_dataTable]
  N005. t80             =  ADD      ; t78
  N000. t115            =  PUTARG_REG; t80
  N001. t116            =  CNS_INT(h) 0x7ffac1def660 ftn
  N002. t117            =  IND      ; t116
  N007. t40             =  CALL     ; t115,t117
  N008.                    V06 MEM; t40
  N001. t82             =  V00 MEM
  N002.                    NULLCHECK; t82
  N003. t84             =  V00 MEM
  N004.                    CNS_INT   80 Fseq[_dataTable]
  N005. t86             =  ADD      ; t84
  N000. t118            =  PUTARG_REG; t86
  N001. t119            =  CNS_INT(h) 0x7ffac1def678 ftn
  N002. t120            =  IND      ; t119
  N007. t45             =  CALL     ; t118,t120
  N008.                    V07 MEM; t45
  N009. t90             =  V07 MEM
  N000. t121            =  PUTARG_REG; t90
  N010. t42             =  V05 MEM
  N000. t122            =  PUTARG_REG; t42
  N011. t47             =  V06 MEM
  N000. t123            =  PUTARG_REG; t47
  N012. t34             =  V00 MEM
  N000. t124            =  PUTARG_REG; t34
  N013. t88             =  CNS_INT(h)  'RunBasicScenario_Load'
  N000. t125            =  PUTARG_REG; t88
  N001. t126            =  CNS_INT(h) 0x7ffac1def8b8 ftn
  N002. t127            =  IND      ; t126
  N014.                    CALL     ; t121,t122,t123,t124,t125,t127
  N000.                    IL_OFFSET INLRT @ 0x077[E-]
  N001.                    RETURN   




buildIntervals second part ========
Int arg V00 in reg x0

NEW BLOCK BB01
<RefPosition #0   @0   RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>

DefList: {  }
N002 (???,???) [000091] -----------                         *  IL_OFFSET void   INLRT @ 0x000[E-] REG NA

DefList: {  }
N004 (  3, 12) [000051] H----------                         *  CNS_INT(h) ref     'RunBasicScenario_Load' REG NA
Interval  0: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #1   @5   RefTypeDef <Ivl:0> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N004.t51. CNS_INT }
N006 (???,???) [000097] -----------                         *  PUTARG_REG ref    REG x0
<RefPosition #2   @6   RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #3   @6   RefTypeUse <Ivl:0> BB01 regmask=[x0] minReg=1 last fixed wt=100.00>
Interval  1: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #4   @7   RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #5   @7   RefTypeDef <Ivl:1> PUTARG_REG BB01 regmask=[x0] minReg=1 fixed wt=400.00>

DefList: { N006.t97. PUTARG_REG }
N008 (  3, 12) [000098] H----------                         *  CNS_INT(h) long   0x7ffac2114528 ftn REG NA
Interval  2: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #6   @9   RefTypeDef <Ivl:2> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N006.t97. PUTARG_REG; N008.t98. CNS_INT }
N010 (  6, 14) [000099] n---G------                         *  IND       long   REG NA
<RefPosition #7   @10  RefTypeUse <Ivl:2> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
Interval  3: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #8   @11  RefTypeDef <Ivl:3> IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N006.t97. PUTARG_REG; N010.t99. IND }
N012 ( 17, 15) [000001] --CXG------                         *  CALL      void   TestLibrary.TestFramework:BeginScenario(System.String) REG NA
<RefPosition #9   @12  RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #10  @12  RefTypeUse <Ivl:1> BB01 regmask=[x0] minReg=1 last fixed wt=100.00>
<RefPosition #11  @12  RefTypeUse <Ivl:3> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #12  @13  RefTypeKill BB01 regmask=[x0-xip1 lr d0-d7 d16-d31] minReg=1>

DefList: {  }
N014 (???,???) [000092] -----------                         *  IL_OFFSET void   INLRT @ 0x00A[E-] REG NA

DefList: {  }
N016 (  1,  2) [000002] -c-----N---                         *  CNS_INT   int    31 REG NA
Contained
DefList: {  }
N018 (  2,  3) [000003] -----------                         *  HWINTRINSIC mask   int CreateTrueMaskInt32 REG NA
Interval  4: mask RefPositions {} physReg:NA Preferences=[allMask] Aversions=[]
<RefPosition #13  @19  RefTypeDef <Ivl:4> HWINTRINSIC BB01 regmask=[allMask] minReg=1 wt=400.00>

DefList: { N018.t3. HWINTRINSIC }
N020 (  3,  4) [000004] -----------                         *  HWINTRINSIC simd16 int ConvertMaskToVector REG NA
<RefPosition #14  @20  RefTypeUse <Ivl:4> BB01 regmask=[allMask] minReg=1 last wt=100.00>
Interval  5: simd16 RefPositions {} physReg:NA Preferences=[allFloat] Aversions=[]
<RefPosition #15  @21  RefTypeDef <Ivl:5> HWINTRINSIC BB01 regmask=[allFloat] minReg=1 wt=400.00>

DefList: { N020.t4. HWINTRINSIC }
N022 (  7,  7) [000005] DA---------                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V01 loc0          NA REG NA
<RefPosition #16  @22  RefTypeUse <Ivl:5> BB01 regmask=[allFloat] minReg=1 last wt=100.00>

DefList: {  }
N024 (???,???) [000093] -----------                         *  IL_OFFSET void   INLRT @ 0x012[E-] REG NA

DefList: {  }
N026 (  3,  2) [000052] -----------                         *  LCL_VAR   ref    V00 this          NA REG NA
Interval  6: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #17  @27  RefTypeDef <Ivl:6> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N026.t52. LCL_VAR }
N028 (  4,  3) [000053] ---X-O-----                         *  NULLCHECK byte   REG NA
<RefPosition #18  @28  RefTypeUse <Ivl:6> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>

DefList: {  }
N030 (  3,  2) [000054] -----------                         *  LCL_VAR   ref    V00 this          NA REG NA
Interval  7: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #19  @31  RefTypeDef <Ivl:7> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N030.t54. LCL_VAR }
N032 (  1,  2) [000055] -c---------                         *  CNS_INT   long   80 Fseq[_dataTable] REG NA
Contained
DefList: { N030.t54. LCL_VAR }
N034 (  5,  5) [000056] -----O-----                         *  ADD       byref  REG NA
<RefPosition #20  @34  RefTypeUse <Ivl:7> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
Interval  8: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #21  @35  RefTypeDef <Ivl:8> ADD BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N034.t56. ADD }
N036 (???,???) [000100] -----O-----                         *  PUTARG_REG byref  REG x0
<RefPosition #22  @36  RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #23  @36  RefTypeUse <Ivl:8> BB01 regmask=[x0] minReg=1 last fixed wt=100.00>
Interval  9: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #24  @37  RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #25  @37  RefTypeDef <Ivl:9> PUTARG_REG BB01 regmask=[x0] minReg=1 fixed wt=400.00>

DefList: { N036.t100. PUTARG_REG }
N038 (  3, 12) [000101] H----------                         *  CNS_INT(h) long   0x7ffac1def648 ftn REG NA
Interval 10: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #26  @39  RefTypeDef <Ivl:10> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N036.t100. PUTARG_REG; N038.t101. CNS_INT }
N040 (  6, 14) [000102] n---G------                         *  IND       long   REG NA
<RefPosition #27  @40  RefTypeUse <Ivl:10> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
Interval 11: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #28  @41  RefTypeDef <Ivl:11> IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N036.t100. PUTARG_REG; N040.t102. IND }
N042 ( 23, 11) [000009] --CXGO-----                         *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this REG NA
<RefPosition #29  @42  RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #30  @42  RefTypeUse <Ivl:9> BB01 regmask=[x0] minReg=1 last fixed wt=100.00>
<RefPosition #31  @42  RefTypeUse <Ivl:11> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #32  @43  RefTypeKill BB01 regmask=[x0-xip1 lr d0-d7 d16-d31] minReg=1>
Interval 12: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #33  @43  RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #34  @43  RefTypeDef <Ivl:12> CALL BB01 regmask=[x0] minReg=1 fixed wt=400.00>

DefList: { N042.t9. CALL }
N044 (  3,  2) [000006] -----------                         *  LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0          NA REG NA
Interval 13: simd16 RefPositions {} physReg:NA Preferences=[allFloat] Aversions=[]
<RefPosition #35  @45  RefTypeDef <Ivl:13> LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=400.00>

DefList: { N042.t9. CALL; N044.t6. LCL_VAR }
N046 (  1,  1) [000011] -----------                         *  HWINTRINSIC mask   int CreateTrueMaskAll REG NA
Interval 14: mask RefPositions {} physReg:NA Preferences=[allMask] Aversions=[]
<RefPosition #36  @47  RefTypeDef <Ivl:14> HWINTRINSIC BB01 regmask=[allMask] minReg=1 wt=400.00>

DefList: { N042.t9. CALL; N044.t6. LCL_VAR; N046.t11. HWINTRINSIC }
N048 (  5,  4) [000012] -----------                         *  HWINTRINSIC mask   int ConvertVectorToMask REG NA
<RefPosition #37  @48  RefTypeUse <Ivl:14> BB01 regmask=[p0-p7] minReg=1 last wt=100.00>
<RefPosition #38  @48  RefTypeUse <Ivl:13> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
Interval 15: mask RefPositions {} physReg:NA Preferences=[allMask] Aversions=[]
<RefPosition #39  @49  RefTypeDef <Ivl:15> HWINTRINSIC BB01 regmask=[allMask] minReg=1 wt=400.00>

DefList: { N042.t9. CALL; N048.t12. HWINTRINSIC }
N050 ( 29, 16) [000010] --CXGO-----                         *  HWINTRINSIC simd16 int LoadVector REG NA
<RefPosition #40  @50  RefTypeUse <Ivl:15> BB01 regmask=[p0-p7] minReg=1 last wt=100.00>
<RefPosition #41  @50  RefTypeUse <Ivl:12> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
Interval 16: simd16 RefPositions {} physReg:NA Preferences=[allFloat] Aversions=[]
<RefPosition #42  @51  RefTypeDef <Ivl:16> HWINTRINSIC BB01 regmask=[allFloat] minReg=1 wt=400.00>

DefList: { N050.t10. HWINTRINSIC }
N052 ( 33, 19) [000017] DACXGO-----                         *  STORE_LCL_VAR simd16 V04 tmp1          NA REG NA
<RefPosition #43  @52  RefTypeUse <Ivl:16> BB01 regmask=[allFloat] minReg=1 last wt=100.00>

DefList: {  }
N054 (  3,  2) [000058] -----------                         *  LCL_VAR   ref    V00 this          NA REG NA
Interval 17: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #44  @55  RefTypeDef <Ivl:17> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N054.t58. LCL_VAR }
N056 (  4,  3) [000059] ---X-O-----                         *  NULLCHECK byte   REG NA
<RefPosition #45  @56  RefTypeUse <Ivl:17> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>

DefList: {  }
N058 (  3,  2) [000060] -----------                         *  LCL_VAR   ref    V00 this          NA REG NA
Interval 18: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #46  @59  RefTypeDef <Ivl:18> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N058.t60. LCL_VAR }
N060 (  1,  2) [000061] -c---------                         *  CNS_INT   long   80 Fseq[_dataTable] REG NA
Contained
DefList: { N058.t60. LCL_VAR }
N062 (  5,  5) [000062] -----O-----                         *  ADD       byref  REG NA
<RefPosition #47  @62  RefTypeUse <Ivl:18> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
Interval 19: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #48  @63  RefTypeDef <Ivl:19> ADD BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N062.t62. ADD }
N064 (???,???) [000103] -----O-----                         *  PUTARG_REG byref  REG x0
<RefPosition #49  @64  RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #50  @64  RefTypeUse <Ivl:19> BB01 regmask=[x0] minReg=1 last fixed wt=100.00>
Interval 20: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #51  @65  RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #52  @65  RefTypeDef <Ivl:20> PUTARG_REG BB01 regmask=[x0] minReg=1 fixed wt=400.00>

DefList: { N064.t103. PUTARG_REG }
N066 (  3, 12) [000104] H----------                         *  CNS_INT(h) long   0x7ffac1def660 ftn REG NA
Interval 21: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #53  @67  RefTypeDef <Ivl:21> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N064.t103. PUTARG_REG; N066.t104. CNS_INT }
N068 (  6, 14) [000105] n---G------                         *  IND       long   REG NA
<RefPosition #54  @68  RefTypeUse <Ivl:21> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
Interval 22: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #55  @69  RefTypeDef <Ivl:22> IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N064.t103. PUTARG_REG; N068.t105. IND }
N070 ( 23, 11) [000016] --CXGO-----                         *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this REG NA
<RefPosition #56  @70  RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #57  @70  RefTypeUse <Ivl:20> BB01 regmask=[x0] minReg=1 last fixed wt=100.00>
<RefPosition #58  @70  RefTypeUse <Ivl:22> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #59  @71  RefTypeKill BB01 regmask=[x0-xip1 lr d0-d7 d16-d31] minReg=1>
Interval 23: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #60  @71  RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #61  @71  RefTypeDef <Ivl:23> CALL BB01 regmask=[x0] minReg=1 fixed wt=400.00>

DefList: { N070.t16. CALL }
N072 (  3,  2) [000013] -----------                         *  LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0          NA REG NA
Interval 24: simd16 RefPositions {} physReg:NA Preferences=[allFloat] Aversions=[]
<RefPosition #62  @73  RefTypeDef <Ivl:24> LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=400.00>

DefList: { N070.t16. CALL; N072.t13. LCL_VAR }
N074 (  1,  1) [000020] -----------                         *  HWINTRINSIC mask   int CreateTrueMaskAll REG NA
Interval 25: mask RefPositions {} physReg:NA Preferences=[allMask] Aversions=[]
<RefPosition #63  @75  RefTypeDef <Ivl:25> HWINTRINSIC BB01 regmask=[allMask] minReg=1 wt=400.00>

DefList: { N070.t16. CALL; N072.t13. LCL_VAR; N074.t20. HWINTRINSIC }
N076 (  5,  4) [000021] -----------                         *  HWINTRINSIC mask   int ConvertVectorToMask REG NA
<RefPosition #64  @76  RefTypeUse <Ivl:25> BB01 regmask=[p0-p7] minReg=1 last wt=100.00>
<RefPosition #65  @76  RefTypeUse <Ivl:24> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
Interval 26: mask RefPositions {} physReg:NA Preferences=[allMask] Aversions=[]
<RefPosition #66  @77  RefTypeDef <Ivl:26> HWINTRINSIC BB01 regmask=[allMask] minReg=1 wt=400.00>

DefList: { N070.t16. CALL; N076.t21. HWINTRINSIC }
N078 ( 29, 16) [000019] --CXGO-----                         *  HWINTRINSIC simd16 int LoadVector REG NA
<RefPosition #67  @78  RefTypeUse <Ivl:26> BB01 regmask=[p0-p7] minReg=1 last wt=100.00>
<RefPosition #68  @78  RefTypeUse <Ivl:23> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
Interval 27: simd16 RefPositions {} physReg:NA Preferences=[allFloat] Aversions=[]
<RefPosition #69  @79  RefTypeDef <Ivl:27> HWINTRINSIC BB01 regmask=[allFloat] minReg=1 wt=400.00>

DefList: { N078.t19. HWINTRINSIC }
N080 (  1,  1) [000025] -----------                         *  HWINTRINSIC mask   int CreateTrueMaskAll REG NA
Interval 28: mask RefPositions {} physReg:NA Preferences=[allMask] Aversions=[]
<RefPosition #70  @81  RefTypeDef <Ivl:28> HWINTRINSIC BB01 regmask=[allMask] minReg=1 wt=400.00>

DefList: { N078.t19. HWINTRINSIC; N080.t25. HWINTRINSIC }
N082 ( 31, 18) [000026] --CXGO-----                         *  HWINTRINSIC mask   int ConvertVectorToMask REG NA
<RefPosition #71  @82  RefTypeUse <Ivl:28> BB01 regmask=[p0-p7] minReg=1 last wt=100.00>
<RefPosition #72  @82  RefTypeUse <Ivl:27> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
Interval 29: mask RefPositions {} physReg:NA Preferences=[allMask] Aversions=[]
<RefPosition #73  @83  RefTypeDef <Ivl:29> HWINTRINSIC BB01 regmask=[allMask] minReg=1 wt=400.00>

DefList: { N082.t26. HWINTRINSIC }
N084 (  3,  2) [000018] -----------                         *  LCL_VAR   simd16 V04 tmp1          NA REG NA
Interval 30: simd16 RefPositions {} physReg:NA Preferences=[allFloat] Aversions=[]
<RefPosition #74  @85  RefTypeDef <Ivl:30> LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=400.00>

DefList: { N082.t26. HWINTRINSIC; N084.t18. LCL_VAR }
N086 (  1,  1) [000023] -----------                         *  HWINTRINSIC mask   int CreateTrueMaskAll REG NA
Interval 31: mask RefPositions {} physReg:NA Preferences=[allMask] Aversions=[]
<RefPosition #75  @87  RefTypeDef <Ivl:31> HWINTRINSIC BB01 regmask=[allMask] minReg=1 wt=400.00>

DefList: { N082.t26. HWINTRINSIC; N084.t18. LCL_VAR; N086.t23. HWINTRINSIC }
N088 (  5,  4) [000024] -----------                         *  HWINTRINSIC mask   int ConvertVectorToMask REG NA
<RefPosition #76  @88  RefTypeUse <Ivl:31> BB01 regmask=[p0-p7] minReg=1 last wt=100.00>
<RefPosition #77  @88  RefTypeUse <Ivl:30> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
Interval 32: mask RefPositions {} physReg:NA Preferences=[allMask] Aversions=[]
<RefPosition #78  @89  RefTypeDef <Ivl:32> HWINTRINSIC BB01 regmask=[allMask] minReg=1 wt=400.00>

DefList: { N082.t26. HWINTRINSIC; N088.t24. HWINTRINSIC }
N090 (???,???) [000106] -----------                         *  HWINTRINSIC mask   int CreateTrueMaskAll REG NA
Interval 33: mask RefPositions {} physReg:NA Preferences=[allMask] Aversions=[]
<RefPosition #79  @91  RefTypeDef <Ivl:33> HWINTRINSIC BB01 regmask=[allMask] minReg=1 wt=400.00>

DefList: { N082.t26. HWINTRINSIC; N088.t24. HWINTRINSIC; N090.t106. HWINTRINSIC }
N092 (???,???) [000107] -c---------                         *  CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000> REG NA
Contained
DefList: { N082.t26. HWINTRINSIC; N088.t24. HWINTRINSIC; N090.t106. HWINTRINSIC }
N094 ( 37, 23) [000022] -cCXGO-----                         *  HWINTRINSIC mask   int CreateBreakPropagateMask REG NA
Contained
DefList: { N082.t26. HWINTRINSIC; N088.t24. HWINTRINSIC; N090.t106. HWINTRINSIC }
N096 (???,???) [000108] --CXGO-----                         *  HWINTRINSIC mask   int ConditionalSelect REG NA
<RefPosition #80  @96  RefTypeUse <Ivl:33> BB01 regmask=[allMask] minReg=1 last wt=100.00>
<RefPosition #81  @96  RefTypeUse <Ivl:29> BB01 regmask=[allMask] minReg=1 last wt=100.00>
<RefPosition #82  @96  RefTypeUse <Ivl:32> BB01 regmask=[allMask] minReg=1 last wt=100.00>
Interval 34: mask RefPositions {} physReg:NA Preferences=[allMask] Aversions=[]
<RefPosition #83  @97  RefTypeDef <Ivl:34> HWINTRINSIC BB01 regmask=[allMask] minReg=1 wt=400.00>
Assigning related <I34> to <I29>

DefList: { N096.t108. HWINTRINSIC }
N098 ( 38, 24) [000027] --CXGO-----                         *  HWINTRINSIC simd16 int ConvertMaskToVector REG NA
<RefPosition #84  @98  RefTypeUse <Ivl:34> BB01 regmask=[allMask] minReg=1 last wt=100.00>
Interval 35: simd16 RefPositions {} physReg:NA Preferences=[allFloat] Aversions=[]
<RefPosition #85  @99  RefTypeDef <Ivl:35> HWINTRINSIC BB01 regmask=[allFloat] minReg=1 wt=400.00>

DefList: { N098.t27. HWINTRINSIC }
N100 ( 42, 27) [000028] DACXGO-----                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V02 loc1          NA REG NA
<RefPosition #86  @100 RefTypeUse <Ivl:35> BB01 regmask=[allFloat] minReg=1 last wt=100.00>

DefList: {  }
N102 (???,???) [000094] -----------                         *  IL_OFFSET void   INLRT @ 0x03A[E-] REG NA

DefList: {  }
N104 (  3,  2) [000064] -----------                         *  LCL_VAR   ref    V00 this          NA REG NA
Interval 36: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #87  @105 RefTypeDef <Ivl:36> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N104.t64. LCL_VAR }
N106 (  4,  3) [000065] ---X-O-----                         *  NULLCHECK byte   REG NA
<RefPosition #88  @106 RefTypeUse <Ivl:36> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>

DefList: {  }
N108 (  3,  2) [000066] -----------                         *  LCL_VAR   ref    V00 this          NA REG NA
Interval 37: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #89  @109 RefTypeDef <Ivl:37> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N108.t66. LCL_VAR }
N110 (  1,  2) [000067] -c---------                         *  CNS_INT   long   80 Fseq[_dataTable] REG NA
Contained
DefList: { N108.t66. LCL_VAR }
N112 (  5,  5) [000068] -----O-----                         *  ADD       byref  REG NA
<RefPosition #90  @112 RefTypeUse <Ivl:37> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
Interval 38: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #91  @113 RefTypeDef <Ivl:38> ADD BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N112.t68. ADD }
N114 (???,???) [000109] -----O-----                         *  PUTARG_REG byref  REG x0
<RefPosition #92  @114 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #93  @114 RefTypeUse <Ivl:38> BB01 regmask=[x0] minReg=1 last fixed wt=100.00>
Interval 39: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #94  @115 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #95  @115 RefTypeDef <Ivl:39> PUTARG_REG BB01 regmask=[x0] minReg=1 fixed wt=400.00>

DefList: { N114.t109. PUTARG_REG }
N116 (  3, 12) [000110] H----------                         *  CNS_INT(h) long   0x7ffac1def678 ftn REG NA
Interval 40: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #96  @117 RefTypeDef <Ivl:40> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N114.t109. PUTARG_REG; N116.t110. CNS_INT }
N118 (  6, 14) [000111] n---G------                         *  IND       long   REG NA
<RefPosition #97  @118 RefTypeUse <Ivl:40> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
Interval 41: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #98  @119 RefTypeDef <Ivl:41> IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N114.t109. PUTARG_REG; N118.t111. IND }
N120 ( 23, 11) [000031] --CXGO-----                         *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this REG NA
<RefPosition #99  @120 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #100 @120 RefTypeUse <Ivl:39> BB01 regmask=[x0] minReg=1 last fixed wt=100.00>
<RefPosition #101 @120 RefTypeUse <Ivl:41> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #102 @121 RefTypeKill BB01 regmask=[x0-xip1 lr d0-d7 d16-d31] minReg=1>
Interval 42: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #103 @121 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #104 @121 RefTypeDef <Ivl:42> CALL BB01 regmask=[x0] minReg=1 fixed wt=400.00>

DefList: { N120.t31. CALL }
N122 (  3,  2) [000032] -----------                         *  LCL_VAR   simd16<System.Numerics.Vector`1> V02 loc1          NA REG NA
Interval 43: simd16 RefPositions {} physReg:NA Preferences=[allFloat] Aversions=[]
<RefPosition #105 @123 RefTypeDef <Ivl:43> LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=400.00>

DefList: { N120.t31. CALL; N122.t32. LCL_VAR }
N124 ( 30, 16) [000033] -ACXGO-----                         *  STOREIND  simd16 (copy) REG NA
<RefPosition #106 @124 RefTypeUse <Ivl:42> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #107 @124 RefTypeUse <Ivl:43> BB01 regmask=[allFloat] minReg=1 last wt=100.00>

DefList: {  }
N126 (???,???) [000095] -----------                         *  IL_OFFSET void   INLRT @ 0x04B[E-] REG NA

DefList: {  }
N128 (  3,  2) [000070] -----------                         *  LCL_VAR   ref    V00 this          NA REG NA
Interval 44: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #108 @129 RefTypeDef <Ivl:44> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N128.t70. LCL_VAR }
N130 (  4,  3) [000071] ---X-O-----                         *  NULLCHECK byte   REG NA
<RefPosition #109 @130 RefTypeUse <Ivl:44> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>

DefList: {  }
N132 (  3,  2) [000072] -----------                         *  LCL_VAR   ref    V00 this          NA REG NA
Interval 45: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #110 @133 RefTypeDef <Ivl:45> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N132.t72. LCL_VAR }
N134 (  1,  2) [000073] -c---------                         *  CNS_INT   long   80 Fseq[_dataTable] REG NA
Contained
DefList: { N132.t72. LCL_VAR }
N136 (  5,  5) [000074] -----O-----                         *  ADD       byref  REG NA
<RefPosition #111 @136 RefTypeUse <Ivl:45> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
Interval 46: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #112 @137 RefTypeDef <Ivl:46> ADD BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N136.t74. ADD }
N138 (???,???) [000112] -----O-----                         *  PUTARG_REG byref  REG x0
<RefPosition #113 @138 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #114 @138 RefTypeUse <Ivl:46> BB01 regmask=[x0] minReg=1 last fixed wt=100.00>
Interval 47: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #115 @139 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #116 @139 RefTypeDef <Ivl:47> PUTARG_REG BB01 regmask=[x0] minReg=1 fixed wt=400.00>

DefList: { N138.t112. PUTARG_REG }
N140 (  3, 12) [000113] H----------                         *  CNS_INT(h) long   0x7ffac1def648 ftn REG NA
Interval 48: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #117 @141 RefTypeDef <Ivl:48> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N138.t112. PUTARG_REG; N140.t113. CNS_INT }
N142 (  6, 14) [000114] n---G------                         *  IND       long   REG NA
<RefPosition #118 @142 RefTypeUse <Ivl:48> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
Interval 49: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #119 @143 RefTypeDef <Ivl:49> IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N138.t112. PUTARG_REG; N142.t114. IND }
N144 ( 23, 11) [000037] --CXGO-----                         *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this REG NA
<RefPosition #120 @144 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #121 @144 RefTypeUse <Ivl:47> BB01 regmask=[x0] minReg=1 last fixed wt=100.00>
<RefPosition #122 @144 RefTypeUse <Ivl:49> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #123 @145 RefTypeKill BB01 regmask=[x0-xip1 lr d0-d7 d16-d31] minReg=1>
Interval 50: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #124 @145 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #125 @145 RefTypeDef <Ivl:50> CALL BB01 regmask=[x0] minReg=1 fixed wt=400.00>

DefList: { N144.t37. CALL }
N146 ( 27, 14) [000041] DACXGO-----                         *  STORE_LCL_VAR long   V05 tmp2          NA REG NA
<RefPosition #126 @146 RefTypeUse <Ivl:50> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>

DefList: {  }
N148 (  3,  2) [000076] -----------                         *  LCL_VAR   ref    V00 this          NA REG NA
Interval 51: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #127 @149 RefTypeDef <Ivl:51> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N148.t76. LCL_VAR }
N150 (  4,  3) [000077] ---X-O-----                         *  NULLCHECK byte   REG NA
<RefPosition #128 @150 RefTypeUse <Ivl:51> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>

DefList: {  }
N152 (  3,  2) [000078] -----------                         *  LCL_VAR   ref    V00 this          NA REG NA
Interval 52: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #129 @153 RefTypeDef <Ivl:52> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N152.t78. LCL_VAR }
N154 (  1,  2) [000079] -c---------                         *  CNS_INT   long   80 Fseq[_dataTable] REG NA
Contained
DefList: { N152.t78. LCL_VAR }
N156 (  5,  5) [000080] -----O-----                         *  ADD       byref  REG NA
<RefPosition #130 @156 RefTypeUse <Ivl:52> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
Interval 53: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #131 @157 RefTypeDef <Ivl:53> ADD BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N156.t80. ADD }
N158 (???,???) [000115] -----O-----                         *  PUTARG_REG byref  REG x0
<RefPosition #132 @158 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #133 @158 RefTypeUse <Ivl:53> BB01 regmask=[x0] minReg=1 last fixed wt=100.00>
Interval 54: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #134 @159 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #135 @159 RefTypeDef <Ivl:54> PUTARG_REG BB01 regmask=[x0] minReg=1 fixed wt=400.00>

DefList: { N158.t115. PUTARG_REG }
N160 (  3, 12) [000116] H----------                         *  CNS_INT(h) long   0x7ffac1def660 ftn REG NA
Interval 55: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #136 @161 RefTypeDef <Ivl:55> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N158.t115. PUTARG_REG; N160.t116. CNS_INT }
N162 (  6, 14) [000117] n---G------                         *  IND       long   REG NA
<RefPosition #137 @162 RefTypeUse <Ivl:55> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
Interval 56: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #138 @163 RefTypeDef <Ivl:56> IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N158.t115. PUTARG_REG; N162.t117. IND }
N164 ( 23, 11) [000040] --CXGO-----                         *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this REG NA
<RefPosition #139 @164 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #140 @164 RefTypeUse <Ivl:54> BB01 regmask=[x0] minReg=1 last fixed wt=100.00>
<RefPosition #141 @164 RefTypeUse <Ivl:56> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #142 @165 RefTypeKill BB01 regmask=[x0-xip1 lr d0-d7 d16-d31] minReg=1>
Interval 57: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #143 @165 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #144 @165 RefTypeDef <Ivl:57> CALL BB01 regmask=[x0] minReg=1 fixed wt=400.00>

DefList: { N164.t40. CALL }
N166 ( 27, 14) [000046] DACXGO-----                         *  STORE_LCL_VAR long   V06 tmp3          NA REG NA
<RefPosition #145 @166 RefTypeUse <Ivl:57> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>

DefList: {  }
N168 (  3,  2) [000082] -----------                         *  LCL_VAR   ref    V00 this          NA REG NA
Interval 58: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #146 @169 RefTypeDef <Ivl:58> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N168.t82. LCL_VAR }
N170 (  4,  3) [000083] ---X-O-----                         *  NULLCHECK byte   REG NA
<RefPosition #147 @170 RefTypeUse <Ivl:58> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>

DefList: {  }
N172 (  3,  2) [000084] -----------                         *  LCL_VAR   ref    V00 this          NA REG NA
Interval 59: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #148 @173 RefTypeDef <Ivl:59> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N172.t84. LCL_VAR }
N174 (  1,  2) [000085] -c---------                         *  CNS_INT   long   80 Fseq[_dataTable] REG NA
Contained
DefList: { N172.t84. LCL_VAR }
N176 (  5,  5) [000086] -----O-----                         *  ADD       byref  REG NA
<RefPosition #149 @176 RefTypeUse <Ivl:59> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
Interval 60: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #150 @177 RefTypeDef <Ivl:60> ADD BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N176.t86. ADD }
N178 (???,???) [000118] -----O-----                         *  PUTARG_REG byref  REG x0
<RefPosition #151 @178 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #152 @178 RefTypeUse <Ivl:60> BB01 regmask=[x0] minReg=1 last fixed wt=100.00>
Interval 61: byref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #153 @179 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #154 @179 RefTypeDef <Ivl:61> PUTARG_REG BB01 regmask=[x0] minReg=1 fixed wt=400.00>

DefList: { N178.t118. PUTARG_REG }
N180 (  3, 12) [000119] H----------                         *  CNS_INT(h) long   0x7ffac1def678 ftn REG NA
Interval 62: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #155 @181 RefTypeDef <Ivl:62> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N178.t118. PUTARG_REG; N180.t119. CNS_INT }
N182 (  6, 14) [000120] n---G------                         *  IND       long   REG NA
<RefPosition #156 @182 RefTypeUse <Ivl:62> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
Interval 63: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #157 @183 RefTypeDef <Ivl:63> IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N178.t118. PUTARG_REG; N182.t120. IND }
N184 ( 23, 11) [000045] --CXGO-----                         *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this REG NA
<RefPosition #158 @184 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #159 @184 RefTypeUse <Ivl:61> BB01 regmask=[x0] minReg=1 last fixed wt=100.00>
<RefPosition #160 @184 RefTypeUse <Ivl:63> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #161 @185 RefTypeKill BB01 regmask=[x0-xip1 lr d0-d7 d16-d31] minReg=1>
Interval 64: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #162 @185 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #163 @185 RefTypeDef <Ivl:64> CALL BB01 regmask=[x0] minReg=1 fixed wt=400.00>

DefList: { N184.t45. CALL }
N186 ( 27, 14) [000089] DACXGO-----                         *  STORE_LCL_VAR long   V07 tmp4          NA REG NA
<RefPosition #164 @186 RefTypeUse <Ivl:64> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>

DefList: {  }
N188 (  3,  2) [000090] -----------                         *  LCL_VAR   long   V07 tmp4          NA REG NA
Interval 65: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #165 @189 RefTypeDef <Ivl:65> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N188.t90. LCL_VAR }
N190 (???,???) [000121] -----------                         *  PUTARG_REG long   REG x3
<RefPosition #166 @190 RefTypeFixedReg <Reg:x3 > BB01 regmask=[x3] minReg=1 wt=100.00>
<RefPosition #167 @190 RefTypeUse <Ivl:65> BB01 regmask=[x3] minReg=1 last fixed wt=100.00>
Interval 66: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #168 @191 RefTypeFixedReg <Reg:x3 > BB01 regmask=[x3] minReg=1 wt=100.00>
<RefPosition #169 @191 RefTypeDef <Ivl:66> PUTARG_REG BB01 regmask=[x3] minReg=1 fixed wt=400.00>

DefList: { N190.t121. PUTARG_REG }
N192 (  3,  2) [000042] -----------                         *  LCL_VAR   long   V05 tmp2          NA REG NA
Interval 67: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #170 @193 RefTypeDef <Ivl:67> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N190.t121. PUTARG_REG; N192.t42. LCL_VAR }
N194 (???,???) [000122] -----------                         *  PUTARG_REG long   REG x1
<RefPosition #171 @194 RefTypeFixedReg <Reg:x1 > BB01 regmask=[x1] minReg=1 wt=100.00>
<RefPosition #172 @194 RefTypeUse <Ivl:67> BB01 regmask=[x1] minReg=1 last fixed wt=100.00>
Interval 68: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #173 @195 RefTypeFixedReg <Reg:x1 > BB01 regmask=[x1] minReg=1 wt=100.00>
<RefPosition #174 @195 RefTypeDef <Ivl:68> PUTARG_REG BB01 regmask=[x1] minReg=1 fixed wt=400.00>

DefList: { N190.t121. PUTARG_REG; N194.t122. PUTARG_REG }
N196 (  3,  2) [000047] -----------                         *  LCL_VAR   long   V06 tmp3          NA REG NA
Interval 69: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #175 @197 RefTypeDef <Ivl:69> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N190.t121. PUTARG_REG; N194.t122. PUTARG_REG; N196.t47. LCL_VAR }
N198 (???,???) [000123] -----------                         *  PUTARG_REG long   REG x2
<RefPosition #176 @198 RefTypeFixedReg <Reg:x2 > BB01 regmask=[x2] minReg=1 wt=100.00>
<RefPosition #177 @198 RefTypeUse <Ivl:69> BB01 regmask=[x2] minReg=1 last fixed wt=100.00>
Interval 70: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #178 @199 RefTypeFixedReg <Reg:x2 > BB01 regmask=[x2] minReg=1 wt=100.00>
<RefPosition #179 @199 RefTypeDef <Ivl:70> PUTARG_REG BB01 regmask=[x2] minReg=1 fixed wt=400.00>

DefList: { N190.t121. PUTARG_REG; N194.t122. PUTARG_REG; N198.t123. PUTARG_REG }
N200 (  3,  2) [000034] -----------                         *  LCL_VAR   ref    V00 this          NA REG NA
Interval 71: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #180 @201 RefTypeDef <Ivl:71> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N190.t121. PUTARG_REG; N194.t122. PUTARG_REG; N198.t123. PUTARG_REG; N200.t34. LCL_VAR }
N202 (???,???) [000124] -----------                         *  PUTARG_REG ref    REG x0
<RefPosition #181 @202 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #182 @202 RefTypeUse <Ivl:71> BB01 regmask=[x0] minReg=1 last fixed wt=100.00>
Interval 72: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #183 @203 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #184 @203 RefTypeDef <Ivl:72> PUTARG_REG BB01 regmask=[x0] minReg=1 fixed wt=400.00>

DefList: { N190.t121. PUTARG_REG; N194.t122. PUTARG_REG; N198.t123. PUTARG_REG; N202.t124. PUTARG_REG }
N204 (  3, 12) [000088] H----------                         *  CNS_INT(h) ref     'RunBasicScenario_Load' REG NA
Interval 73: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #185 @205 RefTypeDef <Ivl:73> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N190.t121. PUTARG_REG; N194.t122. PUTARG_REG; N198.t123. PUTARG_REG; N202.t124. PUTARG_REG; N204.t88. CNS_INT }
N206 (???,???) [000125] -----------                         *  PUTARG_REG ref    REG x4
<RefPosition #186 @206 RefTypeFixedReg <Reg:x4 > BB01 regmask=[x4] minReg=1 wt=100.00>
<RefPosition #187 @206 RefTypeUse <Ivl:73> BB01 regmask=[x4] minReg=1 last fixed wt=100.00>
Interval 74: ref RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #188 @207 RefTypeFixedReg <Reg:x4 > BB01 regmask=[x4] minReg=1 wt=100.00>
<RefPosition #189 @207 RefTypeDef <Ivl:74> PUTARG_REG BB01 regmask=[x4] minReg=1 fixed wt=400.00>

DefList: { N190.t121. PUTARG_REG; N194.t122. PUTARG_REG; N198.t123. PUTARG_REG; N202.t124. PUTARG_REG; N206.t125. PUTARG_REG }
N208 (  3, 12) [000126] H----------                         *  CNS_INT(h) long   0x7ffac1def8b8 ftn REG NA
Interval 75: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #190 @209 RefTypeDef <Ivl:75> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N190.t121. PUTARG_REG; N194.t122. PUTARG_REG; N198.t123. PUTARG_REG; N202.t124. PUTARG_REG; N206.t125. PUTARG_REG; N208.t126. CNS_INT }
N210 (  6, 14) [000127] n---G------                         *  IND       long   REG NA
<RefPosition #191 @210 RefTypeUse <Ivl:75> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
Interval 76: long RefPositions {} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
<RefPosition #192 @211 RefTypeDef <Ivl:76> IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>

DefList: { N190.t121. PUTARG_REG; N194.t122. PUTARG_REG; N198.t123. PUTARG_REG; N202.t124. PUTARG_REG; N206.t125. PUTARG_REG; N210.t127. IND }
N212 ( 59, 42) [000049] -ACXGO-----                         *  CALL      void   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:ValidateResult(ulong,ulong,ulong,System.String):this REG NA
<RefPosition #193 @212 RefTypeFixedReg <Reg:x3 > BB01 regmask=[x3] minReg=1 wt=100.00>
<RefPosition #194 @212 RefTypeUse <Ivl:66> BB01 regmask=[x3] minReg=1 last fixed wt=100.00>
<RefPosition #195 @212 RefTypeFixedReg <Reg:x1 > BB01 regmask=[x1] minReg=1 wt=100.00>
<RefPosition #196 @212 RefTypeUse <Ivl:68> BB01 regmask=[x1] minReg=1 last fixed wt=100.00>
<RefPosition #197 @212 RefTypeFixedReg <Reg:x2 > BB01 regmask=[x2] minReg=1 wt=100.00>
<RefPosition #198 @212 RefTypeUse <Ivl:70> BB01 regmask=[x2] minReg=1 last fixed wt=100.00>
<RefPosition #199 @212 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #200 @212 RefTypeUse <Ivl:72> BB01 regmask=[x0] minReg=1 last fixed wt=100.00>
<RefPosition #201 @212 RefTypeFixedReg <Reg:x4 > BB01 regmask=[x4] minReg=1 wt=100.00>
<RefPosition #202 @212 RefTypeUse <Ivl:74> BB01 regmask=[x4] minReg=1 last fixed wt=100.00>
<RefPosition #203 @212 RefTypeUse <Ivl:76> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #204 @213 RefTypeKill BB01 regmask=[x0-xip1 lr d0-d7 d16-d31] minReg=1>

DefList: {  }
N214 (???,???) [000096] -----------                         *  IL_OFFSET void   INLRT @ 0x077[E-] REG NA

DefList: {  }
N216 (  0,  0) [000050] -----------                         *  RETURN    void   REG NA


Linear scan intervals BEFORE VALIDATING INTERVALS:
Interval  0: ref (constant) RefPositions {#1@5 #3@6} physReg:NA Preferences=[x0] Aversions=[]
Interval  1: ref RefPositions {#5@7 #10@12} physReg:NA Preferences=[x0] Aversions=[]
Interval  2: long (constant) RefPositions {#6@9 #7@10} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval  3: long RefPositions {#8@11 #11@12} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval  4: mask RefPositions {#13@19 #14@20} physReg:NA Preferences=[allMask] Aversions=[]
Interval  5: simd16 RefPositions {#15@21 #16@22} physReg:NA Preferences=[allFloat] Aversions=[]
Interval  6: ref RefPositions {#17@27 #18@28} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval  7: ref RefPositions {#19@31 #20@34} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval  8: byref RefPositions {#21@35 #23@36} physReg:NA Preferences=[x0] Aversions=[]
Interval  9: byref RefPositions {#25@37 #30@42} physReg:NA Preferences=[x0] Aversions=[]
Interval 10: long (constant) RefPositions {#26@39 #27@40} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 11: long RefPositions {#28@41 #31@42} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 12: long RefPositions {#34@43 #41@50} physReg:NA Preferences=[x0] Aversions=[]
Interval 13: simd16 RefPositions {#35@45 #38@48} physReg:NA Preferences=[allFloat] Aversions=[]
Interval 14: mask RefPositions {#36@47 #37@48} physReg:NA Preferences=[p0-p7] Aversions=[]
Interval 15: mask RefPositions {#39@49 #40@50} physReg:NA Preferences=[p0-p7] Aversions=[]
Interval 16: simd16 RefPositions {#42@51 #43@52} physReg:NA Preferences=[allFloat] Aversions=[]
Interval 17: ref RefPositions {#44@55 #45@56} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 18: ref RefPositions {#46@59 #47@62} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 19: byref RefPositions {#48@63 #50@64} physReg:NA Preferences=[x0] Aversions=[]
Interval 20: byref RefPositions {#52@65 #57@70} physReg:NA Preferences=[x0] Aversions=[]
Interval 21: long (constant) RefPositions {#53@67 #54@68} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 22: long RefPositions {#55@69 #58@70} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 23: long RefPositions {#61@71 #68@78} physReg:NA Preferences=[x0] Aversions=[]
Interval 24: simd16 RefPositions {#62@73 #65@76} physReg:NA Preferences=[allFloat] Aversions=[]
Interval 25: mask RefPositions {#63@75 #64@76} physReg:NA Preferences=[p0-p7] Aversions=[]
Interval 26: mask RefPositions {#66@77 #67@78} physReg:NA Preferences=[p0-p7] Aversions=[]
Interval 27: simd16 RefPositions {#69@79 #72@82} physReg:NA Preferences=[allFloat] Aversions=[]
Interval 28: mask RefPositions {#70@81 #71@82} physReg:NA Preferences=[p0-p7] Aversions=[]
Interval 29: mask RefPositions {#73@83 #81@96} physReg:NA Preferences=[allMask] Aversions=[] RelatedInterval <I34>
Interval 30: simd16 RefPositions {#74@85 #77@88} physReg:NA Preferences=[allFloat] Aversions=[]
Interval 31: mask RefPositions {#75@87 #76@88} physReg:NA Preferences=[p0-p7] Aversions=[]
Interval 32: mask RefPositions {#78@89 #82@96} physReg:NA Preferences=[allMask] Aversions=[]
Interval 33: mask RefPositions {#79@91 #80@96} physReg:NA Preferences=[allMask] Aversions=[]
Interval 34: mask (interfering uses) RefPositions {#83@97 #84@98} physReg:NA Preferences=[allMask] Aversions=[]
Interval 35: simd16 RefPositions {#85@99 #86@100} physReg:NA Preferences=[allFloat] Aversions=[]
Interval 36: ref RefPositions {#87@105 #88@106} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 37: ref RefPositions {#89@109 #90@112} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 38: byref RefPositions {#91@113 #93@114} physReg:NA Preferences=[x0] Aversions=[]
Interval 39: byref RefPositions {#95@115 #100@120} physReg:NA Preferences=[x0] Aversions=[]
Interval 40: long (constant) RefPositions {#96@117 #97@118} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 41: long RefPositions {#98@119 #101@120} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 42: long RefPositions {#104@121 #106@124} physReg:NA Preferences=[x0] Aversions=[]
Interval 43: simd16 RefPositions {#105@123 #107@124} physReg:NA Preferences=[allFloat] Aversions=[]
Interval 44: ref RefPositions {#108@129 #109@130} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 45: ref RefPositions {#110@133 #111@136} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 46: byref RefPositions {#112@137 #114@138} physReg:NA Preferences=[x0] Aversions=[]
Interval 47: byref RefPositions {#116@139 #121@144} physReg:NA Preferences=[x0] Aversions=[]
Interval 48: long (constant) RefPositions {#117@141 #118@142} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 49: long RefPositions {#119@143 #122@144} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 50: long RefPositions {#125@145 #126@146} physReg:NA Preferences=[x0] Aversions=[]
Interval 51: ref RefPositions {#127@149 #128@150} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 52: ref RefPositions {#129@153 #130@156} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 53: byref RefPositions {#131@157 #133@158} physReg:NA Preferences=[x0] Aversions=[]
Interval 54: byref RefPositions {#135@159 #140@164} physReg:NA Preferences=[x0] Aversions=[]
Interval 55: long (constant) RefPositions {#136@161 #137@162} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 56: long RefPositions {#138@163 #141@164} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 57: long RefPositions {#144@165 #145@166} physReg:NA Preferences=[x0] Aversions=[]
Interval 58: ref RefPositions {#146@169 #147@170} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 59: ref RefPositions {#148@173 #149@176} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 60: byref RefPositions {#150@177 #152@178} physReg:NA Preferences=[x0] Aversions=[]
Interval 61: byref RefPositions {#154@179 #159@184} physReg:NA Preferences=[x0] Aversions=[]
Interval 62: long (constant) RefPositions {#155@181 #156@182} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 63: long RefPositions {#157@183 #160@184} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 64: long RefPositions {#163@185 #164@186} physReg:NA Preferences=[x0] Aversions=[]
Interval 65: long RefPositions {#165@189 #167@190} physReg:NA Preferences=[x3] Aversions=[]
Interval 66: long RefPositions {#169@191 #194@212} physReg:NA Preferences=[x3] Aversions=[]
Interval 67: long RefPositions {#170@193 #172@194} physReg:NA Preferences=[x1] Aversions=[]
Interval 68: long RefPositions {#174@195 #196@212} physReg:NA Preferences=[x1] Aversions=[]
Interval 69: long RefPositions {#175@197 #177@198} physReg:NA Preferences=[x2] Aversions=[]
Interval 70: long RefPositions {#179@199 #198@212} physReg:NA Preferences=[x2] Aversions=[]
Interval 71: ref RefPositions {#180@201 #182@202} physReg:NA Preferences=[x0] Aversions=[]
Interval 72: ref RefPositions {#184@203 #200@212} physReg:NA Preferences=[x0] Aversions=[]
Interval 73: ref (constant) RefPositions {#185@205 #187@206} physReg:NA Preferences=[x4] Aversions=[]
Interval 74: ref RefPositions {#189@207 #202@212} physReg:NA Preferences=[x4] Aversions=[]
Interval 75: long (constant) RefPositions {#190@209 #191@210} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 76: long RefPositions {#192@211 #203@212} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]

------------
REFPOSITIONS BEFORE VALIDATING INTERVALS: 
------------
<RefPosition #0   @0   RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>
<RefPosition #1   @5   RefTypeDef <Ivl:0> CNS_INT BB01 regmask=[x0] minReg=1 wt=400.00>
<RefPosition #2   @6   RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #3   @6   RefTypeUse <Ivl:0> BB01 regmask=[x0] minReg=1 last fixed wt=100.00>
<RefPosition #4   @7   RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #5   @7   RefTypeDef <Ivl:1> PUTARG_REG BB01 regmask=[x0] minReg=1 fixed wt=400.00>
<RefPosition #6   @9   RefTypeDef <Ivl:2> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #7   @10  RefTypeUse <Ivl:2> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #8   @11  RefTypeDef <Ivl:3> IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #9   @12  RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #10  @12  RefTypeUse <Ivl:1> BB01 regmask=[x0] minReg=1 last fixed wt=100.00>
<RefPosition #11  @12  RefTypeUse <Ivl:3> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #12  @13  RefTypeKill BB01 regmask=[x0-xip1 lr d0-d7 d16-d31 p0-p15] minReg=1>
<RefPosition #13  @19  RefTypeDef <Ivl:4> HWINTRINSIC BB01 regmask=[allMask] minReg=1 wt=400.00>
<RefPosition #14  @20  RefTypeUse <Ivl:4> BB01 regmask=[allMask] minReg=1 last wt=100.00>
<RefPosition #15  @21  RefTypeDef <Ivl:5> HWINTRINSIC BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #16  @22  RefTypeUse <Ivl:5> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #17  @27  RefTypeDef <Ivl:6> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #18  @28  RefTypeUse <Ivl:6> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #19  @31  RefTypeDef <Ivl:7> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #20  @34  RefTypeUse <Ivl:7> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #21  @35  RefTypeDef <Ivl:8> ADD BB01 regmask=[x0] minReg=1 wt=400.00>
<RefPosition #22  @36  RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #23  @36  RefTypeUse <Ivl:8> BB01 regmask=[x0] minReg=1 last fixed wt=100.00>
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<RefPosition #48  @63  RefTypeDef <Ivl:19> ADD BB01 regmask=[x0] minReg=1 wt=400.00>
<RefPosition #49  @64  RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #50  @64  RefTypeUse <Ivl:19> BB01 regmask=[x0] minReg=1 last fixed wt=100.00>
<RefPosition #51  @65  RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #52  @65  RefTypeDef <Ivl:20> PUTARG_REG BB01 regmask=[x0] minReg=1 fixed wt=400.00>
<RefPosition #53  @67  RefTypeDef <Ivl:21> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #54  @68  RefTypeUse <Ivl:21> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #55  @69  RefTypeDef <Ivl:22> IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #56  @70  RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #57  @70  RefTypeUse <Ivl:20> BB01 regmask=[x0] minReg=1 last fixed wt=100.00>
<RefPosition #58  @70  RefTypeUse <Ivl:22> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #59  @71  RefTypeKill BB01 regmask=[x0-xip1 lr d0-d7 d16-d31 p0-p15] minReg=1>
<RefPosition #60  @71  RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #61  @71  RefTypeDef <Ivl:23> CALL BB01 regmask=[x0] minReg=1 fixed wt=400.00>
<RefPosition #62  @73  RefTypeDef <Ivl:24> LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #63  @75  RefTypeDef <Ivl:25> HWINTRINSIC BB01 regmask=[p0-p7] minReg=1 wt=400.00>
<RefPosition #64  @76  RefTypeUse <Ivl:25> BB01 regmask=[p0-p7] minReg=1 last wt=100.00>
<RefPosition #65  @76  RefTypeUse <Ivl:24> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #66  @77  RefTypeDef <Ivl:26> HWINTRINSIC BB01 regmask=[p0-p7] minReg=1 wt=400.00>
<RefPosition #67  @78  RefTypeUse <Ivl:26> BB01 regmask=[p0-p7] minReg=1 last wt=100.00>
<RefPosition #68  @78  RefTypeUse <Ivl:23> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #69  @79  RefTypeDef <Ivl:27> HWINTRINSIC BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #70  @81  RefTypeDef <Ivl:28> HWINTRINSIC BB01 regmask=[p0-p7] minReg=1 wt=400.00>
<RefPosition #71  @82  RefTypeUse <Ivl:28> BB01 regmask=[p0-p7] minReg=1 last wt=100.00>
<RefPosition #72  @82  RefTypeUse <Ivl:27> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #73  @83  RefTypeDef <Ivl:29> HWINTRINSIC BB01 regmask=[allMask] minReg=1 wt=400.00>
<RefPosition #74  @85  RefTypeDef <Ivl:30> LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #75  @87  RefTypeDef <Ivl:31> HWINTRINSIC BB01 regmask=[p0-p7] minReg=1 wt=400.00>
<RefPosition #76  @88  RefTypeUse <Ivl:31> BB01 regmask=[p0-p7] minReg=1 last wt=100.00>
<RefPosition #77  @88  RefTypeUse <Ivl:30> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #78  @89  RefTypeDef <Ivl:32> HWINTRINSIC BB01 regmask=[allMask] minReg=1 wt=400.00>
<RefPosition #79  @91  RefTypeDef <Ivl:33> HWINTRINSIC BB01 regmask=[allMask] minReg=1 wt=400.00>
<RefPosition #80  @96  RefTypeUse <Ivl:33> BB01 regmask=[allMask] minReg=1 last delay wt=100.00>
<RefPosition #81  @96  RefTypeUse <Ivl:29> BB01 regmask=[allMask] minReg=1 last wt=100.00>
<RefPosition #82  @96  RefTypeUse <Ivl:32> BB01 regmask=[allMask] minReg=1 last delay wt=100.00>
<RefPosition #83  @97  RefTypeDef <Ivl:34> HWINTRINSIC BB01 regmask=[allMask] minReg=1 wt=400.00>
<RefPosition #84  @98  RefTypeUse <Ivl:34> BB01 regmask=[allMask] minReg=1 last wt=100.00>
<RefPosition #85  @99  RefTypeDef <Ivl:35> HWINTRINSIC BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #86  @100 RefTypeUse <Ivl:35> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #87  @105 RefTypeDef <Ivl:36> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #88  @106 RefTypeUse <Ivl:36> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #89  @109 RefTypeDef <Ivl:37> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #90  @112 RefTypeUse <Ivl:37> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #91  @113 RefTypeDef <Ivl:38> ADD BB01 regmask=[x0] minReg=1 wt=400.00>
<RefPosition #92  @114 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #93  @114 RefTypeUse <Ivl:38> BB01 regmask=[x0] minReg=1 last fixed wt=100.00>
<RefPosition #94  @115 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #95  @115 RefTypeDef <Ivl:39> PUTARG_REG BB01 regmask=[x0] minReg=1 fixed wt=400.00>
<RefPosition #96  @117 RefTypeDef <Ivl:40> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #97  @118 RefTypeUse <Ivl:40> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #98  @119 RefTypeDef <Ivl:41> IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #99  @120 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #100 @120 RefTypeUse <Ivl:39> BB01 regmask=[x0] minReg=1 last fixed wt=100.00>
<RefPosition #101 @120 RefTypeUse <Ivl:41> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #102 @121 RefTypeKill BB01 regmask=[x0-xip1 lr d0-d7 d16-d31 p0-p15] minReg=1>
<RefPosition #103 @121 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #104 @121 RefTypeDef <Ivl:42> CALL BB01 regmask=[x0] minReg=1 fixed wt=400.00>
<RefPosition #105 @123 RefTypeDef <Ivl:43> LCL_VAR BB01 regmask=[allFloat] minReg=1 wt=400.00>
<RefPosition #106 @124 RefTypeUse <Ivl:42> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #107 @124 RefTypeUse <Ivl:43> BB01 regmask=[allFloat] minReg=1 last wt=100.00>
<RefPosition #108 @129 RefTypeDef <Ivl:44> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #109 @130 RefTypeUse <Ivl:44> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #110 @133 RefTypeDef <Ivl:45> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #111 @136 RefTypeUse <Ivl:45> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #112 @137 RefTypeDef <Ivl:46> ADD BB01 regmask=[x0] minReg=1 wt=400.00>
<RefPosition #113 @138 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #114 @138 RefTypeUse <Ivl:46> BB01 regmask=[x0] minReg=1 last fixed wt=100.00>
<RefPosition #115 @139 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #116 @139 RefTypeDef <Ivl:47> PUTARG_REG BB01 regmask=[x0] minReg=1 fixed wt=400.00>
<RefPosition #117 @141 RefTypeDef <Ivl:48> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #118 @142 RefTypeUse <Ivl:48> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #119 @143 RefTypeDef <Ivl:49> IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #120 @144 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #121 @144 RefTypeUse <Ivl:47> BB01 regmask=[x0] minReg=1 last fixed wt=100.00>
<RefPosition #122 @144 RefTypeUse <Ivl:49> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #123 @145 RefTypeKill BB01 regmask=[x0-xip1 lr d0-d7 d16-d31 p0-p15] minReg=1>
<RefPosition #124 @145 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #125 @145 RefTypeDef <Ivl:50> CALL BB01 regmask=[x0] minReg=1 fixed wt=400.00>
<RefPosition #126 @146 RefTypeUse <Ivl:50> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #127 @149 RefTypeDef <Ivl:51> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #128 @150 RefTypeUse <Ivl:51> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #129 @153 RefTypeDef <Ivl:52> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #130 @156 RefTypeUse <Ivl:52> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #131 @157 RefTypeDef <Ivl:53> ADD BB01 regmask=[x0] minReg=1 wt=400.00>
<RefPosition #132 @158 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #133 @158 RefTypeUse <Ivl:53> BB01 regmask=[x0] minReg=1 last fixed wt=100.00>
<RefPosition #134 @159 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #135 @159 RefTypeDef <Ivl:54> PUTARG_REG BB01 regmask=[x0] minReg=1 fixed wt=400.00>
<RefPosition #136 @161 RefTypeDef <Ivl:55> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #137 @162 RefTypeUse <Ivl:55> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #138 @163 RefTypeDef <Ivl:56> IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #139 @164 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #140 @164 RefTypeUse <Ivl:54> BB01 regmask=[x0] minReg=1 last fixed wt=100.00>
<RefPosition #141 @164 RefTypeUse <Ivl:56> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #142 @165 RefTypeKill BB01 regmask=[x0-xip1 lr d0-d7 d16-d31 p0-p15] minReg=1>
<RefPosition #143 @165 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #144 @165 RefTypeDef <Ivl:57> CALL BB01 regmask=[x0] minReg=1 fixed wt=400.00>
<RefPosition #145 @166 RefTypeUse <Ivl:57> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #146 @169 RefTypeDef <Ivl:58> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #147 @170 RefTypeUse <Ivl:58> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #148 @173 RefTypeDef <Ivl:59> LCL_VAR BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #149 @176 RefTypeUse <Ivl:59> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #150 @177 RefTypeDef <Ivl:60> ADD BB01 regmask=[x0] minReg=1 wt=400.00>
<RefPosition #151 @178 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #152 @178 RefTypeUse <Ivl:60> BB01 regmask=[x0] minReg=1 last fixed wt=100.00>
<RefPosition #153 @179 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #154 @179 RefTypeDef <Ivl:61> PUTARG_REG BB01 regmask=[x0] minReg=1 fixed wt=400.00>
<RefPosition #155 @181 RefTypeDef <Ivl:62> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #156 @182 RefTypeUse <Ivl:62> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #157 @183 RefTypeDef <Ivl:63> IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #158 @184 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #159 @184 RefTypeUse <Ivl:61> BB01 regmask=[x0] minReg=1 last fixed wt=100.00>
<RefPosition #160 @184 RefTypeUse <Ivl:63> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #161 @185 RefTypeKill BB01 regmask=[x0-xip1 lr d0-d7 d16-d31 p0-p15] minReg=1>
<RefPosition #162 @185 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #163 @185 RefTypeDef <Ivl:64> CALL BB01 regmask=[x0] minReg=1 fixed wt=400.00>
<RefPosition #164 @186 RefTypeUse <Ivl:64> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #165 @189 RefTypeDef <Ivl:65> LCL_VAR BB01 regmask=[x3] minReg=1 wt=400.00>
<RefPosition #166 @190 RefTypeFixedReg <Reg:x3 > BB01 regmask=[x3] minReg=1 wt=100.00>
<RefPosition #167 @190 RefTypeUse <Ivl:65> BB01 regmask=[x3] minReg=1 last fixed wt=100.00>
<RefPosition #168 @191 RefTypeFixedReg <Reg:x3 > BB01 regmask=[x3] minReg=1 wt=100.00>
<RefPosition #169 @191 RefTypeDef <Ivl:66> PUTARG_REG BB01 regmask=[x3] minReg=1 fixed wt=400.00>
<RefPosition #170 @193 RefTypeDef <Ivl:67> LCL_VAR BB01 regmask=[x1] minReg=1 wt=400.00>
<RefPosition #171 @194 RefTypeFixedReg <Reg:x1 > BB01 regmask=[x1] minReg=1 wt=100.00>
<RefPosition #172 @194 RefTypeUse <Ivl:67> BB01 regmask=[x1] minReg=1 last fixed wt=100.00>
<RefPosition #173 @195 RefTypeFixedReg <Reg:x1 > BB01 regmask=[x1] minReg=1 wt=100.00>
<RefPosition #174 @195 RefTypeDef <Ivl:68> PUTARG_REG BB01 regmask=[x1] minReg=1 fixed wt=400.00>
<RefPosition #175 @197 RefTypeDef <Ivl:69> LCL_VAR BB01 regmask=[x2] minReg=1 wt=400.00>
<RefPosition #176 @198 RefTypeFixedReg <Reg:x2 > BB01 regmask=[x2] minReg=1 wt=100.00>
<RefPosition #177 @198 RefTypeUse <Ivl:69> BB01 regmask=[x2] minReg=1 last fixed wt=100.00>
<RefPosition #178 @199 RefTypeFixedReg <Reg:x2 > BB01 regmask=[x2] minReg=1 wt=100.00>
<RefPosition #179 @199 RefTypeDef <Ivl:70> PUTARG_REG BB01 regmask=[x2] minReg=1 fixed wt=400.00>
<RefPosition #180 @201 RefTypeDef <Ivl:71> LCL_VAR BB01 regmask=[x0] minReg=1 wt=400.00>
<RefPosition #181 @202 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #182 @202 RefTypeUse <Ivl:71> BB01 regmask=[x0] minReg=1 last fixed wt=100.00>
<RefPosition #183 @203 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #184 @203 RefTypeDef <Ivl:72> PUTARG_REG BB01 regmask=[x0] minReg=1 fixed wt=400.00>
<RefPosition #185 @205 RefTypeDef <Ivl:73> CNS_INT BB01 regmask=[x4] minReg=1 wt=400.00>
<RefPosition #186 @206 RefTypeFixedReg <Reg:x4 > BB01 regmask=[x4] minReg=1 wt=100.00>
<RefPosition #187 @206 RefTypeUse <Ivl:73> BB01 regmask=[x4] minReg=1 last fixed wt=100.00>
<RefPosition #188 @207 RefTypeFixedReg <Reg:x4 > BB01 regmask=[x4] minReg=1 wt=100.00>
<RefPosition #189 @207 RefTypeDef <Ivl:74> PUTARG_REG BB01 regmask=[x4] minReg=1 fixed wt=400.00>
<RefPosition #190 @209 RefTypeDef <Ivl:75> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #191 @210 RefTypeUse <Ivl:75> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #192 @211 RefTypeDef <Ivl:76> IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #193 @212 RefTypeFixedReg <Reg:x3 > BB01 regmask=[x3] minReg=1 wt=100.00>
<RefPosition #194 @212 RefTypeUse <Ivl:66> BB01 regmask=[x3] minReg=1 last fixed wt=100.00>
<RefPosition #195 @212 RefTypeFixedReg <Reg:x1 > BB01 regmask=[x1] minReg=1 wt=100.00>
<RefPosition #196 @212 RefTypeUse <Ivl:68> BB01 regmask=[x1] minReg=1 last fixed wt=100.00>
<RefPosition #197 @212 RefTypeFixedReg <Reg:x2 > BB01 regmask=[x2] minReg=1 wt=100.00>
<RefPosition #198 @212 RefTypeUse <Ivl:70> BB01 regmask=[x2] minReg=1 last fixed wt=100.00>
<RefPosition #199 @212 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #200 @212 RefTypeUse <Ivl:72> BB01 regmask=[x0] minReg=1 last fixed wt=100.00>
<RefPosition #201 @212 RefTypeFixedReg <Reg:x4 > BB01 regmask=[x4] minReg=1 wt=100.00>
<RefPosition #202 @212 RefTypeUse <Ivl:74> BB01 regmask=[x4] minReg=1 last fixed wt=100.00>
<RefPosition #203 @212 RefTypeUse <Ivl:76> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #204 @213 RefTypeKill BB01 regmask=[x0-xip1 lr d0-d7 d16-d31 p0-p15] minReg=1>
TUPLE STYLE DUMP WITH REF POSITIONS
Incoming Parameters: 
BB01 [0000] [000..078) (return), preds={} succs={}
=====
  N002.                    IL_OFFSET INLRT @ 0x000[E-]
  N004.                    CNS_INT(h)  'RunBasicScenario_Load'
        Def:<I0>(#1)
  N006.                    PUTARG_REG
                               Use:<I0>(#3) Fixed:x0(#2) *
        Def:<I1>(#5) x0
  N008.                    CNS_INT(h) 0x7ffac2114528 ftn
        Def:<I2>(#6)
  N010.                    IND      
                               Use:<I2>(#7) *
        Def:<I3>(#8)
  N012.                    CALL     
                               Use:<I1>(#10) Fixed:x0(#9) *
                               Use:<I3>(#11) *
        Kill: [x0-xip1 lr d0-d7 d16-d31 p0-p15] 
  N014.                    IL_OFFSET INLRT @ 0x00A[E-]
  N016.                    CNS_INT   31
  N018.                    HWINTRINSIC
        Def:<I4>(#13)
  N020.                    HWINTRINSIC
                               Use:<I4>(#14) *
        Def:<I5>(#15)
  N022.                    V01 MEM
                               Use:<I5>(#16) *
  N024.                    IL_OFFSET INLRT @ 0x012[E-]
  N026.                    V00 MEM
        Def:<I6>(#17)
  N028.                    NULLCHECK
                               Use:<I6>(#18) *
  N030.                    V00 MEM
        Def:<I7>(#19)
  N032.                    CNS_INT   80 Fseq[_dataTable]
  N034.                    ADD      
                               Use:<I7>(#20) *
        Def:<I8>(#21)
  N036.                    PUTARG_REG
                               Use:<I8>(#23) Fixed:x0(#22) *
        Def:<I9>(#25) x0
  N038.                    CNS_INT(h) 0x7ffac1def648 ftn
        Def:<I10>(#26)
  N040.                    IND      
                               Use:<I10>(#27) *
        Def:<I11>(#28)
  N042.                    CALL     
                               Use:<I9>(#30) Fixed:x0(#29) *
                               Use:<I11>(#31) *
        Kill: [x0-xip1 lr d0-d7 d16-d31 p0-p15] 
        Def:<I12>(#34) x0
  N044.                    V01 MEM
        Def:<I13>(#35)
  N046.                    HWINTRINSIC
        Def:<I14>(#36)
  N048.                    HWINTRINSIC
                               Use:<I14>(#37) *
                               Use:<I13>(#38) *
        Def:<I15>(#39)
  N050.                    HWINTRINSIC
                               Use:<I15>(#40) *
                               Use:<I12>(#41) *
        Def:<I16>(#42)
  N052.                    V04 MEM
                               Use:<I16>(#43) *
  N054.                    V00 MEM
        Def:<I17>(#44)
  N056.                    NULLCHECK
                               Use:<I17>(#45) *
  N058.                    V00 MEM
        Def:<I18>(#46)
  N060.                    CNS_INT   80 Fseq[_dataTable]
  N062.                    ADD      
                               Use:<I18>(#47) *
        Def:<I19>(#48)
  N064.                    PUTARG_REG
                               Use:<I19>(#50) Fixed:x0(#49) *
        Def:<I20>(#52) x0
  N066.                    CNS_INT(h) 0x7ffac1def660 ftn
        Def:<I21>(#53)
  N068.                    IND      
                               Use:<I21>(#54) *
        Def:<I22>(#55)
  N070.                    CALL     
                               Use:<I20>(#57) Fixed:x0(#56) *
                               Use:<I22>(#58) *
        Kill: [x0-xip1 lr d0-d7 d16-d31 p0-p15] 
        Def:<I23>(#61) x0
  N072.                    V01 MEM
        Def:<I24>(#62)
  N074.                    HWINTRINSIC
        Def:<I25>(#63)
  N076.                    HWINTRINSIC
                               Use:<I25>(#64) *
                               Use:<I24>(#65) *
        Def:<I26>(#66)
  N078.                    HWINTRINSIC
                               Use:<I26>(#67) *
                               Use:<I23>(#68) *
        Def:<I27>(#69)
  N080.                    HWINTRINSIC
        Def:<I28>(#70)
  N082.                    HWINTRINSIC
                               Use:<I28>(#71) *
                               Use:<I27>(#72) *
        Def:<I29>(#73) Pref:<I34>
  N084.                    V04 MEM
        Def:<I30>(#74)
  N086.                    HWINTRINSIC
        Def:<I31>(#75)
  N088.                    HWINTRINSIC
                               Use:<I31>(#76) *
                               Use:<I30>(#77) *
        Def:<I32>(#78)
  N090.                    HWINTRINSIC
        Def:<I33>(#79)
  N092.                    CNS_VEC  <0x00000000, 0x00000000, 0x00000000, 0x00000000>
  N094.                    HWINTRINSIC
  N096.                    HWINTRINSIC
                               Use:<I33>(#80) *
                               Use:<I29>(#81) *
                               Use:<I32>(#82) *
        Def:<I34>(#83)
  N098.                    HWINTRINSIC
                               Use:<I34>(#84) *
        Def:<I35>(#85)
  N100.                    V02 MEM
                               Use:<I35>(#86) *
  N102.                    IL_OFFSET INLRT @ 0x03A[E-]
  N104.                    V00 MEM
        Def:<I36>(#87)
  N106.                    NULLCHECK
                               Use:<I36>(#88) *
  N108.                    V00 MEM
        Def:<I37>(#89)
  N110.                    CNS_INT   80 Fseq[_dataTable]
  N112.                    ADD      
                               Use:<I37>(#90) *
        Def:<I38>(#91)
  N114.                    PUTARG_REG
                               Use:<I38>(#93) Fixed:x0(#92) *
        Def:<I39>(#95) x0
  N116.                    CNS_INT(h) 0x7ffac1def678 ftn
        Def:<I40>(#96)
  N118.                    IND      
                               Use:<I40>(#97) *
        Def:<I41>(#98)
  N120.                    CALL     
                               Use:<I39>(#100) Fixed:x0(#99) *
                               Use:<I41>(#101) *
        Kill: [x0-xip1 lr d0-d7 d16-d31 p0-p15] 
        Def:<I42>(#104) x0
  N122.                    V02 MEM
        Def:<I43>(#105)
  N124.                    STOREIND 
                               Use:<I42>(#106) *
                               Use:<I43>(#107) *
  N126.                    IL_OFFSET INLRT @ 0x04B[E-]
  N128.                    V00 MEM
        Def:<I44>(#108)
  N130.                    NULLCHECK
                               Use:<I44>(#109) *
  N132.                    V00 MEM
        Def:<I45>(#110)
  N134.                    CNS_INT   80 Fseq[_dataTable]
  N136.                    ADD      
                               Use:<I45>(#111) *
        Def:<I46>(#112)
  N138.                    PUTARG_REG
                               Use:<I46>(#114) Fixed:x0(#113) *
        Def:<I47>(#116) x0
  N140.                    CNS_INT(h) 0x7ffac1def648 ftn
        Def:<I48>(#117)
  N142.                    IND      
                               Use:<I48>(#118) *
        Def:<I49>(#119)
  N144.                    CALL     
                               Use:<I47>(#121) Fixed:x0(#120) *
                               Use:<I49>(#122) *
        Kill: [x0-xip1 lr d0-d7 d16-d31 p0-p15] 
        Def:<I50>(#125) x0
  N146.                    V05 MEM
                               Use:<I50>(#126) *
  N148.                    V00 MEM
        Def:<I51>(#127)
  N150.                    NULLCHECK
                               Use:<I51>(#128) *
  N152.                    V00 MEM
        Def:<I52>(#129)
  N154.                    CNS_INT   80 Fseq[_dataTable]
  N156.                    ADD      
                               Use:<I52>(#130) *
        Def:<I53>(#131)
  N158.                    PUTARG_REG
                               Use:<I53>(#133) Fixed:x0(#132) *
        Def:<I54>(#135) x0
  N160.                    CNS_INT(h) 0x7ffac1def660 ftn
        Def:<I55>(#136)
  N162.                    IND      
                               Use:<I55>(#137) *
        Def:<I56>(#138)
  N164.                    CALL     
                               Use:<I54>(#140) Fixed:x0(#139) *
                               Use:<I56>(#141) *
        Kill: [x0-xip1 lr d0-d7 d16-d31 p0-p15] 
        Def:<I57>(#144) x0
  N166.                    V06 MEM
                               Use:<I57>(#145) *
  N168.                    V00 MEM
        Def:<I58>(#146)
  N170.                    NULLCHECK
                               Use:<I58>(#147) *
  N172.                    V00 MEM
        Def:<I59>(#148)
  N174.                    CNS_INT   80 Fseq[_dataTable]
  N176.                    ADD      
                               Use:<I59>(#149) *
        Def:<I60>(#150)
  N178.                    PUTARG_REG
                               Use:<I60>(#152) Fixed:x0(#151) *
        Def:<I61>(#154) x0
  N180.                    CNS_INT(h) 0x7ffac1def678 ftn
        Def:<I62>(#155)
  N182.                    IND      
                               Use:<I62>(#156) *
        Def:<I63>(#157)
  N184.                    CALL     
                               Use:<I61>(#159) Fixed:x0(#158) *
                               Use:<I63>(#160) *
        Kill: [x0-xip1 lr d0-d7 d16-d31 p0-p15] 
        Def:<I64>(#163) x0
  N186.                    V07 MEM
                               Use:<I64>(#164) *
  N188.                    V07 MEM
        Def:<I65>(#165)
  N190.                    PUTARG_REG
                               Use:<I65>(#167) Fixed:x3(#166) *
        Def:<I66>(#169) x3
  N192.                    V05 MEM
        Def:<I67>(#170)
  N194.                    PUTARG_REG
                               Use:<I67>(#172) Fixed:x1(#171) *
        Def:<I68>(#174) x1
  N196.                    V06 MEM
        Def:<I69>(#175)
  N198.                    PUTARG_REG
                               Use:<I69>(#177) Fixed:x2(#176) *
        Def:<I70>(#179) x2
  N200.                    V00 MEM
        Def:<I71>(#180)
  N202.                    PUTARG_REG
                               Use:<I71>(#182) Fixed:x0(#181) *
        Def:<I72>(#184) x0
  N204.                    CNS_INT(h)  'RunBasicScenario_Load'
        Def:<I73>(#185)
  N206.                    PUTARG_REG
                               Use:<I73>(#187) Fixed:x4(#186) *
        Def:<I74>(#189) x4
  N208.                    CNS_INT(h) 0x7ffac1def8b8 ftn
        Def:<I75>(#190)
  N210.                    IND      
                               Use:<I75>(#191) *
        Def:<I76>(#192)
  N212.                    CALL     
                               Use:<I66>(#194) Fixed:x3(#193) *
                               Use:<I68>(#196) Fixed:x1(#195) *
                               Use:<I70>(#198) Fixed:x2(#197) *
                               Use:<I72>(#200) Fixed:x0(#199) *
                               Use:<I74>(#202) Fixed:x4(#201) *
                               Use:<I76>(#203) *
        Kill: [x0-xip1 lr d0-d7 d16-d31 p0-p15] 
  N214.                    IL_OFFSET INLRT @ 0x077[E-]
  N216.                    RETURN   




Linear scan intervals after buildIntervals:
Interval  0: ref (constant) RefPositions {#1@5 #3@6} physReg:NA Preferences=[x0] Aversions=[]
Interval  1: ref RefPositions {#5@7 #10@12} physReg:NA Preferences=[x0] Aversions=[]
Interval  2: long (constant) RefPositions {#6@9 #7@10} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval  3: long RefPositions {#8@11 #11@12} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval  4: mask RefPositions {#13@19 #14@20} physReg:NA Preferences=[allMask] Aversions=[]
Interval  5: simd16 RefPositions {#15@21 #16@22} physReg:NA Preferences=[allFloat] Aversions=[]
Interval  6: ref RefPositions {#17@27 #18@28} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval  7: ref RefPositions {#19@31 #20@34} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval  8: byref RefPositions {#21@35 #23@36} physReg:NA Preferences=[x0] Aversions=[]
Interval  9: byref RefPositions {#25@37 #30@42} physReg:NA Preferences=[x0] Aversions=[]
Interval 10: long (constant) RefPositions {#26@39 #27@40} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 11: long RefPositions {#28@41 #31@42} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 12: long RefPositions {#34@43 #41@50} physReg:NA Preferences=[x0] Aversions=[]
Interval 13: simd16 RefPositions {#35@45 #38@48} physReg:NA Preferences=[allFloat] Aversions=[]
Interval 14: mask RefPositions {#36@47 #37@48} physReg:NA Preferences=[p0-p7] Aversions=[]
Interval 15: mask RefPositions {#39@49 #40@50} physReg:NA Preferences=[p0-p7] Aversions=[]
Interval 16: simd16 RefPositions {#42@51 #43@52} physReg:NA Preferences=[allFloat] Aversions=[]
Interval 17: ref RefPositions {#44@55 #45@56} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 18: ref RefPositions {#46@59 #47@62} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 19: byref RefPositions {#48@63 #50@64} physReg:NA Preferences=[x0] Aversions=[]
Interval 20: byref RefPositions {#52@65 #57@70} physReg:NA Preferences=[x0] Aversions=[]
Interval 21: long (constant) RefPositions {#53@67 #54@68} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 22: long RefPositions {#55@69 #58@70} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 23: long RefPositions {#61@71 #68@78} physReg:NA Preferences=[x0] Aversions=[]
Interval 24: simd16 RefPositions {#62@73 #65@76} physReg:NA Preferences=[allFloat] Aversions=[]
Interval 25: mask RefPositions {#63@75 #64@76} physReg:NA Preferences=[p0-p7] Aversions=[]
Interval 26: mask RefPositions {#66@77 #67@78} physReg:NA Preferences=[p0-p7] Aversions=[]
Interval 27: simd16 RefPositions {#69@79 #72@82} physReg:NA Preferences=[allFloat] Aversions=[]
Interval 28: mask RefPositions {#70@81 #71@82} physReg:NA Preferences=[p0-p7] Aversions=[]
Interval 29: mask RefPositions {#73@83 #81@96} physReg:NA Preferences=[allMask] Aversions=[] RelatedInterval <I34>
Interval 30: simd16 RefPositions {#74@85 #77@88} physReg:NA Preferences=[allFloat] Aversions=[]
Interval 31: mask RefPositions {#75@87 #76@88} physReg:NA Preferences=[p0-p7] Aversions=[]
Interval 32: mask RefPositions {#78@89 #82@96} physReg:NA Preferences=[allMask] Aversions=[]
Interval 33: mask RefPositions {#79@91 #80@96} physReg:NA Preferences=[allMask] Aversions=[]
Interval 34: mask (interfering uses) RefPositions {#83@97 #84@98} physReg:NA Preferences=[allMask] Aversions=[]
Interval 35: simd16 RefPositions {#85@99 #86@100} physReg:NA Preferences=[allFloat] Aversions=[]
Interval 36: ref RefPositions {#87@105 #88@106} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 37: ref RefPositions {#89@109 #90@112} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 38: byref RefPositions {#91@113 #93@114} physReg:NA Preferences=[x0] Aversions=[]
Interval 39: byref RefPositions {#95@115 #100@120} physReg:NA Preferences=[x0] Aversions=[]
Interval 40: long (constant) RefPositions {#96@117 #97@118} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 41: long RefPositions {#98@119 #101@120} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 42: long RefPositions {#104@121 #106@124} physReg:NA Preferences=[x0] Aversions=[]
Interval 43: simd16 RefPositions {#105@123 #107@124} physReg:NA Preferences=[allFloat] Aversions=[]
Interval 44: ref RefPositions {#108@129 #109@130} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 45: ref RefPositions {#110@133 #111@136} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 46: byref RefPositions {#112@137 #114@138} physReg:NA Preferences=[x0] Aversions=[]
Interval 47: byref RefPositions {#116@139 #121@144} physReg:NA Preferences=[x0] Aversions=[]
Interval 48: long (constant) RefPositions {#117@141 #118@142} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 49: long RefPositions {#119@143 #122@144} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 50: long RefPositions {#125@145 #126@146} physReg:NA Preferences=[x0] Aversions=[]
Interval 51: ref RefPositions {#127@149 #128@150} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 52: ref RefPositions {#129@153 #130@156} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 53: byref RefPositions {#131@157 #133@158} physReg:NA Preferences=[x0] Aversions=[]
Interval 54: byref RefPositions {#135@159 #140@164} physReg:NA Preferences=[x0] Aversions=[]
Interval 55: long (constant) RefPositions {#136@161 #137@162} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 56: long RefPositions {#138@163 #141@164} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 57: long RefPositions {#144@165 #145@166} physReg:NA Preferences=[x0] Aversions=[]
Interval 58: ref RefPositions {#146@169 #147@170} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 59: ref RefPositions {#148@173 #149@176} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 60: byref RefPositions {#150@177 #152@178} physReg:NA Preferences=[x0] Aversions=[]
Interval 61: byref RefPositions {#154@179 #159@184} physReg:NA Preferences=[x0] Aversions=[]
Interval 62: long (constant) RefPositions {#155@181 #156@182} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 63: long RefPositions {#157@183 #160@184} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 64: long RefPositions {#163@185 #164@186} physReg:NA Preferences=[x0] Aversions=[]
Interval 65: long RefPositions {#165@189 #167@190} physReg:NA Preferences=[x3] Aversions=[]
Interval 66: long RefPositions {#169@191 #194@212} physReg:NA Preferences=[x3] Aversions=[]
Interval 67: long RefPositions {#170@193 #172@194} physReg:NA Preferences=[x1] Aversions=[]
Interval 68: long RefPositions {#174@195 #196@212} physReg:NA Preferences=[x1] Aversions=[]
Interval 69: long RefPositions {#175@197 #177@198} physReg:NA Preferences=[x2] Aversions=[]
Interval 70: long RefPositions {#179@199 #198@212} physReg:NA Preferences=[x2] Aversions=[]
Interval 71: ref RefPositions {#180@201 #182@202} physReg:NA Preferences=[x0] Aversions=[]
Interval 72: ref RefPositions {#184@203 #200@212} physReg:NA Preferences=[x0] Aversions=[]
Interval 73: ref (constant) RefPositions {#185@205 #187@206} physReg:NA Preferences=[x4] Aversions=[]
Interval 74: ref RefPositions {#189@207 #202@212} physReg:NA Preferences=[x4] Aversions=[]
Interval 75: long (constant) RefPositions {#190@209 #191@210} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 76: long RefPositions {#192@211 #203@212} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]

*************** In LinearScan::allocateRegistersMinimal()

Linear scan intervals before allocateRegistersMinimal:
Interval  0: ref (constant) RefPositions {#1@5 #3@6} physReg:NA Preferences=[x0] Aversions=[]
Interval  1: ref RefPositions {#5@7 #10@12} physReg:NA Preferences=[x0] Aversions=[]
Interval  2: long (constant) RefPositions {#6@9 #7@10} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval  3: long RefPositions {#8@11 #11@12} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval  4: mask RefPositions {#13@19 #14@20} physReg:NA Preferences=[allMask] Aversions=[]
Interval  5: simd16 RefPositions {#15@21 #16@22} physReg:NA Preferences=[allFloat] Aversions=[]
Interval  6: ref RefPositions {#17@27 #18@28} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval  7: ref RefPositions {#19@31 #20@34} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval  8: byref RefPositions {#21@35 #23@36} physReg:NA Preferences=[x0] Aversions=[]
Interval  9: byref RefPositions {#25@37 #30@42} physReg:NA Preferences=[x0] Aversions=[]
Interval 10: long (constant) RefPositions {#26@39 #27@40} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 11: long RefPositions {#28@41 #31@42} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 12: long RefPositions {#34@43 #41@50} physReg:NA Preferences=[x0] Aversions=[]
Interval 13: simd16 RefPositions {#35@45 #38@48} physReg:NA Preferences=[allFloat] Aversions=[]
Interval 14: mask RefPositions {#36@47 #37@48} physReg:NA Preferences=[p0-p7] Aversions=[]
Interval 15: mask RefPositions {#39@49 #40@50} physReg:NA Preferences=[p0-p7] Aversions=[]
Interval 16: simd16 RefPositions {#42@51 #43@52} physReg:NA Preferences=[allFloat] Aversions=[]
Interval 17: ref RefPositions {#44@55 #45@56} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 18: ref RefPositions {#46@59 #47@62} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 19: byref RefPositions {#48@63 #50@64} physReg:NA Preferences=[x0] Aversions=[]
Interval 20: byref RefPositions {#52@65 #57@70} physReg:NA Preferences=[x0] Aversions=[]
Interval 21: long (constant) RefPositions {#53@67 #54@68} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 22: long RefPositions {#55@69 #58@70} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 23: long RefPositions {#61@71 #68@78} physReg:NA Preferences=[x0] Aversions=[]
Interval 24: simd16 RefPositions {#62@73 #65@76} physReg:NA Preferences=[allFloat] Aversions=[]
Interval 25: mask RefPositions {#63@75 #64@76} physReg:NA Preferences=[p0-p7] Aversions=[]
Interval 26: mask RefPositions {#66@77 #67@78} physReg:NA Preferences=[p0-p7] Aversions=[]
Interval 27: simd16 RefPositions {#69@79 #72@82} physReg:NA Preferences=[allFloat] Aversions=[]
Interval 28: mask RefPositions {#70@81 #71@82} physReg:NA Preferences=[p0-p7] Aversions=[]
Interval 29: mask RefPositions {#73@83 #81@96} physReg:NA Preferences=[allMask] Aversions=[] RelatedInterval <I34>
Interval 30: simd16 RefPositions {#74@85 #77@88} physReg:NA Preferences=[allFloat] Aversions=[]
Interval 31: mask RefPositions {#75@87 #76@88} physReg:NA Preferences=[p0-p7] Aversions=[]
Interval 32: mask RefPositions {#78@89 #82@96} physReg:NA Preferences=[allMask] Aversions=[]
Interval 33: mask RefPositions {#79@91 #80@96} physReg:NA Preferences=[allMask] Aversions=[]
Interval 34: mask (interfering uses) RefPositions {#83@97 #84@98} physReg:NA Preferences=[allMask] Aversions=[]
Interval 35: simd16 RefPositions {#85@99 #86@100} physReg:NA Preferences=[allFloat] Aversions=[]
Interval 36: ref RefPositions {#87@105 #88@106} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 37: ref RefPositions {#89@109 #90@112} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 38: byref RefPositions {#91@113 #93@114} physReg:NA Preferences=[x0] Aversions=[]
Interval 39: byref RefPositions {#95@115 #100@120} physReg:NA Preferences=[x0] Aversions=[]
Interval 40: long (constant) RefPositions {#96@117 #97@118} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 41: long RefPositions {#98@119 #101@120} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 42: long RefPositions {#104@121 #106@124} physReg:NA Preferences=[x0] Aversions=[]
Interval 43: simd16 RefPositions {#105@123 #107@124} physReg:NA Preferences=[allFloat] Aversions=[]
Interval 44: ref RefPositions {#108@129 #109@130} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 45: ref RefPositions {#110@133 #111@136} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 46: byref RefPositions {#112@137 #114@138} physReg:NA Preferences=[x0] Aversions=[]
Interval 47: byref RefPositions {#116@139 #121@144} physReg:NA Preferences=[x0] Aversions=[]
Interval 48: long (constant) RefPositions {#117@141 #118@142} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 49: long RefPositions {#119@143 #122@144} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 50: long RefPositions {#125@145 #126@146} physReg:NA Preferences=[x0] Aversions=[]
Interval 51: ref RefPositions {#127@149 #128@150} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 52: ref RefPositions {#129@153 #130@156} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 53: byref RefPositions {#131@157 #133@158} physReg:NA Preferences=[x0] Aversions=[]
Interval 54: byref RefPositions {#135@159 #140@164} physReg:NA Preferences=[x0] Aversions=[]
Interval 55: long (constant) RefPositions {#136@161 #137@162} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 56: long RefPositions {#138@163 #141@164} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 57: long RefPositions {#144@165 #145@166} physReg:NA Preferences=[x0] Aversions=[]
Interval 58: ref RefPositions {#146@169 #147@170} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 59: ref RefPositions {#148@173 #149@176} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 60: byref RefPositions {#150@177 #152@178} physReg:NA Preferences=[x0] Aversions=[]
Interval 61: byref RefPositions {#154@179 #159@184} physReg:NA Preferences=[x0] Aversions=[]
Interval 62: long (constant) RefPositions {#155@181 #156@182} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 63: long RefPositions {#157@183 #160@184} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 64: long RefPositions {#163@185 #164@186} physReg:NA Preferences=[x0] Aversions=[]
Interval 65: long RefPositions {#165@189 #167@190} physReg:NA Preferences=[x3] Aversions=[]
Interval 66: long RefPositions {#169@191 #194@212} physReg:NA Preferences=[x3] Aversions=[]
Interval 67: long RefPositions {#170@193 #172@194} physReg:NA Preferences=[x1] Aversions=[]
Interval 68: long RefPositions {#174@195 #196@212} physReg:NA Preferences=[x1] Aversions=[]
Interval 69: long RefPositions {#175@197 #177@198} physReg:NA Preferences=[x2] Aversions=[]
Interval 70: long RefPositions {#179@199 #198@212} physReg:NA Preferences=[x2] Aversions=[]
Interval 71: ref RefPositions {#180@201 #182@202} physReg:NA Preferences=[x0] Aversions=[]
Interval 72: ref RefPositions {#184@203 #200@212} physReg:NA Preferences=[x0] Aversions=[]
Interval 73: ref (constant) RefPositions {#185@205 #187@206} physReg:NA Preferences=[x4] Aversions=[]
Interval 74: ref RefPositions {#189@207 #202@212} physReg:NA Preferences=[x4] Aversions=[]
Interval 75: long (constant) RefPositions {#190@209 #191@210} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]
Interval 76: long RefPositions {#192@211 #203@212} physReg:NA Preferences=[x0-xip0 x19-x28] Aversions=[]

------------
REFPOSITIONS BEFORE ALLOCATION: 
------------
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<RefPosition #169 @191 RefTypeDef <Ivl:66> PUTARG_REG BB01 regmask=[x3] minReg=1 fixed wt=400.00>
<RefPosition #170 @193 RefTypeDef <Ivl:67> LCL_VAR BB01 regmask=[x1] minReg=1 wt=400.00>
<RefPosition #171 @194 RefTypeFixedReg <Reg:x1 > BB01 regmask=[x1] minReg=1 wt=100.00>
<RefPosition #172 @194 RefTypeUse <Ivl:67> BB01 regmask=[x1] minReg=1 last fixed wt=100.00>
<RefPosition #173 @195 RefTypeFixedReg <Reg:x1 > BB01 regmask=[x1] minReg=1 wt=100.00>
<RefPosition #174 @195 RefTypeDef <Ivl:68> PUTARG_REG BB01 regmask=[x1] minReg=1 fixed wt=400.00>
<RefPosition #175 @197 RefTypeDef <Ivl:69> LCL_VAR BB01 regmask=[x2] minReg=1 wt=400.00>
<RefPosition #176 @198 RefTypeFixedReg <Reg:x2 > BB01 regmask=[x2] minReg=1 wt=100.00>
<RefPosition #177 @198 RefTypeUse <Ivl:69> BB01 regmask=[x2] minReg=1 last fixed wt=100.00>
<RefPosition #178 @199 RefTypeFixedReg <Reg:x2 > BB01 regmask=[x2] minReg=1 wt=100.00>
<RefPosition #179 @199 RefTypeDef <Ivl:70> PUTARG_REG BB01 regmask=[x2] minReg=1 fixed wt=400.00>
<RefPosition #180 @201 RefTypeDef <Ivl:71> LCL_VAR BB01 regmask=[x0] minReg=1 wt=400.00>
<RefPosition #181 @202 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #182 @202 RefTypeUse <Ivl:71> BB01 regmask=[x0] minReg=1 last fixed wt=100.00>
<RefPosition #183 @203 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #184 @203 RefTypeDef <Ivl:72> PUTARG_REG BB01 regmask=[x0] minReg=1 fixed wt=400.00>
<RefPosition #185 @205 RefTypeDef <Ivl:73> CNS_INT BB01 regmask=[x4] minReg=1 wt=400.00>
<RefPosition #186 @206 RefTypeFixedReg <Reg:x4 > BB01 regmask=[x4] minReg=1 wt=100.00>
<RefPosition #187 @206 RefTypeUse <Ivl:73> BB01 regmask=[x4] minReg=1 last fixed wt=100.00>
<RefPosition #188 @207 RefTypeFixedReg <Reg:x4 > BB01 regmask=[x4] minReg=1 wt=100.00>
<RefPosition #189 @207 RefTypeDef <Ivl:74> PUTARG_REG BB01 regmask=[x4] minReg=1 fixed wt=400.00>
<RefPosition #190 @209 RefTypeDef <Ivl:75> CNS_INT BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #191 @210 RefTypeUse <Ivl:75> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #192 @211 RefTypeDef <Ivl:76> IND BB01 regmask=[x0-xip0 x19-x28] minReg=1 wt=400.00>
<RefPosition #193 @212 RefTypeFixedReg <Reg:x3 > BB01 regmask=[x3] minReg=1 wt=100.00>
<RefPosition #194 @212 RefTypeUse <Ivl:66> BB01 regmask=[x3] minReg=1 last fixed wt=100.00>
<RefPosition #195 @212 RefTypeFixedReg <Reg:x1 > BB01 regmask=[x1] minReg=1 wt=100.00>
<RefPosition #196 @212 RefTypeUse <Ivl:68> BB01 regmask=[x1] minReg=1 last fixed wt=100.00>
<RefPosition #197 @212 RefTypeFixedReg <Reg:x2 > BB01 regmask=[x2] minReg=1 wt=100.00>
<RefPosition #198 @212 RefTypeUse <Ivl:70> BB01 regmask=[x2] minReg=1 last fixed wt=100.00>
<RefPosition #199 @212 RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #200 @212 RefTypeUse <Ivl:72> BB01 regmask=[x0] minReg=1 last fixed wt=100.00>
<RefPosition #201 @212 RefTypeFixedReg <Reg:x4 > BB01 regmask=[x4] minReg=1 wt=100.00>
<RefPosition #202 @212 RefTypeUse <Ivl:74> BB01 regmask=[x4] minReg=1 last fixed wt=100.00>
<RefPosition #203 @212 RefTypeUse <Ivl:76> BB01 regmask=[x0-xip0 x19-x28] minReg=1 last wt=100.00>
<RefPosition #204 @213 RefTypeKill BB01 regmask=[x0-xip1 lr d0-d7 d16-d31 p0-p15] minReg=1>


Allocating Registers
--------------------
The following table has one or more rows for each RefPosition that is handled during allocation.
The columns are: (1) Loc: LSRA location, (2) RP#: RefPosition number, (3) Name, (4) Type (e.g. Def, Use,
Fixd, Parm, DDef (Dummy Def), ExpU (Exposed Use), Kill) followed by a '*' if it is a last use, and a 'D'
if it is delayRegFree, (5) Action taken during allocation. Some actions include (a) Alloc a new register,
(b) Keep an existing register, (c) Spill a register, (d) ReLod (Reload) a register. If an ALL-CAPS name
such as COVRS is displayed, it is a score name from lsra_score.h, with a trailing '(A)' indicating alloc,
'(C)' indicating copy, and '(R)' indicating re-use. See dumpLsraAllocationEvent() for details.
The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is
active, 'p' if it is a large vector that has been partially spilled, and 'i' if it is inactive.
Columns are only printed up to the last modified register, which may increase during allocation,
in which case additional columns will appear. Registers which are not marked modified have ---- in
their column.

--------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID   Loc RP#  Name Type  Action    Reg  |x0  |x1  |x2  |x3  |x4  |x5  |x6  |x7  |x19 |x20 |d0  |d1  |d2  |d8  |d9  |
--------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
                                            |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
           0.#0   BB1 PredBB0               |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000051]   5.#1   C0   Def    Alloc    x0   |C0 a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000097]   6.#2   x0   Fixd   Keep     x0   |C0 a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |
           6.#3   C0   Use *  Keep     x0   |C0 a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |
           7.#4   x0   Fixd   Keep     x0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
           7.#5   I1   Def    Alloc    x0   |I1 a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000098]   9.#6   C2   Def    ORDER(A) x1   |I1 a|C2 a|    |    |    |    |    |    |    |    |    |    |    |    |    |
[000099]  10.#7   C2   Use *  Keep     x1   |I1 a|C2 a|    |    |    |    |    |    |    |    |    |    |    |    |    |
          11.#8   I3   Def    ORDER(A) x1   |I1 a|I3 a|    |    |    |    |    |    |    |    |    |    |    |    |    |
[000001]  12.#9   x0   Fixd   Keep     x0   |I1 a|I3 a|    |    |    |    |    |    |    |    |    |    |    |    |    |
          12.#10  I1   Use *  Keep     x0   |I1 a|I3 a|    |    |    |    |    |    |    |    |    |    |    |    |    |
          12.#11  I3   Use *  Keep     x1   |I1 a|I3 a|    |    |    |    |    |    |    |    |    |    |    |    |    |
          13.#12       Kill   None     [x0-xip1 lr d0-d7 d16-d31 p0-p15]
                                            |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
--------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID   Loc RP#  Name Type  Action    Reg  |x0  |x1  |x2  |x3  |x4  |x5  |x6  |x7  |x19 |x20 |d0  |d1  |d2  |d8  |d9  |p0  |
--------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
[000003]  19.#13  I4   Def    ORDER(A) p0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I4 a|
[000004]  20.#14  I4   Use *  Keep     p0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I4 a|
--------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID   Loc RP#  Name Type  Action    Reg  |x0  |x1  |x2  |x3  |x4  |x5  |x6  |x7  |x19 |x20 |d0  |d1  |d2  |d8  |d9  |d16 |p0  |
--------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
          21.#15  I5   Def    ORDER(A) d16  |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I5 a|    |
[000005]  22.#16  I5   Use *  Keep     d16  |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I5 a|    |
[000052]  27.#17  I6   Def    ORDER(A) x0   |I6 a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000053]  28.#18  I6   Use *  Keep     x0   |I6 a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000054]  31.#19  I7   Def    ORDER(A) x0   |I7 a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000056]  34.#20  I7   Use *  Keep     x0   |I7 a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          35.#21  I8   Def    Alloc    x0   |I8 a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000100]  36.#22  x0   Fixd   Keep     x0   |I8 a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          36.#23  I8   Use *  Keep     x0   |I8 a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          37.#24  x0   Fixd   Keep     x0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          37.#25  I9   Def    Alloc    x0   |I9 a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000101]  39.#26  C10  Def    ORDER(A) x1   |I9 a|C10a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000102]  40.#27  C10  Use *  Keep     x1   |I9 a|C10a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          41.#28  I11  Def    ORDER(A) x1   |I9 a|I11a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000009]  42.#29  x0   Fixd   Keep     x0   |I9 a|I11a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          42.#30  I9   Use *  Keep     x0   |I9 a|I11a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          42.#31  I11  Use *  Keep     x1   |I9 a|I11a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          43.#32       Kill   None     [x0-xip1 lr d0-d7 d16-d31 p0-p15]
                                            |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          43.#33  x0   Fixd   Keep     x0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          43.#34  I12  Def    Alloc    x0   |I12a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000006]  45.#35  I13  Def    ORDER(A) d16  |I12a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |I13a|    |
[000011]  47.#36  I14  Def    ORDER(A) p0   |I12a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |I13a|I14a|
[000012]  48.#37  I14  Use *  Keep     p0   |I12a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |I13a|I14a|
          48.#38  I13  Use *  Keep     d16  |I12a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |I13a|I14a|
          49.#39  I15  Def    ORDER(A) p0   |I12a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I15a|
[000010]  50.#40  I15  Use *  Keep     p0   |I12a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I15a|
          50.#41  I12  Use *  Keep     x0   |I12a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I15a|
          51.#42  I16  Def    ORDER(A) d16  |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I16a|    |
[000017]  52.#43  I16  Use *  Keep     d16  |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I16a|    |
[000058]  55.#44  I17  Def    ORDER(A) x0   |I17a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000059]  56.#45  I17  Use *  Keep     x0   |I17a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000060]  59.#46  I18  Def    ORDER(A) x0   |I18a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000062]  62.#47  I18  Use *  Keep     x0   |I18a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          63.#48  I19  Def    Alloc    x0   |I19a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000103]  64.#49  x0   Fixd   Keep     x0   |I19a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          64.#50  I19  Use *  Keep     x0   |I19a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          65.#51  x0   Fixd   Keep     x0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          65.#52  I20  Def    Alloc    x0   |I20a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000104]  67.#53  C21  Def    ORDER(A) x1   |I20a|C21a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000105]  68.#54  C21  Use *  Keep     x1   |I20a|C21a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          69.#55  I22  Def    ORDER(A) x1   |I20a|I22a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000016]  70.#56  x0   Fixd   Keep     x0   |I20a|I22a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          70.#57  I20  Use *  Keep     x0   |I20a|I22a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          70.#58  I22  Use *  Keep     x1   |I20a|I22a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          71.#59       Kill   None     [x0-xip1 lr d0-d7 d16-d31 p0-p15]
                                            |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          71.#60  x0   Fixd   Keep     x0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          71.#61  I23  Def    Alloc    x0   |I23a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000013]  73.#62  I24  Def    ORDER(A) d16  |I23a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |I24a|    |
[000020]  75.#63  I25  Def    ORDER(A) p0   |I23a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |I24a|I25a|
[000021]  76.#64  I25  Use *  Keep     p0   |I23a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |I24a|I25a|
          76.#65  I24  Use *  Keep     d16  |I23a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |I24a|I25a|
--------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID   Loc RP#  Name Type  Action    Reg  |x0  |x1  |x2  |x3  |x4  |x5  |x6  |x7  |x19 |x20 |d0  |d1  |d2  |d8  |d9  |d16 |p0  |
--------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
          77.#66  I26  Def    ORDER(A) p0   |I23a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I26a|
[000019]  78.#67  I26  Use *  Keep     p0   |I23a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I26a|
          78.#68  I23  Use *  Keep     x0   |I23a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I26a|
          79.#69  I27  Def    ORDER(A) d16  |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I27a|    |
[000025]  81.#70  I28  Def    ORDER(A) p0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I27a|I28a|
[000026]  82.#71  I28  Use *  Keep     p0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I27a|I28a|
          82.#72  I27  Use *  Keep     d16  |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I27a|I28a|
          83.#73  I29  Def    ORDER(A) p0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I29a|
[000018]  85.#74  I30  Def    ORDER(A) d16  |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I30a|I29a|
--------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID   Loc RP#  Name Type  Action    Reg  |x0  |x1  |x2  |x3  |x4  |x5  |x6  |x7  |x19 |x20 |d0  |d1  |d2  |d8  |d9  |d16 |p0  |p1  |
--------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
[000023]  87.#75  I31  Def    ORDER(A) p1   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I30a|I29a|I31a|
[000024]  88.#76  I31  Use *  Keep     p1   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I30a|I29a|I31a|
          88.#77  I30  Use *  Keep     d16  |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I30a|I29a|I31a|
          89.#78  I32  Def    ORDER(A) p1   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I29a|I32a|
--------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID   Loc RP#  Name Type  Action    Reg  |x0  |x1  |x2  |x3  |x4  |x5  |x6  |x7  |x19 |x20 |d0  |d1  |d2  |d8  |d9  |d16 |p0  |p1  |p2  |
--------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
[000106]  91.#79  I33  Def    ORDER(A) p2   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I29a|I32a|I33a|
[000108]  96.#80  I33  Use *D Keep     p2   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I29a|I32a|I33a|
          96.#81  I29  Use *  Keep     p0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I29a|I32a|I33a|
          96.#82  I32  Use *D Keep     p1   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I29a|I32a|I33a|
          97.#83  I34  Def    ORDER(A) p0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I34a|I32a|I33a|
[000027]  98.#84  I34  Use *  Keep     p0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I34a|    |    |
          99.#85  I35  Def    ORDER(A) d16  |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I35a|    |    |    |
[000028] 100.#86  I35  Use *  Keep     d16  |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I35a|    |    |    |
[000064] 105.#87  I36  Def    ORDER(A) x0   |I36a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000065] 106.#88  I36  Use *  Keep     x0   |I36a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000066] 109.#89  I37  Def    ORDER(A) x0   |I37a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000068] 112.#90  I37  Use *  Keep     x0   |I37a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         113.#91  I38  Def    Alloc    x0   |I38a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000109] 114.#92  x0   Fixd   Keep     x0   |I38a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         114.#93  I38  Use *  Keep     x0   |I38a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         115.#94  x0   Fixd   Keep     x0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         115.#95  I39  Def    Alloc    x0   |I39a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000110] 117.#96  C40  Def    ORDER(A) x1   |I39a|C40a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000111] 118.#97  C40  Use *  Keep     x1   |I39a|C40a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         119.#98  I41  Def    ORDER(A) x1   |I39a|I41a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000031] 120.#99  x0   Fixd   Keep     x0   |I39a|I41a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         120.#100 I39  Use *  Keep     x0   |I39a|I41a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         120.#101 I41  Use *  Keep     x1   |I39a|I41a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         121.#102      Kill   None     [x0-xip1 lr d0-d7 d16-d31 p0-p15]
                                            |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         121.#103 x0   Fixd   Keep     x0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         121.#104 I42  Def    Alloc    x0   |I42a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000032] 123.#105 I43  Def    ORDER(A) d16  |I42a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |I43a|    |    |    |
[000033] 124.#106 I42  Use *  Keep     x0   |I42a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |I43a|    |    |    |
         124.#107 I43  Use *  Keep     d16  |I42a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |I43a|    |    |    |
[000070] 129.#108 I44  Def    ORDER(A) x0   |I44a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000071] 130.#109 I44  Use *  Keep     x0   |I44a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000072] 133.#110 I45  Def    ORDER(A) x0   |I45a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000074] 136.#111 I45  Use *  Keep     x0   |I45a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         137.#112 I46  Def    Alloc    x0   |I46a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000112] 138.#113 x0   Fixd   Keep     x0   |I46a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         138.#114 I46  Use *  Keep     x0   |I46a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         139.#115 x0   Fixd   Keep     x0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         139.#116 I47  Def    Alloc    x0   |I47a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000113] 141.#117 C48  Def    ORDER(A) x1   |I47a|C48a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000114] 142.#118 C48  Use *  Keep     x1   |I47a|C48a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         143.#119 I49  Def    ORDER(A) x1   |I47a|I49a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000037] 144.#120 x0   Fixd   Keep     x0   |I47a|I49a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         144.#121 I47  Use *  Keep     x0   |I47a|I49a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         144.#122 I49  Use *  Keep     x1   |I47a|I49a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         145.#123      Kill   None     [x0-xip1 lr d0-d7 d16-d31 p0-p15]
                                            |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         145.#124 x0   Fixd   Keep     x0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         145.#125 I50  Def    Alloc    x0   |I50a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000041] 146.#126 I50  Use *  Keep     x0   |I50a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000076] 149.#127 I51  Def    ORDER(A) x0   |I51a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000077] 150.#128 I51  Use *  Keep     x0   |I51a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000078] 153.#129 I52  Def    ORDER(A) x0   |I52a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
--------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID   Loc RP#  Name Type  Action    Reg  |x0  |x1  |x2  |x3  |x4  |x5  |x6  |x7  |x19 |x20 |d0  |d1  |d2  |d8  |d9  |d16 |p0  |p1  |p2  |
--------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
[000080] 156.#130 I52  Use *  Keep     x0   |I52a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         157.#131 I53  Def    Alloc    x0   |I53a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000115] 158.#132 x0   Fixd   Keep     x0   |I53a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         158.#133 I53  Use *  Keep     x0   |I53a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         159.#134 x0   Fixd   Keep     x0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         159.#135 I54  Def    Alloc    x0   |I54a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000116] 161.#136 C55  Def    ORDER(A) x1   |I54a|C55a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000117] 162.#137 C55  Use *  Keep     x1   |I54a|C55a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         163.#138 I56  Def    ORDER(A) x1   |I54a|I56a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000040] 164.#139 x0   Fixd   Keep     x0   |I54a|I56a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         164.#140 I54  Use *  Keep     x0   |I54a|I56a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         164.#141 I56  Use *  Keep     x1   |I54a|I56a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         165.#142      Kill   None     [x0-xip1 lr d0-d7 d16-d31 p0-p15]
                                            |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         165.#143 x0   Fixd   Keep     x0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         165.#144 I57  Def    Alloc    x0   |I57a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000046] 166.#145 I57  Use *  Keep     x0   |I57a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000082] 169.#146 I58  Def    ORDER(A) x0   |I58a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000083] 170.#147 I58  Use *  Keep     x0   |I58a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000084] 173.#148 I59  Def    ORDER(A) x0   |I59a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000086] 176.#149 I59  Use *  Keep     x0   |I59a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         177.#150 I60  Def    Alloc    x0   |I60a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000118] 178.#151 x0   Fixd   Keep     x0   |I60a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         178.#152 I60  Use *  Keep     x0   |I60a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         179.#153 x0   Fixd   Keep     x0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         179.#154 I61  Def    Alloc    x0   |I61a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000119] 181.#155 C62  Def    ORDER(A) x1   |I61a|C62a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000120] 182.#156 C62  Use *  Keep     x1   |I61a|C62a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         183.#157 I63  Def    ORDER(A) x1   |I61a|I63a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000045] 184.#158 x0   Fixd   Keep     x0   |I61a|I63a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         184.#159 I61  Use *  Keep     x0   |I61a|I63a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         184.#160 I63  Use *  Keep     x1   |I61a|I63a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         185.#161      Kill   None     [x0-xip1 lr d0-d7 d16-d31 p0-p15]
                                            |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         185.#162 x0   Fixd   Keep     x0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         185.#163 I64  Def    Alloc    x0   |I64a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000089] 186.#164 I64  Use *  Keep     x0   |I64a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000090] 189.#165 I65  Def    Alloc    x3   |    |    |    |I65a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000121] 190.#166 x3   Fixd   Keep     x3   |    |    |    |I65a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         190.#167 I65  Use *  Keep     x3   |    |    |    |I65a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         191.#168 x3   Fixd   Keep     x3   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         191.#169 I66  Def    Alloc    x3   |    |    |    |I66a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000042] 193.#170 I67  Def    Alloc    x1   |    |I67a|    |I66a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000122] 194.#171 x1   Fixd   Keep     x1   |    |I67a|    |I66a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         194.#172 I67  Use *  Keep     x1   |    |I67a|    |I66a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         195.#173 x1   Fixd   Keep     x1   |    |    |    |I66a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         195.#174 I68  Def    Alloc    x1   |    |I68a|    |I66a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000047] 197.#175 I69  Def    Alloc    x2   |    |I68a|I69a|I66a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000123] 198.#176 x2   Fixd   Keep     x2   |    |I68a|I69a|I66a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         198.#177 I69  Use *  Keep     x2   |    |I68a|I69a|I66a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         199.#178 x2   Fixd   Keep     x2   |    |I68a|    |I66a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         199.#179 I70  Def    Alloc    x2   |    |I68a|I70a|I66a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000034] 201.#180 I71  Def    Alloc    x0   |I71a|I68a|I70a|I66a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000124] 202.#181 x0   Fixd   Keep     x0   |I71a|I68a|I70a|I66a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
--------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID   Loc RP#  Name Type  Action    Reg  |x0  |x1  |x2  |x3  |x4  |x5  |x6  |x7  |x19 |x20 |d0  |d1  |d2  |d8  |d9  |d16 |p0  |p1  |p2  |
--------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
         202.#182 I71  Use *  Keep     x0   |I71a|I68a|I70a|I66a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         203.#183 x0   Fixd   Keep     x0   |    |I68a|I70a|I66a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         203.#184 I72  Def    Alloc    x0   |I72a|I68a|I70a|I66a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000088] 205.#185 C73  Def    Alloc    x4   |I72a|I68a|I70a|I66a|C73a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000125] 206.#186 x4   Fixd   Keep     x4   |I72a|I68a|I70a|I66a|C73a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         206.#187 C73  Use *  Keep     x4   |I72a|I68a|I70a|I66a|C73a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         207.#188 x4   Fixd   Keep     x4   |I72a|I68a|I70a|I66a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         207.#189 I74  Def    Alloc    x4   |I72a|I68a|I70a|I66a|I74a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000126] 209.#190 C75  Def    ORDER(A) x5   |I72a|I68a|I70a|I66a|I74a|C75a|    |    |    |    |    |    |    |    |    |    |    |    |    |
[000127] 210.#191 C75  Use *  Keep     x5   |I72a|I68a|I70a|I66a|I74a|C75a|    |    |    |    |    |    |    |    |    |    |    |    |    |
         211.#192 I76  Def    ORDER(A) x5   |I72a|I68a|I70a|I66a|I74a|I76a|    |    |    |    |    |    |    |    |    |    |    |    |    |
[000049] 212.#193 x3   Fixd   Keep     x3   |I72a|I68a|I70a|I66a|I74a|I76a|    |    |    |    |    |    |    |    |    |    |    |    |    |
         212.#194 I66  Use *  Keep     x3   |I72a|I68a|I70a|I66a|I74a|I76a|    |    |    |    |    |    |    |    |    |    |    |    |    |
         212.#195 x1   Fixd   Keep     x1   |I72a|I68a|I70a|I66a|I74a|I76a|    |    |    |    |    |    |    |    |    |    |    |    |    |
         212.#196 I68  Use *  Keep     x1   |I72a|I68a|I70a|I66a|I74a|I76a|    |    |    |    |    |    |    |    |    |    |    |    |    |
         212.#197 x2   Fixd   Keep     x2   |I72a|I68a|I70a|I66a|I74a|I76a|    |    |    |    |    |    |    |    |    |    |    |    |    |
         212.#198 I70  Use *  Keep     x2   |I72a|I68a|I70a|I66a|I74a|I76a|    |    |    |    |    |    |    |    |    |    |    |    |    |
         212.#199 x0   Fixd   Keep     x0   |I72a|I68a|I70a|I66a|I74a|I76a|    |    |    |    |    |    |    |    |    |    |    |    |    |
         212.#200 I72  Use *  Keep     x0   |I72a|I68a|I70a|I66a|I74a|I76a|    |    |    |    |    |    |    |    |    |    |    |    |    |
         212.#201 x4   Fixd   Keep     x4   |I72a|I68a|I70a|I66a|I74a|I76a|    |    |    |    |    |    |    |    |    |    |    |    |    |
         212.#202 I74  Use *  Keep     x4   |I72a|I68a|I70a|I66a|I74a|I76a|    |    |    |    |    |    |    |    |    |    |    |    |    |
         212.#203 I76  Use *  Keep     x5   |I72a|I68a|I70a|I66a|I74a|I76a|    |    |    |    |    |    |    |    |    |    |    |    |    |
         213.#204      Kill   None     [x0-xip1 lr d0-d7 d16-d31 p0-p15]
                                            |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |

------------
REFPOSITIONS AFTER ALLOCATION: 
------------
<RefPosition #0   @0   RefTypeBB BB01 regmask=[] minReg=1 wt=100.00>
<RefPosition #1   @5   RefTypeDef <Ivl:0> CNS_INT BB01 regmask=[x0] minReg=1 wt=400.00>
<RefPosition #2   @6   RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #3   @6   RefTypeUse <Ivl:0> BB01 regmask=[x0] minReg=1 last fixed wt=100.00>
<RefPosition #4   @7   RefTypeFixedReg <Reg:x0 > BB01 regmask=[x0] minReg=1 wt=100.00>
<RefPosition #5   @7   RefTypeDef <Ivl:1> PUTARG_REG BB01 regmask=[x0] minReg=1 fixed wt=400.00>
<RefPosition #6   @9   RefTypeDef <Ivl:2> CNS_INT BB01 regmask=[x1] minReg=1 wt=400.00>
<RefPosition #7   @10  RefTypeUse <Ivl:2> BB01 regmask=[x1] minReg=1 last wt=100.00>
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Active intervals at end of allocation:

Trees after linear scan register allocator (LSRA)

---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   [IL range]   [jump]                            [EH region]        [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    [000..078)                           (return)                     i LIR hascall gcsafe nullcheck
---------------------------------------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [0000] [000..078) (return), preds={} succs={}
N002 (???,???) [000091] -----------                            IL_OFFSET void   INLRT @ 0x000[E-] REG NA
N004 (  3, 12) [000051] H----------                   t51 =    CNS_INT(h) ref     'RunBasicScenario_Load' REG x0
                                                            /--*  t51    ref    
N006 (???,???) [000097] -----------                   t97 = *  PUTARG_REG ref    REG x0
N008 (  3, 12) [000098] H----------                   t98 =    CNS_INT(h) long   0x7ffac2114528 ftn REG x1
                                                            /--*  t98    long   
N010 (  6, 14) [000099] n---G------                   t99 = *  IND       long   REG x1
                                                            /--*  t97    ref    arg0 in x0
                                                            +--*  t99    long   control expr
N012 ( 17, 15) [000001] --CXG------                         *  CALL      void   TestLibrary.TestFramework:BeginScenario(System.String) REG NA
N014 (???,???) [000092] -----------                            IL_OFFSET void   INLRT @ 0x00A[E-] REG NA
N016 (  1,  2) [000002] -c-----N---                    t2 =    CNS_INT   int    31 REG NA
                                                            /--*  t2     int    
N018 (  2,  3) [000003] -----------                    t3 = *  HWINTRINSIC mask   int CreateTrueMaskInt32 REG p0
                                                            /--*  t3     mask   
N020 (  3,  4) [000004] -----------                    t4 = *  HWINTRINSIC simd16 int ConvertMaskToVector REG d16
                                                            /--*  t4     simd16 
N022 (  7,  7) [000005] DA---------                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V01 loc0          NA REG NA
N024 (???,???) [000093] -----------                            IL_OFFSET void   INLRT @ 0x012[E-] REG NA
N026 (  3,  2) [000052] -----------                   t52 =    LCL_VAR   ref    V00 this          x0 REG x0
                                                            /--*  t52    ref    
N028 (  4,  3) [000053] ---X-O-----                         *  NULLCHECK byte   REG NA
N030 (  3,  2) [000054] -----------                   t54 =    LCL_VAR   ref    V00 this          x0 REG x0
N032 (  1,  2) [000055] -c---------                   t55 =    CNS_INT   long   80 Fseq[_dataTable] REG NA
                                                            /--*  t54    ref    
                                                            +--*  t55    long   
N034 (  5,  5) [000056] -----O-----                   t56 = *  ADD       byref  REG x0
                                                            /--*  t56    byref  
N036 (???,???) [000100] -----O-----                  t100 = *  PUTARG_REG byref  REG x0
N038 (  3, 12) [000101] H----------                  t101 =    CNS_INT(h) long   0x7ffac1def648 ftn REG x1
                                                            /--*  t101   long   
N040 (  6, 14) [000102] n---G------                  t102 = *  IND       long   REG x1
                                                            /--*  t100   byref  this in x0
                                                            +--*  t102   long   control expr
N042 ( 23, 11) [000009] --CXGO-----                    t9 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this REG x0
N044 (  3,  2) [000006] -----------                    t6 =    LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0          d16 REG d16
N046 (  1,  1) [000011] -----------                   t11 =    HWINTRINSIC mask   int CreateTrueMaskAll REG p0
                                                            /--*  t11    mask   
                                                            +--*  t6     simd16 
N048 (  5,  4) [000012] -----------                   t12 = *  HWINTRINSIC mask   int ConvertVectorToMask REG p0
                                                            /--*  t12    mask   
                                                            +--*  t9     long   
N050 ( 29, 16) [000010] --CXGO-----                   t10 = *  HWINTRINSIC simd16 int LoadVector REG d16
                                                            /--*  t10    simd16 
N052 ( 33, 19) [000017] DACXGO-----                         *  STORE_LCL_VAR simd16 V04 tmp1          NA REG NA
N054 (  3,  2) [000058] -----------                   t58 =    LCL_VAR   ref    V00 this          x0 REG x0
                                                            /--*  t58    ref    
N056 (  4,  3) [000059] ---X-O-----                         *  NULLCHECK byte   REG NA
N058 (  3,  2) [000060] -----------                   t60 =    LCL_VAR   ref    V00 this          x0 REG x0
N060 (  1,  2) [000061] -c---------                   t61 =    CNS_INT   long   80 Fseq[_dataTable] REG NA
                                                            /--*  t60    ref    
                                                            +--*  t61    long   
N062 (  5,  5) [000062] -----O-----                   t62 = *  ADD       byref  REG x0
                                                            /--*  t62    byref  
N064 (???,???) [000103] -----O-----                  t103 = *  PUTARG_REG byref  REG x0
N066 (  3, 12) [000104] H----------                  t104 =    CNS_INT(h) long   0x7ffac1def660 ftn REG x1
                                                            /--*  t104   long   
N068 (  6, 14) [000105] n---G------                  t105 = *  IND       long   REG x1
                                                            /--*  t103   byref  this in x0
                                                            +--*  t105   long   control expr
N070 ( 23, 11) [000016] --CXGO-----                   t16 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this REG x0
N072 (  3,  2) [000013] -----------                   t13 =    LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0          d16 REG d16
N074 (  1,  1) [000020] -----------                   t20 =    HWINTRINSIC mask   int CreateTrueMaskAll REG p0
                                                            /--*  t20    mask   
                                                            +--*  t13    simd16 
N076 (  5,  4) [000021] -----------                   t21 = *  HWINTRINSIC mask   int ConvertVectorToMask REG p0
                                                            /--*  t21    mask   
                                                            +--*  t16    long   
N078 ( 29, 16) [000019] --CXGO-----                   t19 = *  HWINTRINSIC simd16 int LoadVector REG d16
N080 (  1,  1) [000025] -----------                   t25 =    HWINTRINSIC mask   int CreateTrueMaskAll REG p0
                                                            /--*  t25    mask   
                                                            +--*  t19    simd16 
N082 ( 31, 18) [000026] --CXGO-----                   t26 = *  HWINTRINSIC mask   int ConvertVectorToMask REG p0
N084 (  3,  2) [000018] -----------                   t18 =    LCL_VAR   simd16 V04 tmp1          d16 REG d16
N086 (  1,  1) [000023] -----------                   t23 =    HWINTRINSIC mask   int CreateTrueMaskAll REG p1
                                                            /--*  t23    mask   
                                                            +--*  t18    simd16 
N088 (  5,  4) [000024] -----------                   t24 = *  HWINTRINSIC mask   int ConvertVectorToMask REG p1
N090 (???,???) [000106] -----------                  t106 =    HWINTRINSIC mask   int CreateTrueMaskAll REG p2
N092 (???,???) [000107] -c---------                  t107 =    CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000> REG NA
                                                            /--*  t24    mask   
                                                            +--*  t26    mask   
N094 ( 37, 23) [000022] -cCXGO-----                   t22 = *  HWINTRINSIC mask   int CreateBreakPropagateMask REG NA
                                                            /--*  t106   mask   
                                                            +--*  t22    mask   
                                                            +--*  t107   simd16 
N096 (???,???) [000108] --CXGO-----                  t108 = *  HWINTRINSIC mask   int ConditionalSelect REG p0
                                                            /--*  t108   mask   
N098 ( 38, 24) [000027] --CXGO-----                   t27 = *  HWINTRINSIC simd16 int ConvertMaskToVector REG d16
                                                            /--*  t27    simd16 
N100 ( 42, 27) [000028] DACXGO-----                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V02 loc1          NA REG NA
N102 (???,???) [000094] -----------                            IL_OFFSET void   INLRT @ 0x03A[E-] REG NA
N104 (  3,  2) [000064] -----------                   t64 =    LCL_VAR   ref    V00 this          x0 REG x0
                                                            /--*  t64    ref    
N106 (  4,  3) [000065] ---X-O-----                         *  NULLCHECK byte   REG NA
N108 (  3,  2) [000066] -----------                   t66 =    LCL_VAR   ref    V00 this          x0 REG x0
N110 (  1,  2) [000067] -c---------                   t67 =    CNS_INT   long   80 Fseq[_dataTable] REG NA
                                                            /--*  t66    ref    
                                                            +--*  t67    long   
N112 (  5,  5) [000068] -----O-----                   t68 = *  ADD       byref  REG x0
                                                            /--*  t68    byref  
N114 (???,???) [000109] -----O-----                  t109 = *  PUTARG_REG byref  REG x0
N116 (  3, 12) [000110] H----------                  t110 =    CNS_INT(h) long   0x7ffac1def678 ftn REG x1
                                                            /--*  t110   long   
N118 (  6, 14) [000111] n---G------                  t111 = *  IND       long   REG x1
                                                            /--*  t109   byref  this in x0
                                                            +--*  t111   long   control expr
N120 ( 23, 11) [000031] --CXGO-----                   t31 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this REG x0
N122 (  3,  2) [000032] -----------                   t32 =    LCL_VAR   simd16<System.Numerics.Vector`1> V02 loc1          d16 REG d16
                                                            /--*  t31    long   
                                                            +--*  t32    simd16 
N124 ( 30, 16) [000033] -ACXGO-----                         *  STOREIND  simd16 (copy) REG NA
N126 (???,???) [000095] -----------                            IL_OFFSET void   INLRT @ 0x04B[E-] REG NA
N128 (  3,  2) [000070] -----------                   t70 =    LCL_VAR   ref    V00 this          x0 REG x0
                                                            /--*  t70    ref    
N130 (  4,  3) [000071] ---X-O-----                         *  NULLCHECK byte   REG NA
N132 (  3,  2) [000072] -----------                   t72 =    LCL_VAR   ref    V00 this          x0 REG x0
N134 (  1,  2) [000073] -c---------                   t73 =    CNS_INT   long   80 Fseq[_dataTable] REG NA
                                                            /--*  t72    ref    
                                                            +--*  t73    long   
N136 (  5,  5) [000074] -----O-----                   t74 = *  ADD       byref  REG x0
                                                            /--*  t74    byref  
N138 (???,???) [000112] -----O-----                  t112 = *  PUTARG_REG byref  REG x0
N140 (  3, 12) [000113] H----------                  t113 =    CNS_INT(h) long   0x7ffac1def648 ftn REG x1
                                                            /--*  t113   long   
N142 (  6, 14) [000114] n---G------                  t114 = *  IND       long   REG x1
                                                            /--*  t112   byref  this in x0
                                                            +--*  t114   long   control expr
N144 ( 23, 11) [000037] --CXGO-----                   t37 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this REG x0
                                                            /--*  t37    long   
N146 ( 27, 14) [000041] DACXGO-----                         *  STORE_LCL_VAR long   V05 tmp2          NA REG NA
N148 (  3,  2) [000076] -----------                   t76 =    LCL_VAR   ref    V00 this          x0 REG x0
                                                            /--*  t76    ref    
N150 (  4,  3) [000077] ---X-O-----                         *  NULLCHECK byte   REG NA
N152 (  3,  2) [000078] -----------                   t78 =    LCL_VAR   ref    V00 this          x0 REG x0
N154 (  1,  2) [000079] -c---------                   t79 =    CNS_INT   long   80 Fseq[_dataTable] REG NA
                                                            /--*  t78    ref    
                                                            +--*  t79    long   
N156 (  5,  5) [000080] -----O-----                   t80 = *  ADD       byref  REG x0
                                                            /--*  t80    byref  
N158 (???,???) [000115] -----O-----                  t115 = *  PUTARG_REG byref  REG x0
N160 (  3, 12) [000116] H----------                  t116 =    CNS_INT(h) long   0x7ffac1def660 ftn REG x1
                                                            /--*  t116   long   
N162 (  6, 14) [000117] n---G------                  t117 = *  IND       long   REG x1
                                                            /--*  t115   byref  this in x0
                                                            +--*  t117   long   control expr
N164 ( 23, 11) [000040] --CXGO-----                   t40 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this REG x0
                                                            /--*  t40    long   
N166 ( 27, 14) [000046] DACXGO-----                         *  STORE_LCL_VAR long   V06 tmp3          NA REG NA
N168 (  3,  2) [000082] -----------                   t82 =    LCL_VAR   ref    V00 this          x0 REG x0
                                                            /--*  t82    ref    
N170 (  4,  3) [000083] ---X-O-----                         *  NULLCHECK byte   REG NA
N172 (  3,  2) [000084] -----------                   t84 =    LCL_VAR   ref    V00 this          x0 REG x0
N174 (  1,  2) [000085] -c---------                   t85 =    CNS_INT   long   80 Fseq[_dataTable] REG NA
                                                            /--*  t84    ref    
                                                            +--*  t85    long   
N176 (  5,  5) [000086] -----O-----                   t86 = *  ADD       byref  REG x0
                                                            /--*  t86    byref  
N178 (???,???) [000118] -----O-----                  t118 = *  PUTARG_REG byref  REG x0
N180 (  3, 12) [000119] H----------                  t119 =    CNS_INT(h) long   0x7ffac1def678 ftn REG x1
                                                            /--*  t119   long   
N182 (  6, 14) [000120] n---G------                  t120 = *  IND       long   REG x1
                                                            /--*  t118   byref  this in x0
                                                            +--*  t120   long   control expr
N184 ( 23, 11) [000045] --CXGO-----                   t45 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this REG x0
                                                            /--*  t45    long   
N186 ( 27, 14) [000089] DACXGO-----                         *  STORE_LCL_VAR long   V07 tmp4          NA REG NA
N188 (  3,  2) [000090] -----------                   t90 =    LCL_VAR   long   V07 tmp4          x3 REG x3
                                                            /--*  t90    long   
N190 (???,???) [000121] -----------                  t121 = *  PUTARG_REG long   REG x3
N192 (  3,  2) [000042] -----------                   t42 =    LCL_VAR   long   V05 tmp2          x1 REG x1
                                                            /--*  t42    long   
N194 (???,???) [000122] -----------                  t122 = *  PUTARG_REG long   REG x1
N196 (  3,  2) [000047] -----------                   t47 =    LCL_VAR   long   V06 tmp3          x2 REG x2
                                                            /--*  t47    long   
N198 (???,???) [000123] -----------                  t123 = *  PUTARG_REG long   REG x2
N200 (  3,  2) [000034] -----------                   t34 =    LCL_VAR   ref    V00 this          x0 REG x0
                                                            /--*  t34    ref    
N202 (???,???) [000124] -----------                  t124 = *  PUTARG_REG ref    REG x0
N204 (  3, 12) [000088] H----------                   t88 =    CNS_INT(h) ref     'RunBasicScenario_Load' REG x4
                                                            /--*  t88    ref    
N206 (???,???) [000125] -----------                  t125 = *  PUTARG_REG ref    REG x4
N208 (  3, 12) [000126] H----------                  t126 =    CNS_INT(h) long   0x7ffac1def8b8 ftn REG x5
                                                            /--*  t126   long   
N210 (  6, 14) [000127] n---G------                  t127 = *  IND       long   REG x5
                                                            /--*  t121   long   arg3 in x3
                                                            +--*  t122   long   arg1 in x1
                                                            +--*  t123   long   arg2 in x2
                                                            +--*  t124   ref    this in x0
                                                            +--*  t125   ref    arg4 in x4
                                                            +--*  t127   long   control expr
N212 ( 59, 42) [000049] -ACXGO-----                         *  CALL      void   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:ValidateResult(ulong,ulong,ulong,System.String):this REG NA
N214 (???,???) [000096] -----------                            IL_OFFSET void   INLRT @ 0x077[E-] REG NA
N216 (  0,  0) [000050] -----------                            RETURN    void   REG NA

-------------------------------------------------------------------------------------------------------------------

Final allocation
--------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
TreeID   Loc RP#  Name Type  Action    Reg  |x0  |x1  |x2  |x3  |x4  |x5  |x6  |x7  |x19 |x20 |d0  |d1  |d2  |d8  |d9  |d16 |p0  |p1  |p2  |
--------------------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
           0.#0   BB1 PredBB0               |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000051]   5.#1   C0   Def    Alloc    x0   |C0 a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000097]   6.#2   x0   Fixd   Keep     x0   |C0 a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
           6.#3   C0   Use *  Keep     x0   |C0 i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
           7.#4   x0   Fixd   Keep     x0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
           7.#5   I1   Def    Alloc    x0   |I1 a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000098]   9.#6   C2   Def    Alloc    x1   |I1 a|C2 a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000099]  10.#7   C2   Use *  Keep     x1   |I1 a|C2 i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          11.#8   I3   Def    Alloc    x1   |I1 a|I3 a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000001]  12.#9   x0   Fixd   Keep     x0   |I1 a|I3 a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          12.#10  I1   Use *  Keep     x0   |I1 i|I3 a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          12.#11  I3   Use *  Keep     x1   |    |I3 i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          13.#12       Kill   None     [x0-xip1 lr d0-d7 d16-d31 p0-p15]
                                            |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000003]  19.#13  I4   Def    Alloc    p0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I4 a|    |    |
[000004]  20.#14  I4   Use *  Keep     p0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I4 i|    |    |
          21.#15  I5   Def    Alloc    d16  |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I5 a|    |    |    |
[000005]  22.#16  I5   Use *  Keep     d16  |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I5 i|    |    |    |
[000052]  27.#17  I6   Def    Alloc    x0   |I6 a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000053]  28.#18  I6   Use *  Keep     x0   |I6 i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000054]  31.#19  I7   Def    Alloc    x0   |I7 a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000056]  34.#20  I7   Use *  Keep     x0   |I7 i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          35.#21  I8   Def    Alloc    x0   |I8 a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000100]  36.#22  x0   Fixd   Keep     x0   |I8 a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          36.#23  I8   Use *  Keep     x0   |I8 i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          37.#24  x0   Fixd   Keep     x0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          37.#25  I9   Def    Alloc    x0   |I9 a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000101]  39.#26  C10  Def    Alloc    x1   |I9 a|C10a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000102]  40.#27  C10  Use *  Keep     x1   |I9 a|C10i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          41.#28  I11  Def    Alloc    x1   |I9 a|I11a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000009]  42.#29  x0   Fixd   Keep     x0   |I9 a|I11a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          42.#30  I9   Use *  Keep     x0   |I9 i|I11a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          42.#31  I11  Use *  Keep     x1   |    |I11i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          43.#32       Kill   None     [x0-xip1 lr d0-d7 d16-d31 p0-p15]
                                            |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          43.#33  x0   Fixd   Keep     x0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          43.#34  I12  Def    Alloc    x0   |I12a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000006]  45.#35  I13  Def    Alloc    d16  |I12a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |I13a|    |    |    |
[000011]  47.#36  I14  Def    Alloc    p0   |I12a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |I13a|I14a|    |    |
[000012]  48.#37  I14  Use *  Keep     p0   |I12a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |I13a|I14i|    |    |
          48.#38  I13  Use *  Keep     d16  |I12a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |I13i|    |    |    |
          49.#39  I15  Def    Alloc    p0   |I12a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I15a|    |    |
[000010]  50.#40  I15  Use *  Keep     p0   |I12a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I15i|    |    |
          50.#41  I12  Use *  Keep     x0   |I12i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          51.#42  I16  Def    Alloc    d16  |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I16a|    |    |    |
[000017]  52.#43  I16  Use *  Keep     d16  |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I16i|    |    |    |
[000058]  55.#44  I17  Def    Alloc    x0   |I17a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000059]  56.#45  I17  Use *  Keep     x0   |I17i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000060]  59.#46  I18  Def    Alloc    x0   |I18a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000062]  62.#47  I18  Use *  Keep     x0   |I18i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          63.#48  I19  Def    Alloc    x0   |I19a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000103]  64.#49  x0   Fixd   Keep     x0   |I19a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          64.#50  I19  Use *  Keep     x0   |I19i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          65.#51  x0   Fixd   Keep     x0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          65.#52  I20  Def    Alloc    x0   |I20a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000104]  67.#53  C21  Def    Alloc    x1   |I20a|C21a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000105]  68.#54  C21  Use *  Keep     x1   |I20a|C21i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          69.#55  I22  Def    Alloc    x1   |I20a|I22a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000016]  70.#56  x0   Fixd   Keep     x0   |I20a|I22a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          70.#57  I20  Use *  Keep     x0   |I20i|I22a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          70.#58  I22  Use *  Keep     x1   |    |I22i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          71.#59       Kill   None     [x0-xip1 lr d0-d7 d16-d31 p0-p15]
                                            |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          71.#60  x0   Fixd   Keep     x0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          71.#61  I23  Def    Alloc    x0   |I23a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000013]  73.#62  I24  Def    Alloc    d16  |I23a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |I24a|    |    |    |
[000020]  75.#63  I25  Def    Alloc    p0   |I23a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |I24a|I25a|    |    |
[000021]  76.#64  I25  Use *  Keep     p0   |I23a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |I24a|I25i|    |    |
          76.#65  I24  Use *  Keep     d16  |I23a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |I24i|    |    |    |
          77.#66  I26  Def    Alloc    p0   |I23a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I26a|    |    |
[000019]  78.#67  I26  Use *  Keep     p0   |I23a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I26i|    |    |
          78.#68  I23  Use *  Keep     x0   |I23i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
          79.#69  I27  Def    Alloc    d16  |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I27a|    |    |    |
[000025]  81.#70  I28  Def    Alloc    p0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I27a|I28a|    |    |
[000026]  82.#71  I28  Use *  Keep     p0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I27a|I28i|    |    |
          82.#72  I27  Use *  Keep     d16  |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I27i|    |    |    |
          83.#73  I29  Def    Alloc    p0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I29a|    |    |
[000018]  85.#74  I30  Def    Alloc    d16  |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I30a|I29a|    |    |
[000023]  87.#75  I31  Def    Alloc    p1   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I30a|I29a|I31a|    |
[000024]  88.#76  I31  Use *  Keep     p1   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I30a|I29a|I31i|    |
          88.#77  I30  Use *  Keep     d16  |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I30i|I29a|    |    |
          89.#78  I32  Def    Alloc    p1   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I29a|I32a|    |
[000106]  91.#79  I33  Def    Alloc    p2   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I29a|I32a|I33a|
[000108]  96.#80  I33  Use *D Keep     p2   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I29a|I32a|I33i|
          96.#81  I29  Use *  Keep     p0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I29i|I32a|    |
          96.#82  I32  Use *D Keep     p1   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I32i|    |
          97.#83  I34  Def    Alloc    p0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I34a|    |    |
[000027]  98.#84  I34  Use *  Keep     p0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I34i|    |    |
          99.#85  I35  Def    Alloc    d16  |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I35a|    |    |    |
[000028] 100.#86  I35  Use *  Keep     d16  |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I35i|    |    |    |
[000064] 105.#87  I36  Def    Alloc    x0   |I36a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000065] 106.#88  I36  Use *  Keep     x0   |I36i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000066] 109.#89  I37  Def    Alloc    x0   |I37a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000068] 112.#90  I37  Use *  Keep     x0   |I37i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         113.#91  I38  Def    Alloc    x0   |I38a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000109] 114.#92  x0   Fixd   Keep     x0   |I38a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         114.#93  I38  Use *  Keep     x0   |I38i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         115.#94  x0   Fixd   Keep     x0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         115.#95  I39  Def    Alloc    x0   |I39a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000110] 117.#96  C40  Def    Alloc    x1   |I39a|C40a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000111] 118.#97  C40  Use *  Keep     x1   |I39a|C40i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         119.#98  I41  Def    Alloc    x1   |I39a|I41a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000031] 120.#99  x0   Fixd   Keep     x0   |I39a|I41a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         120.#100 I39  Use *  Keep     x0   |I39i|I41a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         120.#101 I41  Use *  Keep     x1   |    |I41i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         121.#102      Kill   None     [x0-xip1 lr d0-d7 d16-d31 p0-p15]
                                            |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         121.#103 x0   Fixd   Keep     x0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         121.#104 I42  Def    Alloc    x0   |I42a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000032] 123.#105 I43  Def    Alloc    d16  |I42a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |I43a|    |    |    |
[000033] 124.#106 I42  Use *  Keep     x0   |I42i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |I43a|    |    |    |
         124.#107 I43  Use *  Keep     d16  |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |I43i|    |    |    |
[000070] 129.#108 I44  Def    Alloc    x0   |I44a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000071] 130.#109 I44  Use *  Keep     x0   |I44i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000072] 133.#110 I45  Def    Alloc    x0   |I45a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000074] 136.#111 I45  Use *  Keep     x0   |I45i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         137.#112 I46  Def    Alloc    x0   |I46a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000112] 138.#113 x0   Fixd   Keep     x0   |I46a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         138.#114 I46  Use *  Keep     x0   |I46i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         139.#115 x0   Fixd   Keep     x0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         139.#116 I47  Def    Alloc    x0   |I47a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000113] 141.#117 C48  Def    Alloc    x1   |I47a|C48a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000114] 142.#118 C48  Use *  Keep     x1   |I47a|C48i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         143.#119 I49  Def    Alloc    x1   |I47a|I49a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000037] 144.#120 x0   Fixd   Keep     x0   |I47a|I49a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         144.#121 I47  Use *  Keep     x0   |I47i|I49a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         144.#122 I49  Use *  Keep     x1   |    |I49i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         145.#123      Kill   None     [x0-xip1 lr d0-d7 d16-d31 p0-p15]
                                            |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         145.#124 x0   Fixd   Keep     x0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         145.#125 I50  Def    Alloc    x0   |I50a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000041] 146.#126 I50  Use *  Keep     x0   |I50i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000076] 149.#127 I51  Def    Alloc    x0   |I51a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000077] 150.#128 I51  Use *  Keep     x0   |I51i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000078] 153.#129 I52  Def    Alloc    x0   |I52a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000080] 156.#130 I52  Use *  Keep     x0   |I52i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         157.#131 I53  Def    Alloc    x0   |I53a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000115] 158.#132 x0   Fixd   Keep     x0   |I53a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         158.#133 I53  Use *  Keep     x0   |I53i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         159.#134 x0   Fixd   Keep     x0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         159.#135 I54  Def    Alloc    x0   |I54a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000116] 161.#136 C55  Def    Alloc    x1   |I54a|C55a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000117] 162.#137 C55  Use *  Keep     x1   |I54a|C55i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         163.#138 I56  Def    Alloc    x1   |I54a|I56a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000040] 164.#139 x0   Fixd   Keep     x0   |I54a|I56a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         164.#140 I54  Use *  Keep     x0   |I54i|I56a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         164.#141 I56  Use *  Keep     x1   |    |I56i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         165.#142      Kill   None     [x0-xip1 lr d0-d7 d16-d31 p0-p15]
                                            |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         165.#143 x0   Fixd   Keep     x0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         165.#144 I57  Def    Alloc    x0   |I57a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000046] 166.#145 I57  Use *  Keep     x0   |I57i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000082] 169.#146 I58  Def    Alloc    x0   |I58a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000083] 170.#147 I58  Use *  Keep     x0   |I58i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000084] 173.#148 I59  Def    Alloc    x0   |I59a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000086] 176.#149 I59  Use *  Keep     x0   |I59i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         177.#150 I60  Def    Alloc    x0   |I60a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000118] 178.#151 x0   Fixd   Keep     x0   |I60a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         178.#152 I60  Use *  Keep     x0   |I60i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         179.#153 x0   Fixd   Keep     x0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         179.#154 I61  Def    Alloc    x0   |I61a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000119] 181.#155 C62  Def    Alloc    x1   |I61a|C62a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000120] 182.#156 C62  Use *  Keep     x1   |I61a|C62i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         183.#157 I63  Def    Alloc    x1   |I61a|I63a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000045] 184.#158 x0   Fixd   Keep     x0   |I61a|I63a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         184.#159 I61  Use *  Keep     x0   |I61i|I63a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         184.#160 I63  Use *  Keep     x1   |    |I63i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         185.#161      Kill   None     [x0-xip1 lr d0-d7 d16-d31 p0-p15]
                                            |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         185.#162 x0   Fixd   Keep     x0   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         185.#163 I64  Def    Alloc    x0   |I64a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000089] 186.#164 I64  Use *  Keep     x0   |I64i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000090] 189.#165 I65  Def    Alloc    x3   |    |    |    |I65a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000121] 190.#166 x3   Fixd   Keep     x3   |    |    |    |I65a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         190.#167 I65  Use *  Keep     x3   |    |    |    |I65i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         191.#168 x3   Fixd   Keep     x3   |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         191.#169 I66  Def    Alloc    x3   |    |    |    |I66a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000042] 193.#170 I67  Def    Alloc    x1   |    |I67a|    |I66a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000122] 194.#171 x1   Fixd   Keep     x1   |    |I67a|    |I66a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         194.#172 I67  Use *  Keep     x1   |    |I67i|    |I66a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         195.#173 x1   Fixd   Keep     x1   |    |    |    |I66a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         195.#174 I68  Def    Alloc    x1   |    |I68a|    |I66a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000047] 197.#175 I69  Def    Alloc    x2   |    |I68a|I69a|I66a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000123] 198.#176 x2   Fixd   Keep     x2   |    |I68a|I69a|I66a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         198.#177 I69  Use *  Keep     x2   |    |I68a|I69i|I66a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         199.#178 x2   Fixd   Keep     x2   |    |I68a|    |I66a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         199.#179 I70  Def    Alloc    x2   |    |I68a|I70a|I66a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000034] 201.#180 I71  Def    Alloc    x0   |I71a|I68a|I70a|I66a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000124] 202.#181 x0   Fixd   Keep     x0   |I71a|I68a|I70a|I66a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         202.#182 I71  Use *  Keep     x0   |I71i|I68a|I70a|I66a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         203.#183 x0   Fixd   Keep     x0   |    |I68a|I70a|I66a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         203.#184 I72  Def    Alloc    x0   |I72a|I68a|I70a|I66a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000088] 205.#185 C73  Def    Alloc    x4   |I72a|I68a|I70a|I66a|C73a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000125] 206.#186 x4   Fixd   Keep     x4   |I72a|I68a|I70a|I66a|C73a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         206.#187 C73  Use *  Keep     x4   |I72a|I68a|I70a|I66a|C73i|    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         207.#188 x4   Fixd   Keep     x4   |I72a|I68a|I70a|I66a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |
         207.#189 I74  Def    Alloc    x4   |I72a|I68a|I70a|I66a|I74a|    |    |    |    |    |    |    |    |    |    |    |    |    |    |
[000126] 209.#190 C75  Def    Alloc    x5   |I72a|I68a|I70a|I66a|I74a|C75a|    |    |    |    |    |    |    |    |    |    |    |    |    |
[000127] 210.#191 C75  Use *  Keep     x5   |I72a|I68a|I70a|I66a|I74a|C75i|    |    |    |    |    |    |    |    |    |    |    |    |    |
         211.#192 I76  Def    Alloc    x5   |I72a|I68a|I70a|I66a|I74a|I76a|    |    |    |    |    |    |    |    |    |    |    |    |    |
[000049] 212.#193 x3   Fixd   Keep     x3   |I72a|I68a|I70a|I66a|I74a|I76a|    |    |    |    |    |    |    |    |    |    |    |    |    |
         212.#194 I66  Use *  Keep     x3   |I72a|I68a|I70a|I66i|I74a|I76a|    |    |    |    |    |    |    |    |    |    |    |    |    |
         212.#195 x1   Fixd   Keep     x1   |I72a|I68a|I70a|    |I74a|I76a|    |    |    |    |    |    |    |    |    |    |    |    |    |
         212.#196 I68  Use *  Keep     x1   |I72a|I68i|I70a|    |I74a|I76a|    |    |    |    |    |    |    |    |    |    |    |    |    |
         212.#197 x2   Fixd   Keep     x2   |I72a|    |I70a|    |I74a|I76a|    |    |    |    |    |    |    |    |    |    |    |    |    |
         212.#198 I70  Use *  Keep     x2   |I72a|    |I70i|    |I74a|I76a|    |    |    |    |    |    |    |    |    |    |    |    |    |
         212.#199 x0   Fixd   Keep     x0   |I72a|    |    |    |I74a|I76a|    |    |    |    |    |    |    |    |    |    |    |    |    |
         212.#200 I72  Use *  Keep     x0   |I72i|    |    |    |I74a|I76a|    |    |    |    |    |    |    |    |    |    |    |    |    |
         212.#201 x4   Fixd   Keep     x4   |    |    |    |    |I74a|I76a|    |    |    |    |    |    |    |    |    |    |    |    |    |
         212.#202 I74  Use *  Keep     x4   |    |    |    |    |I74i|I76a|    |    |    |    |    |    |    |    |    |    |    |    |    |
         212.#203 I76  Use *  Keep     x5   |    |    |    |    |    |I76i|    |    |    |    |    |    |    |    |    |    |    |    |    |
         213.#204      Kill   None     [x0-xip1 lr d0-d7 d16-d31 p0-p15]
                                            |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |    |

Recording the maximum number of concurrent spills:

----------
LSRA Stats
----------
Register selection order: ABCDEFGHIJKLMNOPQ
Total Tracked Vars:  0
Total Reg Cand Vars: 0
Total number of Intervals: 76
Total number of RefPositions: 204
Total Number of spill temps created: 0
..........
BB01 [  100.00]: REG_ORDER = 47
..........
Total SpillCount : 0   Weighted: 0.000000
Total CopyReg : 0   Weighted: 0.000000
Total ResolutionMovs : 0   Weighted: 0.000000
Total SplitEdges : 0   Weighted: 0.000000
..........
Total REG_ORDER [#13] : 47   Weighted: 4700.000000

TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS
Incoming Parameters: 
BB01 [0000] [000..078) (return), preds={} succs={}
=====
  N002.                    IL_OFFSET INLRT @ 0x000[E-]
  N004. x0              =  CNS_INT(h)  'RunBasicScenario_Load'
  N006. x0              =  PUTARG_REG; x0
  N008. x1              =  CNS_INT(h) 0x7ffac2114528 ftn
  N010. x1              =  IND      ; x1
  N012.                    CALL     ; x0,x1
  N014.                    IL_OFFSET INLRT @ 0x00A[E-]
  N016.                    CNS_INT   31
  N018. p0              =  HWINTRINSIC
  N020. d16             =  HWINTRINSIC; p0
  N022.                    V01 MEM; d16
  N024.                    IL_OFFSET INLRT @ 0x012[E-]
  N026. x0              =  V00 MEM
  N028.                    NULLCHECK; x0
  N030. x0              =  V00 MEM
  N032.                    CNS_INT   80 Fseq[_dataTable]
  N034. x0              =  ADD      ; x0
  N036. x0              =  PUTARG_REG; x0
  N038. x1              =  CNS_INT(h) 0x7ffac1def648 ftn
  N040. x1              =  IND      ; x1
  N042. x0              =  CALL     ; x0,x1
  N044. d16             =  V01 MEM
  N046. p0              =  HWINTRINSIC
  N048. p0              =  HWINTRINSIC; p0,d16
  N050. d16             =  HWINTRINSIC; p0,x0
  N052.                    V04 MEM; d16
  N054. x0              =  V00 MEM
  N056.                    NULLCHECK; x0
  N058. x0              =  V00 MEM
  N060.                    CNS_INT   80 Fseq[_dataTable]
  N062. x0              =  ADD      ; x0
  N064. x0              =  PUTARG_REG; x0
  N066. x1              =  CNS_INT(h) 0x7ffac1def660 ftn
  N068. x1              =  IND      ; x1
  N070. x0              =  CALL     ; x0,x1
  N072. d16             =  V01 MEM
  N074. p0              =  HWINTRINSIC
  N076. p0              =  HWINTRINSIC; p0,d16
  N078. d16             =  HWINTRINSIC; p0,x0
  N080. p0              =  HWINTRINSIC
  N082. p0              =  HWINTRINSIC; p0,d16
  N084. d16             =  V04 MEM
  N086. p1              =  HWINTRINSIC
  N088. p1              =  HWINTRINSIC; p1,d16
  N090. p2              =  HWINTRINSIC
  N092.                    CNS_VEC  <0x00000000, 0x00000000, 0x00000000, 0x00000000>
  N094. STK             =  HWINTRINSIC; p1,p0
  N096. p0              =  HWINTRINSIC; p2,STK
  N098. d16             =  HWINTRINSIC; p0
  N100.                    V02 MEM; d16
  N102.                    IL_OFFSET INLRT @ 0x03A[E-]
  N104. x0              =  V00 MEM
  N106.                    NULLCHECK; x0
  N108. x0              =  V00 MEM
  N110.                    CNS_INT   80 Fseq[_dataTable]
  N112. x0              =  ADD      ; x0
  N114. x0              =  PUTARG_REG; x0
  N116. x1              =  CNS_INT(h) 0x7ffac1def678 ftn
  N118. x1              =  IND      ; x1
  N120. x0              =  CALL     ; x0,x1
  N122. d16             =  V02 MEM
  N124.                    STOREIND ; x0,d16
  N126.                    IL_OFFSET INLRT @ 0x04B[E-]
  N128. x0              =  V00 MEM
  N130.                    NULLCHECK; x0
  N132. x0              =  V00 MEM
  N134.                    CNS_INT   80 Fseq[_dataTable]
  N136. x0              =  ADD      ; x0
  N138. x0              =  PUTARG_REG; x0
  N140. x1              =  CNS_INT(h) 0x7ffac1def648 ftn
  N142. x1              =  IND      ; x1
  N144. x0              =  CALL     ; x0,x1
  N146.                    V05 MEM; x0
  N148. x0              =  V00 MEM
  N150.                    NULLCHECK; x0
  N152. x0              =  V00 MEM
  N154.                    CNS_INT   80 Fseq[_dataTable]
  N156. x0              =  ADD      ; x0
  N158. x0              =  PUTARG_REG; x0
  N160. x1              =  CNS_INT(h) 0x7ffac1def660 ftn
  N162. x1              =  IND      ; x1
  N164. x0              =  CALL     ; x0,x1
  N166.                    V06 MEM; x0
  N168. x0              =  V00 MEM
  N170.                    NULLCHECK; x0
  N172. x0              =  V00 MEM
  N174.                    CNS_INT   80 Fseq[_dataTable]
  N176. x0              =  ADD      ; x0
  N178. x0              =  PUTARG_REG; x0
  N180. x1              =  CNS_INT(h) 0x7ffac1def678 ftn
  N182. x1              =  IND      ; x1
  N184. x0              =  CALL     ; x0,x1
  N186.                    V07 MEM; x0
  N188. x3              =  V07 MEM
  N190. x3              =  PUTARG_REG; x3
  N192. x1              =  V05 MEM
  N194. x1              =  PUTARG_REG; x1
  N196. x2              =  V06 MEM
  N198. x2              =  PUTARG_REG; x2
  N200. x0              =  V00 MEM
  N202. x0              =  PUTARG_REG; x0
  N204. x4              =  CNS_INT(h)  'RunBasicScenario_Load'
  N206. x4              =  PUTARG_REG; x4
  N208. x5              =  CNS_INT(h) 0x7ffac1def8b8 ftn
  N210. x5              =  IND      ; x5
  N212.                    CALL     ; x3,x1,x2,x0,x4,x5
  N214.                    IL_OFFSET INLRT @ 0x077[E-]
  N216.                    RETURN   




*************** Finishing PHASE Linear scan register alloc
Trees after Linear scan register alloc

---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   [IL range]   [jump]                            [EH region]        [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    [000..078)                           (return)                     i LIR hascall gcsafe nullcheck
---------------------------------------------------------------------------------------------------------------------------------------------------------------------

------------ BB01 [0000] [000..078) (return), preds={} succs={}
N002 (???,???) [000091] -----------                            IL_OFFSET void   INLRT @ 0x000[E-] REG NA
N004 (  3, 12) [000051] H----------                   t51 =    CNS_INT(h) ref     'RunBasicScenario_Load' REG x0
                                                            /--*  t51    ref    
N006 (???,???) [000097] -----------                   t97 = *  PUTARG_REG ref    REG x0
N008 (  3, 12) [000098] H----------                   t98 =    CNS_INT(h) long   0x7ffac2114528 ftn REG x1
                                                            /--*  t98    long   
N010 (  6, 14) [000099] n---G------                   t99 = *  IND       long   REG x1
                                                            /--*  t97    ref    arg0 in x0
                                                            +--*  t99    long   control expr
N012 ( 17, 15) [000001] --CXG------                         *  CALL      void   TestLibrary.TestFramework:BeginScenario(System.String) REG NA
N014 (???,???) [000092] -----------                            IL_OFFSET void   INLRT @ 0x00A[E-] REG NA
N016 (  1,  2) [000002] -c-----N---                    t2 =    CNS_INT   int    31 REG NA
                                                            /--*  t2     int    
N018 (  2,  3) [000003] -----------                    t3 = *  HWINTRINSIC mask   int CreateTrueMaskInt32 REG p0
                                                            /--*  t3     mask   
N020 (  3,  4) [000004] -----------                    t4 = *  HWINTRINSIC simd16 int ConvertMaskToVector REG d16
                                                            /--*  t4     simd16 
N022 (  7,  7) [000005] DA---------                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V01 loc0          NA REG NA
N024 (???,???) [000093] -----------                            IL_OFFSET void   INLRT @ 0x012[E-] REG NA
N026 (  3,  2) [000052] -----------                   t52 =    LCL_VAR   ref    V00 this          x0 REG x0
                                                            /--*  t52    ref    
N028 (  4,  3) [000053] ---X-O-----                         *  NULLCHECK byte   REG NA
N030 (  3,  2) [000054] -----------                   t54 =    LCL_VAR   ref    V00 this          x0 REG x0
N032 (  1,  2) [000055] -c---------                   t55 =    CNS_INT   long   80 Fseq[_dataTable] REG NA
                                                            /--*  t54    ref    
                                                            +--*  t55    long   
N034 (  5,  5) [000056] -----O-----                   t56 = *  ADD       byref  REG x0
                                                            /--*  t56    byref  
N036 (???,???) [000100] -----O-----                  t100 = *  PUTARG_REG byref  REG x0
N038 (  3, 12) [000101] H----------                  t101 =    CNS_INT(h) long   0x7ffac1def648 ftn REG x1
                                                            /--*  t101   long   
N040 (  6, 14) [000102] n---G------                  t102 = *  IND       long   REG x1
                                                            /--*  t100   byref  this in x0
                                                            +--*  t102   long   control expr
N042 ( 23, 11) [000009] --CXGO-----                    t9 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this REG x0
N044 (  3,  2) [000006] -----------                    t6 =    LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0          d16 REG d16
N046 (  1,  1) [000011] -----------                   t11 =    HWINTRINSIC mask   int CreateTrueMaskAll REG p0
                                                            /--*  t11    mask   
                                                            +--*  t6     simd16 
N048 (  5,  4) [000012] -----------                   t12 = *  HWINTRINSIC mask   int ConvertVectorToMask REG p0
                                                            /--*  t12    mask   
                                                            +--*  t9     long   
N050 ( 29, 16) [000010] --CXGO-----                   t10 = *  HWINTRINSIC simd16 int LoadVector REG d16
                                                            /--*  t10    simd16 
N052 ( 33, 19) [000017] DACXGO-----                         *  STORE_LCL_VAR simd16 V04 tmp1          NA REG NA
N054 (  3,  2) [000058] -----------                   t58 =    LCL_VAR   ref    V00 this          x0 REG x0
                                                            /--*  t58    ref    
N056 (  4,  3) [000059] ---X-O-----                         *  NULLCHECK byte   REG NA
N058 (  3,  2) [000060] -----------                   t60 =    LCL_VAR   ref    V00 this          x0 REG x0
N060 (  1,  2) [000061] -c---------                   t61 =    CNS_INT   long   80 Fseq[_dataTable] REG NA
                                                            /--*  t60    ref    
                                                            +--*  t61    long   
N062 (  5,  5) [000062] -----O-----                   t62 = *  ADD       byref  REG x0
                                                            /--*  t62    byref  
N064 (???,???) [000103] -----O-----                  t103 = *  PUTARG_REG byref  REG x0
N066 (  3, 12) [000104] H----------                  t104 =    CNS_INT(h) long   0x7ffac1def660 ftn REG x1
                                                            /--*  t104   long   
N068 (  6, 14) [000105] n---G------                  t105 = *  IND       long   REG x1
                                                            /--*  t103   byref  this in x0
                                                            +--*  t105   long   control expr
N070 ( 23, 11) [000016] --CXGO-----                   t16 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this REG x0
N072 (  3,  2) [000013] -----------                   t13 =    LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0          d16 REG d16
N074 (  1,  1) [000020] -----------                   t20 =    HWINTRINSIC mask   int CreateTrueMaskAll REG p0
                                                            /--*  t20    mask   
                                                            +--*  t13    simd16 
N076 (  5,  4) [000021] -----------                   t21 = *  HWINTRINSIC mask   int ConvertVectorToMask REG p0
                                                            /--*  t21    mask   
                                                            +--*  t16    long   
N078 ( 29, 16) [000019] --CXGO-----                   t19 = *  HWINTRINSIC simd16 int LoadVector REG d16
N080 (  1,  1) [000025] -----------                   t25 =    HWINTRINSIC mask   int CreateTrueMaskAll REG p0
                                                            /--*  t25    mask   
                                                            +--*  t19    simd16 
N082 ( 31, 18) [000026] --CXGO-----                   t26 = *  HWINTRINSIC mask   int ConvertVectorToMask REG p0
N084 (  3,  2) [000018] -----------                   t18 =    LCL_VAR   simd16 V04 tmp1          d16 REG d16
N086 (  1,  1) [000023] -----------                   t23 =    HWINTRINSIC mask   int CreateTrueMaskAll REG p1
                                                            /--*  t23    mask   
                                                            +--*  t18    simd16 
N088 (  5,  4) [000024] -----------                   t24 = *  HWINTRINSIC mask   int ConvertVectorToMask REG p1
N090 (???,???) [000106] -----------                  t106 =    HWINTRINSIC mask   int CreateTrueMaskAll REG p2
N092 (???,???) [000107] -c---------                  t107 =    CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000> REG NA
                                                            /--*  t24    mask   
                                                            +--*  t26    mask   
N094 ( 37, 23) [000022] -cCXGO-----                   t22 = *  HWINTRINSIC mask   int CreateBreakPropagateMask REG NA
                                                            /--*  t106   mask   
                                                            +--*  t22    mask   
                                                            +--*  t107   simd16 
N096 (???,???) [000108] --CXGO-----                  t108 = *  HWINTRINSIC mask   int ConditionalSelect REG p0
                                                            /--*  t108   mask   
N098 ( 38, 24) [000027] --CXGO-----                   t27 = *  HWINTRINSIC simd16 int ConvertMaskToVector REG d16
                                                            /--*  t27    simd16 
N100 ( 42, 27) [000028] DACXGO-----                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V02 loc1          NA REG NA
N102 (???,???) [000094] -----------                            IL_OFFSET void   INLRT @ 0x03A[E-] REG NA
N104 (  3,  2) [000064] -----------                   t64 =    LCL_VAR   ref    V00 this          x0 REG x0
                                                            /--*  t64    ref    
N106 (  4,  3) [000065] ---X-O-----                         *  NULLCHECK byte   REG NA
N108 (  3,  2) [000066] -----------                   t66 =    LCL_VAR   ref    V00 this          x0 REG x0
N110 (  1,  2) [000067] -c---------                   t67 =    CNS_INT   long   80 Fseq[_dataTable] REG NA
                                                            /--*  t66    ref    
                                                            +--*  t67    long   
N112 (  5,  5) [000068] -----O-----                   t68 = *  ADD       byref  REG x0
                                                            /--*  t68    byref  
N114 (???,???) [000109] -----O-----                  t109 = *  PUTARG_REG byref  REG x0
N116 (  3, 12) [000110] H----------                  t110 =    CNS_INT(h) long   0x7ffac1def678 ftn REG x1
                                                            /--*  t110   long   
N118 (  6, 14) [000111] n---G------                  t111 = *  IND       long   REG x1
                                                            /--*  t109   byref  this in x0
                                                            +--*  t111   long   control expr
N120 ( 23, 11) [000031] --CXGO-----                   t31 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this REG x0
N122 (  3,  2) [000032] -----------                   t32 =    LCL_VAR   simd16<System.Numerics.Vector`1> V02 loc1          d16 REG d16
                                                            /--*  t31    long   
                                                            +--*  t32    simd16 
N124 ( 30, 16) [000033] -ACXGO-----                         *  STOREIND  simd16 (copy) REG NA
N126 (???,???) [000095] -----------                            IL_OFFSET void   INLRT @ 0x04B[E-] REG NA
N128 (  3,  2) [000070] -----------                   t70 =    LCL_VAR   ref    V00 this          x0 REG x0
                                                            /--*  t70    ref    
N130 (  4,  3) [000071] ---X-O-----                         *  NULLCHECK byte   REG NA
N132 (  3,  2) [000072] -----------                   t72 =    LCL_VAR   ref    V00 this          x0 REG x0
N134 (  1,  2) [000073] -c---------                   t73 =    CNS_INT   long   80 Fseq[_dataTable] REG NA
                                                            /--*  t72    ref    
                                                            +--*  t73    long   
N136 (  5,  5) [000074] -----O-----                   t74 = *  ADD       byref  REG x0
                                                            /--*  t74    byref  
N138 (???,???) [000112] -----O-----                  t112 = *  PUTARG_REG byref  REG x0
N140 (  3, 12) [000113] H----------                  t113 =    CNS_INT(h) long   0x7ffac1def648 ftn REG x1
                                                            /--*  t113   long   
N142 (  6, 14) [000114] n---G------                  t114 = *  IND       long   REG x1
                                                            /--*  t112   byref  this in x0
                                                            +--*  t114   long   control expr
N144 ( 23, 11) [000037] --CXGO-----                   t37 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this REG x0
                                                            /--*  t37    long   
N146 ( 27, 14) [000041] DACXGO-----                         *  STORE_LCL_VAR long   V05 tmp2          NA REG NA
N148 (  3,  2) [000076] -----------                   t76 =    LCL_VAR   ref    V00 this          x0 REG x0
                                                            /--*  t76    ref    
N150 (  4,  3) [000077] ---X-O-----                         *  NULLCHECK byte   REG NA
N152 (  3,  2) [000078] -----------                   t78 =    LCL_VAR   ref    V00 this          x0 REG x0
N154 (  1,  2) [000079] -c---------                   t79 =    CNS_INT   long   80 Fseq[_dataTable] REG NA
                                                            /--*  t78    ref    
                                                            +--*  t79    long   
N156 (  5,  5) [000080] -----O-----                   t80 = *  ADD       byref  REG x0
                                                            /--*  t80    byref  
N158 (???,???) [000115] -----O-----                  t115 = *  PUTARG_REG byref  REG x0
N160 (  3, 12) [000116] H----------                  t116 =    CNS_INT(h) long   0x7ffac1def660 ftn REG x1
                                                            /--*  t116   long   
N162 (  6, 14) [000117] n---G------                  t117 = *  IND       long   REG x1
                                                            /--*  t115   byref  this in x0
                                                            +--*  t117   long   control expr
N164 ( 23, 11) [000040] --CXGO-----                   t40 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this REG x0
                                                            /--*  t40    long   
N166 ( 27, 14) [000046] DACXGO-----                         *  STORE_LCL_VAR long   V06 tmp3          NA REG NA
N168 (  3,  2) [000082] -----------                   t82 =    LCL_VAR   ref    V00 this          x0 REG x0
                                                            /--*  t82    ref    
N170 (  4,  3) [000083] ---X-O-----                         *  NULLCHECK byte   REG NA
N172 (  3,  2) [000084] -----------                   t84 =    LCL_VAR   ref    V00 this          x0 REG x0
N174 (  1,  2) [000085] -c---------                   t85 =    CNS_INT   long   80 Fseq[_dataTable] REG NA
                                                            /--*  t84    ref    
                                                            +--*  t85    long   
N176 (  5,  5) [000086] -----O-----                   t86 = *  ADD       byref  REG x0
                                                            /--*  t86    byref  
N178 (???,???) [000118] -----O-----                  t118 = *  PUTARG_REG byref  REG x0
N180 (  3, 12) [000119] H----------                  t119 =    CNS_INT(h) long   0x7ffac1def678 ftn REG x1
                                                            /--*  t119   long   
N182 (  6, 14) [000120] n---G------                  t120 = *  IND       long   REG x1
                                                            /--*  t118   byref  this in x0
                                                            +--*  t120   long   control expr
N184 ( 23, 11) [000045] --CXGO-----                   t45 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this REG x0
                                                            /--*  t45    long   
N186 ( 27, 14) [000089] DACXGO-----                         *  STORE_LCL_VAR long   V07 tmp4          NA REG NA
N188 (  3,  2) [000090] -----------                   t90 =    LCL_VAR   long   V07 tmp4          x3 REG x3
                                                            /--*  t90    long   
N190 (???,???) [000121] -----------                  t121 = *  PUTARG_REG long   REG x3
N192 (  3,  2) [000042] -----------                   t42 =    LCL_VAR   long   V05 tmp2          x1 REG x1
                                                            /--*  t42    long   
N194 (???,???) [000122] -----------                  t122 = *  PUTARG_REG long   REG x1
N196 (  3,  2) [000047] -----------                   t47 =    LCL_VAR   long   V06 tmp3          x2 REG x2
                                                            /--*  t47    long   
N198 (???,???) [000123] -----------                  t123 = *  PUTARG_REG long   REG x2
N200 (  3,  2) [000034] -----------                   t34 =    LCL_VAR   ref    V00 this          x0 REG x0
                                                            /--*  t34    ref    
N202 (???,???) [000124] -----------                  t124 = *  PUTARG_REG ref    REG x0
N204 (  3, 12) [000088] H----------                   t88 =    CNS_INT(h) ref     'RunBasicScenario_Load' REG x4
                                                            /--*  t88    ref    
N206 (???,???) [000125] -----------                  t125 = *  PUTARG_REG ref    REG x4
N208 (  3, 12) [000126] H----------                  t126 =    CNS_INT(h) long   0x7ffac1def8b8 ftn REG x5
                                                            /--*  t126   long   
N210 (  6, 14) [000127] n---G------                  t127 = *  IND       long   REG x5
                                                            /--*  t121   long   arg3 in x3
                                                            +--*  t122   long   arg1 in x1
                                                            +--*  t123   long   arg2 in x2
                                                            +--*  t124   ref    this in x0
                                                            +--*  t125   ref    arg4 in x4
                                                            +--*  t127   long   control expr
N212 ( 59, 42) [000049] -ACXGO-----                         *  CALL      void   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:ValidateResult(ulong,ulong,ulong,System.String):this REG NA
N214 (???,???) [000096] -----------                            IL_OFFSET void   INLRT @ 0x077[E-] REG NA
N216 (  0,  0) [000050] -----------                            RETURN    void   REG NA

-------------------------------------------------------------------------------------------------------------------
*************** In fgDebugCheckBBlist
[deferred prior check failed -- skipping this check]

*************** Starting PHASE Place 'align' instructions
*************** In placeLoopAlignInstructions()
Not aligning loops; ShouldAlignLoops is false

*************** Finishing PHASE Place 'align' instructions [no changes]
*************** In genGenerateCode()

---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   [IL range]   [jump]                            [EH region]        [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    [000..078)                           (return)                     i LIR hascall gcsafe nullcheck
---------------------------------------------------------------------------------------------------------------------------------------------------------------------

*************** Starting PHASE Generate code
*************** In fgDebugCheckBBlist
Finalizing stack frame
must init V01 because compInitMem is set and it is not a temp
must init V02 because compInitMem is set and it is not a temp
Modified regs: [x0-xip1 lr d0-d7 d16-d31 p0-p15]
Callee-saved registers pushed: 2 [fp lr]
*************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT)
Setting genSaveFpLrWithAllCalleeSavedRegisters to false
Assign V00 this, size=8, stkOffs=-0x8
Pad V01 loc0, size=16, stkOffs=-0x10, pad=8
Assign V01 loc0, size=16, stkOffs=-0x20
Pad V02 loc1, size=16, stkOffs=-0x20, pad=0
Assign V02 loc1, size=16, stkOffs=-0x30
Pad V04 tmp1, size=16, stkOffs=-0x30, pad=0
Assign V04 tmp1, size=16, stkOffs=-0x40
Assign V05 tmp2, size=8, stkOffs=-0x48
Assign V06 tmp3, size=8, stkOffs=-0x50
Assign V07 tmp4, size=8, stkOffs=-0x58
--- delta bump 112 for FP frame
--- virtual stack offset to actual stack offset delta is 112
-- V00 was -8, now 104
-- V01 was -32, now 80
-- V02 was -48, now 64
-- V03 was 0, now 112
-- V04 was -64, now 48
-- V05 was -72, now 40
-- V06 was -80, now 32
-- V07 was -88, now 24
; Final local variable assignments
;
;  V00 this         [V00    ] (  1,  1   )     ref  ->  [fp+0x68]  do-not-enreg[] this class-hnd <JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int>
;  V01 loc0         [V01    ] (  1,  1   )  simd16  ->  [fp+0x50]  HFA(simd16)  do-not-enreg[S] must-init <System.Numerics.Vector`1[int]>
;  V02 loc1         [V02    ] (  1,  1   )  simd16  ->  [fp+0x40]  HFA(simd16)  do-not-enreg[S] must-init <System.Numerics.Vector`1[int]>
;# V03 OutArgs      [V03    ] (  1,  1   )  struct ( 0) [sp+0x00]  do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;  V04 tmp1         [V04    ] (  1,  1   )  simd16  ->  [fp+0x30]  do-not-enreg[S] "non-inline candidate call"
;  V05 tmp2         [V05    ] (  1,  1   )    long  ->  [fp+0x28]  do-not-enreg[] "non-inline candidate call"
;  V06 tmp3         [V06    ] (  1,  1   )    long  ->  [fp+0x20]  do-not-enreg[] "non-inline candidate call"
;  V07 tmp4         [V07    ] (  1,  1   )    long  ->  [fp+0x18]  do-not-enreg[] "argument with side effect"
;
; Lcl frame size = 96
Created:
      G_M27522_IG02:        ; offs=0x000000, size=0x0000, bbWeight=1, gcrefRegs=0000 {}
Mark labels for codegen
  BB01 : first block
*************** After genMarkLabelsForCodegen()

---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BBnum BBid ref try hnd preds           weight   [IL range]   [jump]                            [EH region]        [flags]
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
BB01 [0000]  1                             1    [000..078)                           (return)                     i LIR label hascall gcsafe nullcheck
---------------------------------------------------------------------------------------------------------------------------------------------------------------------
Setting stack level from -572662307 to 0

=============== Generating BB01 [0000] [000..078) (return), preds={} succs={} flags=0x00000000.10088811: i LIR label hascall gcsafe nullcheck
BB01 IN (0)={}
     OUT(0)={}

Liveness not changing: 0000000000000000 {}
							Live regs: (unchanged) 0000000000000000 {}
							GC regs: (unchanged) 0000 {}
							Byref regs: (unchanged) 0000 {}

      L_M27522_BB01:
Label: G_M27522_IG02, GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}

Scope info: begin block BB01, IL range [000..078)
Scope info: opening scope, LVnum=0 [000..078)
Debug: New V00 debug range: first
Scope info: opening scope, LVnum=1 [000..078)
Debug: New V01 debug range: first
Scope info: opening scope, LVnum=2 [000..078)
Debug: New V02 debug range: first
Added IP mapping: 0x0000 STACK_EMPTY (G_M27522_IG02,ins#0,ofs#0) label
Generating: N002 (???,???) [000091] -----------                            IL_OFFSET void   INLRT @ 0x000[E-] REG NA
Generating: N004 (  3, 12) [000051] H----------                   t51 =    CNS_INT(h) ref     'RunBasicScenario_Load' REG x0
Mapped BB01 to G_M27522_IG02
IN0001:             movz    x0, #0x58C8
IN0002:             movk    x0, #0xEB17 LSL #16
IN0003:             movk    x0, #574 LSL #32
							GC regs: 0000 {} => 0001 {x0}
                                                                        /--*  t51    ref    
Generating: N006 (???,???) [000097] -----------                   t97 = *  PUTARG_REG ref    REG x0
							GC regs: 0001 {x0} => 0000 {}
							GC regs: 0000 {} => 0001 {x0}
Generating: N008 (  3, 12) [000098] H----------                   t98 =    CNS_INT(h) long   0x7ffac2114528 ftn REG x1
IN0004:             movz    x1, #0x4528      // code for TestLibrary.TestFramework:BeginScenario(System.String)
IN0005:             movk    x1, #0xC211 LSL #16
IN0006:             movk    x1, #0x7FFA LSL #32
                                                                        /--*  t98    long   
Generating: N010 (  6, 14) [000099] n---G------                   t99 = *  IND       long   REG x1
IN0007:             ldr     x1, [x1]
                                                                        /--*  t97    ref    arg0 in x0
                                                                        +--*  t99    long   control expr
Generating: N012 ( 17, 15) [000001] --CXG------                         *  CALL      void   TestLibrary.TestFramework:BeginScenario(System.String) REG NA
							GC regs: 0001 {x0} => 0000 {}
Call: GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
IN0008:             blr     x1
Added IP mapping: 0x000A STACK_EMPTY (G_M27522_IG02,ins#8,ofs#32)
Generating: N014 (???,???) [000092] -----------                            IL_OFFSET void   INLRT @ 0x00A[E-] REG NA
Generating: N016 (  1,  2) [000002] -c-----N---                    t2 =    CNS_INT   int    31 REG NA
                                                                        /--*  t2     int    
Generating: N018 (  2,  3) [000003] -----------                    t3 = *  HWINTRINSIC mask   int CreateTrueMaskInt32 REG p0
IN0009:             ptrue   p0.s
                                                                        /--*  t3     mask   
Generating: N020 (  3,  4) [000004] -----------                    t4 = *  HWINTRINSIC simd16 int ConvertMaskToVector REG d16
IN000a:             mov     z16.s, p0/z, #1
                                                                        /--*  t4     simd16 
Generating: N022 (  7,  7) [000005] DA---------                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V01 loc0          NA REG NA
IN000b:             str     q16, [fp, #0x50]	// [V01 loc0]
Added IP mapping: 0x0012 STACK_EMPTY (G_M27522_IG02,ins#11,ofs#44)
Generating: N024 (???,???) [000093] -----------                            IL_OFFSET void   INLRT @ 0x012[E-] REG NA
Generating: N026 (  3,  2) [000052] -----------                   t52 =    LCL_VAR   ref    V00 this          x0 REG x0
IN000c:             ldr     x0, [fp, #0x68]	// [V00 this]
							GC regs: 0000 {} => 0001 {x0}
                                                                        /--*  t52    ref    
Generating: N028 (  4,  3) [000053] ---X-O-----                         *  NULLCHECK byte   REG NA
							GC regs: 0001 {x0} => 0000 {}
IN000d:             ldrsb   wzr, [x0]
Generating: N030 (  3,  2) [000054] -----------                   t54 =    LCL_VAR   ref    V00 this          x0 REG x0
IN000e:             ldr     x0, [fp, #0x68]	// [V00 this]
							GC regs: 0000 {} => 0001 {x0}
Generating: N032 (  1,  2) [000055] -c---------                   t55 =    CNS_INT   long   80 Fseq[_dataTable] REG NA
                                                                        /--*  t54    ref    
                                                                        +--*  t55    long   
Generating: N034 (  5,  5) [000056] -----O-----                   t56 = *  ADD       byref  REG x0
							GC regs: 0001 {x0} => 0000 {}
IN000f:             add     x0, x0, #80
							Byref regs: 0000 {} => 0001 {x0}
                                                                        /--*  t56    byref  
Generating: N036 (???,???) [000100] -----O-----                  t100 = *  PUTARG_REG byref  REG x0
							Byref regs: 0001 {x0} => 0000 {}
							Byref regs: 0000 {} => 0001 {x0}
Generating: N038 (  3, 12) [000101] H----------                  t101 =    CNS_INT(h) long   0x7ffac1def648 ftn REG x1
IN0010:             movz    x1, #0xF648      // code for JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
IN0011:             movk    x1, #0xC1DE LSL #16
IN0012:             movk    x1, #0x7FFA LSL #32
                                                                        /--*  t101   long   
Generating: N040 (  6, 14) [000102] n---G------                  t102 = *  IND       long   REG x1
IN0013:             ldr     x1, [x1]
                                                                        /--*  t100   byref  this in x0
                                                                        +--*  t102   long   control expr
Generating: N042 ( 23, 11) [000009] --CXGO-----                    t9 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this REG x0
							Byref regs: 0001 {x0} => 0000 {}
Call: GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
IN0014:             blr     x1
Generating: N044 (  3,  2) [000006] -----------                    t6 =    LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0          d16 REG d16
IN0015:             ldr     q16, [fp, #0x50]	// [V01 loc0]
Generating: N046 (  1,  1) [000011] -----------                   t11 =    HWINTRINSIC mask   int CreateTrueMaskAll REG p0
IN0016:             ptrue   p0.s
                                                                        /--*  t11    mask   
                                                                        +--*  t6     simd16 
Generating: N048 (  5,  4) [000012] -----------                   t12 = *  HWINTRINSIC mask   int ConvertVectorToMask REG p0
IN0017:             cmpne   p0.s, p0/z, z16.s, #0
                                                                        /--*  t12    mask   
                                                                        +--*  t9     long   
Generating: N050 ( 29, 16) [000010] --CXGO-----                   t10 = *  HWINTRINSIC simd16 int LoadVector REG d16
IN0018:             ld1w    { z16.s }, p0/z, [x0]
                                                                        /--*  t10    simd16 
Generating: N052 ( 33, 19) [000017] DACXGO-----                         *  STORE_LCL_VAR simd16 V04 tmp1          NA REG NA
IN0019:             str     q16, [fp, #0x30]	// [V04 tmp1]
Generating: N054 (  3,  2) [000058] -----------                   t58 =    LCL_VAR   ref    V00 this          x0 REG x0
IN001a:             ldr     x0, [fp, #0x68]	// [V00 this]
							GC regs: 0000 {} => 0001 {x0}
                                                                        /--*  t58    ref    
Generating: N056 (  4,  3) [000059] ---X-O-----                         *  NULLCHECK byte   REG NA
							GC regs: 0001 {x0} => 0000 {}
IN001b:             ldrsb   wzr, [x0]
Generating: N058 (  3,  2) [000060] -----------                   t60 =    LCL_VAR   ref    V00 this          x0 REG x0
IN001c:             ldr     x0, [fp, #0x68]	// [V00 this]
							GC regs: 0000 {} => 0001 {x0}
Generating: N060 (  1,  2) [000061] -c---------                   t61 =    CNS_INT   long   80 Fseq[_dataTable] REG NA
                                                                        /--*  t60    ref    
                                                                        +--*  t61    long   
Generating: N062 (  5,  5) [000062] -----O-----                   t62 = *  ADD       byref  REG x0
							GC regs: 0001 {x0} => 0000 {}
IN001d:             add     x0, x0, #80
							Byref regs: 0000 {} => 0001 {x0}
                                                                        /--*  t62    byref  
Generating: N064 (???,???) [000103] -----O-----                  t103 = *  PUTARG_REG byref  REG x0
							Byref regs: 0001 {x0} => 0000 {}
							Byref regs: 0000 {} => 0001 {x0}
Generating: N066 (  3, 12) [000104] H----------                  t104 =    CNS_INT(h) long   0x7ffac1def660 ftn REG x1
IN001e:             movz    x1, #0xF660      // code for JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
IN001f:             movk    x1, #0xC1DE LSL #16
IN0020:             movk    x1, #0x7FFA LSL #32
                                                                        /--*  t104   long   
Generating: N068 (  6, 14) [000105] n---G------                  t105 = *  IND       long   REG x1
IN0021:             ldr     x1, [x1]
                                                                        /--*  t103   byref  this in x0
                                                                        +--*  t105   long   control expr
Generating: N070 ( 23, 11) [000016] --CXGO-----                   t16 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this REG x0
							Byref regs: 0001 {x0} => 0000 {}
Call: GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
IN0022:             blr     x1
Generating: N072 (  3,  2) [000013] -----------                   t13 =    LCL_VAR   simd16<System.Numerics.Vector`1> V01 loc0          d16 REG d16
IN0023:             ldr     q16, [fp, #0x50]	// [V01 loc0]
Generating: N074 (  1,  1) [000020] -----------                   t20 =    HWINTRINSIC mask   int CreateTrueMaskAll REG p0
IN0024:             ptrue   p0.s
                                                                        /--*  t20    mask   
                                                                        +--*  t13    simd16 
Generating: N076 (  5,  4) [000021] -----------                   t21 = *  HWINTRINSIC mask   int ConvertVectorToMask REG p0
IN0025:             cmpne   p0.s, p0/z, z16.s, #0
                                                                        /--*  t21    mask   
                                                                        +--*  t16    long   
Generating: N078 ( 29, 16) [000019] --CXGO-----                   t19 = *  HWINTRINSIC simd16 int LoadVector REG d16
IN0026:             ld1w    { z16.s }, p0/z, [x0]
Generating: N080 (  1,  1) [000025] -----------                   t25 =    HWINTRINSIC mask   int CreateTrueMaskAll REG p0
IN0027:             ptrue   p0.s
                                                                        /--*  t25    mask   
                                                                        +--*  t19    simd16 
Generating: N082 ( 31, 18) [000026] --CXGO-----                   t26 = *  HWINTRINSIC mask   int ConvertVectorToMask REG p0
IN0028:             cmpne   p0.s, p0/z, z16.s, #0
Generating: N084 (  3,  2) [000018] -----------                   t18 =    LCL_VAR   simd16 V04 tmp1          d16 REG d16
IN0029:             ldr     q16, [fp, #0x30]	// [V04 tmp1]
Generating: N086 (  1,  1) [000023] -----------                   t23 =    HWINTRINSIC mask   int CreateTrueMaskAll REG p1
IN002a:             ptrue   p1.s
                                                                        /--*  t23    mask   
                                                                        +--*  t18    simd16 
Generating: N088 (  5,  4) [000024] -----------                   t24 = *  HWINTRINSIC mask   int ConvertVectorToMask REG p1
IN002b:             cmpne   p1.s, p1/z, z16.s, #0
Generating: N090 (???,???) [000106] -----------                  t106 =    HWINTRINSIC mask   int CreateTrueMaskAll REG p2
IN002c:             ptrue   p2.s
Generating: N092 (???,???) [000107] -c---------                  t107 =    CNS_VEC   simd16<0x00000000, 0x00000000, 0x00000000, 0x00000000> REG NA
                                                                        /--*  t24    mask   
                                                                        +--*  t26    mask   
Generating: N094 ( 37, 23) [000022] -cCXGO-----                   t22 = *  HWINTRINSIC mask   int CreateBreakPropagateMask REG NA
                                                                        /--*  t106   mask   
                                                                        +--*  t22    mask   
                                                                        +--*  t107   simd16 
Generating: N096 (???,???) [000108] --CXGO-----                  t108 = *  HWINTRINSIC mask   int ConditionalSelect REG p0
IN002d:             brkn    p0.b, p2/z, p1.b, p0.b
                                                                        /--*  t108   mask   
Generating: N098 ( 38, 24) [000027] --CXGO-----                   t27 = *  HWINTRINSIC simd16 int ConvertMaskToVector REG d16
IN002e:             mov     z16.s, p0/z, #1
                                                                        /--*  t27    simd16 
Generating: N100 ( 42, 27) [000028] DACXGO-----                         *  STORE_LCL_VAR simd16<System.Numerics.Vector`1> V02 loc1          NA REG NA
IN002f:             str     q16, [fp, #0x40]	// [V02 loc1]
Added IP mapping: 0x003A STACK_EMPTY (G_M27522_IG02,ins#47,ofs#188)
Generating: N102 (???,???) [000094] -----------                            IL_OFFSET void   INLRT @ 0x03A[E-] REG NA
Generating: N104 (  3,  2) [000064] -----------                   t64 =    LCL_VAR   ref    V00 this          x0 REG x0
IN0030:             ldr     x0, [fp, #0x68]	// [V00 this]
							GC regs: 0000 {} => 0001 {x0}
                                                                        /--*  t64    ref    
Generating: N106 (  4,  3) [000065] ---X-O-----                         *  NULLCHECK byte   REG NA
							GC regs: 0001 {x0} => 0000 {}
IN0031:             ldrsb   wzr, [x0]
Generating: N108 (  3,  2) [000066] -----------                   t66 =    LCL_VAR   ref    V00 this          x0 REG x0
IN0032:             ldr     x0, [fp, #0x68]	// [V00 this]
							GC regs: 0000 {} => 0001 {x0}
Generating: N110 (  1,  2) [000067] -c---------                   t67 =    CNS_INT   long   80 Fseq[_dataTable] REG NA
                                                                        /--*  t66    ref    
                                                                        +--*  t67    long   
Generating: N112 (  5,  5) [000068] -----O-----                   t68 = *  ADD       byref  REG x0
							GC regs: 0001 {x0} => 0000 {}
IN0033:             add     x0, x0, #80
							Byref regs: 0000 {} => 0001 {x0}
                                                                        /--*  t68    byref  
Generating: N114 (???,???) [000109] -----O-----                  t109 = *  PUTARG_REG byref  REG x0
							Byref regs: 0001 {x0} => 0000 {}
							Byref regs: 0000 {} => 0001 {x0}
Generating: N116 (  3, 12) [000110] H----------                  t110 =    CNS_INT(h) long   0x7ffac1def678 ftn REG x1
IN0034:             movz    x1, #0xF678      // code for JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
IN0035:             movk    x1, #0xC1DE LSL #16
IN0036:             movk    x1, #0x7FFA LSL #32
                                                                        /--*  t110   long   
Generating: N118 (  6, 14) [000111] n---G------                  t111 = *  IND       long   REG x1
IN0037:             ldr     x1, [x1]
                                                                        /--*  t109   byref  this in x0
                                                                        +--*  t111   long   control expr
Generating: N120 ( 23, 11) [000031] --CXGO-----                   t31 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this REG x0
							Byref regs: 0001 {x0} => 0000 {}
Call: GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
IN0038:             blr     x1
Generating: N122 (  3,  2) [000032] -----------                   t32 =    LCL_VAR   simd16<System.Numerics.Vector`1> V02 loc1          d16 REG d16
IN0039:             ldr     q16, [fp, #0x40]	// [V02 loc1]
                                                                        /--*  t31    long   
                                                                        +--*  t32    simd16 
Generating: N124 ( 30, 16) [000033] -ACXGO-----                         *  STOREIND  simd16 (copy) REG NA
IN003a:             str     q16, [x0]
Added IP mapping: 0x004B STACK_EMPTY (G_M27522_IG02,ins#58,ofs#232)
Generating: N126 (???,???) [000095] -----------                            IL_OFFSET void   INLRT @ 0x04B[E-] REG NA
Generating: N128 (  3,  2) [000070] -----------                   t70 =    LCL_VAR   ref    V00 this          x0 REG x0
IN003b:             ldr     x0, [fp, #0x68]	// [V00 this]
							GC regs: 0000 {} => 0001 {x0}
                                                                        /--*  t70    ref    
Generating: N130 (  4,  3) [000071] ---X-O-----                         *  NULLCHECK byte   REG NA
							GC regs: 0001 {x0} => 0000 {}
IN003c:             ldrsb   wzr, [x0]
Generating: N132 (  3,  2) [000072] -----------                   t72 =    LCL_VAR   ref    V00 this          x0 REG x0
IN003d:             ldr     x0, [fp, #0x68]	// [V00 this]
							GC regs: 0000 {} => 0001 {x0}
Generating: N134 (  1,  2) [000073] -c---------                   t73 =    CNS_INT   long   80 Fseq[_dataTable] REG NA
                                                                        /--*  t72    ref    
                                                                        +--*  t73    long   
Generating: N136 (  5,  5) [000074] -----O-----                   t74 = *  ADD       byref  REG x0
							GC regs: 0001 {x0} => 0000 {}
IN003e:             add     x0, x0, #80
							Byref regs: 0000 {} => 0001 {x0}
                                                                        /--*  t74    byref  
Generating: N138 (???,???) [000112] -----O-----                  t112 = *  PUTARG_REG byref  REG x0
							Byref regs: 0001 {x0} => 0000 {}
							Byref regs: 0000 {} => 0001 {x0}
Generating: N140 (  3, 12) [000113] H----------                  t113 =    CNS_INT(h) long   0x7ffac1def648 ftn REG x1
IN003f:             movz    x1, #0xF648      // code for JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
IN0040:             movk    x1, #0xC1DE LSL #16
IN0041:             movk    x1, #0x7FFA LSL #32
                                                                        /--*  t113   long   
Generating: N142 (  6, 14) [000114] n---G------                  t114 = *  IND       long   REG x1
IN0042:             ldr     x1, [x1]
                                                                        /--*  t112   byref  this in x0
                                                                        +--*  t114   long   control expr
Generating: N144 ( 23, 11) [000037] --CXGO-----                   t37 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this REG x0
							Byref regs: 0001 {x0} => 0000 {}
Call: GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
IN0043:             blr     x1
                                                                        /--*  t37    long   
Generating: N146 ( 27, 14) [000041] DACXGO-----                         *  STORE_LCL_VAR long   V05 tmp2          NA REG NA
IN0044:             str     x0, [fp, #0x28]	// [V05 tmp2]
Generating: N148 (  3,  2) [000076] -----------                   t76 =    LCL_VAR   ref    V00 this          x0 REG x0
IN0045:             ldr     x0, [fp, #0x68]	// [V00 this]
							GC regs: 0000 {} => 0001 {x0}
                                                                        /--*  t76    ref    
Generating: N150 (  4,  3) [000077] ---X-O-----                         *  NULLCHECK byte   REG NA
							GC regs: 0001 {x0} => 0000 {}
IN0046:             ldrsb   wzr, [x0]
Generating: N152 (  3,  2) [000078] -----------                   t78 =    LCL_VAR   ref    V00 this          x0 REG x0
IN0047:             ldr     x0, [fp, #0x68]	// [V00 this]
							GC regs: 0000 {} => 0001 {x0}
Generating: N154 (  1,  2) [000079] -c---------                   t79 =    CNS_INT   long   80 Fseq[_dataTable] REG NA
                                                                        /--*  t78    ref    
                                                                        +--*  t79    long   
Generating: N156 (  5,  5) [000080] -----O-----                   t80 = *  ADD       byref  REG x0
							GC regs: 0001 {x0} => 0000 {}
IN0048:             add     x0, x0, #80
							Byref regs: 0000 {} => 0001 {x0}
                                                                        /--*  t80    byref  
Generating: N158 (???,???) [000115] -----O-----                  t115 = *  PUTARG_REG byref  REG x0
							Byref regs: 0001 {x0} => 0000 {}
							Byref regs: 0000 {} => 0001 {x0}
Generating: N160 (  3, 12) [000116] H----------                  t116 =    CNS_INT(h) long   0x7ffac1def660 ftn REG x1
IN0049:             movz    x1, #0xF660      // code for JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
IN004a:             movk    x1, #0xC1DE LSL #16
IN004b:             movk    x1, #0x7FFA LSL #32
                                                                        /--*  t116   long   
Generating: N162 (  6, 14) [000117] n---G------                  t117 = *  IND       long   REG x1
IN004c:             ldr     x1, [x1]
                                                                        /--*  t115   byref  this in x0
                                                                        +--*  t117   long   control expr
Generating: N164 ( 23, 11) [000040] --CXGO-----                   t40 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this REG x0
							Byref regs: 0001 {x0} => 0000 {}
Call: GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
IN004d:             blr     x1
                                                                        /--*  t40    long   
Generating: N166 ( 27, 14) [000046] DACXGO-----                         *  STORE_LCL_VAR long   V06 tmp3          NA REG NA
IN004e:             str     x0, [fp, #0x20]	// [V06 tmp3]
Generating: N168 (  3,  2) [000082] -----------                   t82 =    LCL_VAR   ref    V00 this          x0 REG x0
IN004f:             ldr     x0, [fp, #0x68]	// [V00 this]
							GC regs: 0000 {} => 0001 {x0}
                                                                        /--*  t82    ref    
Generating: N170 (  4,  3) [000083] ---X-O-----                         *  NULLCHECK byte   REG NA
							GC regs: 0001 {x0} => 0000 {}
IN0050:             ldrsb   wzr, [x0]
Generating: N172 (  3,  2) [000084] -----------                   t84 =    LCL_VAR   ref    V00 this          x0 REG x0
IN0051:             ldr     x0, [fp, #0x68]	// [V00 this]
							GC regs: 0000 {} => 0001 {x0}
Generating: N174 (  1,  2) [000085] -c---------                   t85 =    CNS_INT   long   80 Fseq[_dataTable] REG NA
                                                                        /--*  t84    ref    
                                                                        +--*  t85    long   
Generating: N176 (  5,  5) [000086] -----O-----                   t86 = *  ADD       byref  REG x0
							GC regs: 0001 {x0} => 0000 {}
IN0052:             add     x0, x0, #80
							Byref regs: 0000 {} => 0001 {x0}
                                                                        /--*  t86    byref  
Generating: N178 (???,???) [000118] -----O-----                  t118 = *  PUTARG_REG byref  REG x0
							Byref regs: 0001 {x0} => 0000 {}
							Byref regs: 0000 {} => 0001 {x0}
Generating: N180 (  3, 12) [000119] H----------                  t119 =    CNS_INT(h) long   0x7ffac1def678 ftn REG x1
IN0053:             movz    x1, #0xF678      // code for JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
IN0054:             movk    x1, #0xC1DE LSL #16
IN0055:             movk    x1, #0x7FFA LSL #32
                                                                        /--*  t119   long   
Generating: N182 (  6, 14) [000120] n---G------                  t120 = *  IND       long   REG x1
IN0056:             ldr     x1, [x1]
                                                                        /--*  t118   byref  this in x0
                                                                        +--*  t120   long   control expr
Generating: N184 ( 23, 11) [000045] --CXGO-----                   t45 = *  CALL      long   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this REG x0
							Byref regs: 0001 {x0} => 0000 {}
Call: GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
IN0057:             blr     x1
                                                                        /--*  t45    long   
Generating: N186 ( 27, 14) [000089] DACXGO-----                         *  STORE_LCL_VAR long   V07 tmp4          NA REG NA
IN0058:             str     x0, [fp, #0x18]	// [V07 tmp4]
Generating: N188 (  3,  2) [000090] -----------                   t90 =    LCL_VAR   long   V07 tmp4          x3 REG x3
IN0059:             ldr     x3, [fp, #0x18]	// [V07 tmp4]
                                                                        /--*  t90    long   
Generating: N190 (???,???) [000121] -----------                  t121 = *  PUTARG_REG long   REG x3
Generating: N192 (  3,  2) [000042] -----------                   t42 =    LCL_VAR   long   V05 tmp2          x1 REG x1
IN005a:             ldr     x1, [fp, #0x28]	// [V05 tmp2]
                                                                        /--*  t42    long   
Generating: N194 (???,???) [000122] -----------                  t122 = *  PUTARG_REG long   REG x1
Generating: N196 (  3,  2) [000047] -----------                   t47 =    LCL_VAR   long   V06 tmp3          x2 REG x2
IN005b:             ldr     x2, [fp, #0x20]	// [V06 tmp3]
                                                                        /--*  t47    long   
Generating: N198 (???,???) [000123] -----------                  t123 = *  PUTARG_REG long   REG x2
Generating: N200 (  3,  2) [000034] -----------                   t34 =    LCL_VAR   ref    V00 this          x0 REG x0
IN005c:             ldr     x0, [fp, #0x68]	// [V00 this]
							GC regs: 0000 {} => 0001 {x0}
                                                                        /--*  t34    ref    
Generating: N202 (???,???) [000124] -----------                  t124 = *  PUTARG_REG ref    REG x0
							GC regs: 0001 {x0} => 0000 {}
							GC regs: 0000 {} => 0001 {x0}
Generating: N204 (  3, 12) [000088] H----------                   t88 =    CNS_INT(h) ref     'RunBasicScenario_Load' REG x4
IN005d:             movz    x4, #0x58C8
IN005e:             movk    x4, #0xEB17 LSL #16
IN005f:             movk    x4, #574 LSL #32
							GC regs: 0001 {x0} => 0011 {x0 x4}
                                                                        /--*  t88    ref    
Generating: N206 (???,???) [000125] -----------                  t125 = *  PUTARG_REG ref    REG x4
							GC regs: 0011 {x0 x4} => 0001 {x0}
							GC regs: 0001 {x0} => 0011 {x0 x4}
Generating: N208 (  3, 12) [000126] H----------                  t126 =    CNS_INT(h) long   0x7ffac1def8b8 ftn REG x5
IN0060:             movz    x5, #0xF8B8      // code for JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:ValidateResult(ulong,ulong,ulong,System.String):this
IN0061:             movk    x5, #0xC1DE LSL #16
IN0062:             movk    x5, #0x7FFA LSL #32
                                                                        /--*  t126   long   
Generating: N210 (  6, 14) [000127] n---G------                  t127 = *  IND       long   REG x5
IN0063:             ldr     x5, [x5]
                                                                        /--*  t121   long   arg3 in x3
                                                                        +--*  t122   long   arg1 in x1
                                                                        +--*  t123   long   arg2 in x2
                                                                        +--*  t124   ref    this in x0
                                                                        +--*  t125   ref    arg4 in x4
                                                                        +--*  t127   long   control expr
Generating: N212 ( 59, 42) [000049] -ACXGO-----                         *  CALL      void   JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:ValidateResult(ulong,ulong,ulong,System.String):this REG NA
							GC regs: 0011 {x0 x4} => 0010 {x4}
							GC regs: 0010 {x4} => 0000 {}
Call: GCvars=0000000000000000 {}, gcrefRegs=0000 {}, byrefRegs=0000 {}
IN0064:             blr     x5
Added IP mapping: 0x0077 STACK_EMPTY (G_M27522_IG02,ins#100,ofs#400)
Generating: N214 (???,???) [000096] -----------                            IL_OFFSET void   INLRT @ 0x077[E-] REG NA
Generating: N216 (  0,  0) [000050] -----------                            RETURN    void   REG NA
Debug: Closing V00 debug range.
Debug: Closing V01 debug range.
Debug: Closing V02 debug range.
Added IP mapping: EPILOG (G_M27522_IG02,ins#100,ofs#400) label
Reserving epilog IG for block BB01
Saved:
      G_M27522_IG02:        ; offs=0x000000, size=0x0190, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref
Created:
      G_M27522_IG03:        ; offs=0x000190, size=0x0000, bbWeight=1, gcrefRegs=0000 {}
*************** After placeholder IG creation
G_M27522_IG01:        ; func=00, offs=0x000000, size=0x0000, bbWeight=1, gcrefRegs=0000 {} <-- Prolog IG
G_M27522_IG02:        ; offs=0x000000, size=0x0190, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref
G_M27522_IG03:        ; epilog placeholder, next placeholder=<END>, BB01 [0000], epilog, extend <-- First placeholder <-- Last placeholder
                      ;   PrevGCVars=0000000000000000 {}, PrevGCrefRegs=0000 {}, PrevByrefRegs=0000 {}
                      ;   InitGCVars=0000000000000000 {}, InitGCrefRegs=0000 {}, InitByrefRegs=0000 {}

Variable Live Range History Dump for BB01
V00 this: fp[104] (1 slot) [(G_M27522_IG02,ins#0,ofs#0), (G_M27522_IG02,ins#100,ofs#400)]
V01 loc0: fp[80] (1 slot) [(G_M27522_IG02,ins#0,ofs#0), (G_M27522_IG02,ins#100,ofs#400)]
V02 loc1: fp[64] (1 slot) [(G_M27522_IG02,ins#0,ofs#0), (G_M27522_IG02,ins#100,ofs#400)]
Liveness not changing: 0000000000000000 {}

# compCycleEstimate =    242, compSizeEstimate =   154 JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:RunBasicScenario_Load():this
; Final local variable assignments
;
;  V00 this         [V00    ] (  1,  1   )     ref  ->  [fp+0x68]  do-not-enreg[] this class-hnd <JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int>
;  V01 loc0         [V01    ] (  1,  1   )  simd16  ->  [fp+0x50]  HFA(simd16)  do-not-enreg[S] must-init <System.Numerics.Vector`1[int]>
;  V02 loc1         [V02    ] (  1,  1   )  simd16  ->  [fp+0x40]  HFA(simd16)  do-not-enreg[S] must-init <System.Numerics.Vector`1[int]>
;# V03 OutArgs      [V03    ] (  1,  1   )  struct ( 0) [sp+0x00]  do-not-enreg[XS] addr-exposed "OutgoingArgSpace"
;  V04 tmp1         [V04    ] (  1,  1   )  simd16  ->  [fp+0x30]  do-not-enreg[S] "non-inline candidate call"
;  V05 tmp2         [V05    ] (  1,  1   )    long  ->  [fp+0x28]  do-not-enreg[] "non-inline candidate call"
;  V06 tmp3         [V06    ] (  1,  1   )    long  ->  [fp+0x20]  do-not-enreg[] "non-inline candidate call"
;  V07 tmp4         [V07    ] (  1,  1   )    long  ->  [fp+0x18]  do-not-enreg[] "argument with side effect"
;
; Lcl frame size = 96
*************** Before prolog / epilog generation
G_M27522_IG01:        ; func=00, offs=0x000000, size=0x0000, bbWeight=1, gcrefRegs=0000 {} <-- Prolog IG
G_M27522_IG02:        ; offs=0x000000, size=0x0190, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref
G_M27522_IG03:        ; epilog placeholder, next placeholder=<END>, BB01 [0000], epilog, extend <-- First placeholder <-- Last placeholder
                      ;   PrevGCVars=0000000000000000 {}, PrevGCrefRegs=0000 {}, PrevByrefRegs=0000 {}
                      ;   InitGCVars=0000000000000000 {}, InitGCrefRegs=0000 {}, InitByrefRegs=0000 {}
*************** In genFnProlog()
Added IP mapping to front: PROLOG (G_M27522_IG01,ins#0,ofs#0) label

__prolog:
Debug: New V00 debug range: first
Found 8 lvMustInit int-sized stack slots, frame offsets -64 through -96
Save float regs: []
Save int   regs: [fp lr]
Frame type 1. #outsz=0; #framesz=112; LclFrameSize=96
IN0065:             stp     fp, lr, [sp, #-0x70]!
    offset=112, calleeSaveSpDelta=0
    offsetSpToSavedFp=0
IN0066:             mov     fp, sp
IN0067:             str     xzr, [fp, #0x50]	// [V01 loc0]
IN0068:             str     xzr, [fp, #0x58]	// [V01 loc0+0x08]
IN0069:             str     xzr, [fp, #0x40]	// [V02 loc1]
IN006a:             str     xzr, [fp, #0x48]	// [V02 loc1+0x08]
*************** In genHomeRegisterParams()
IN006b:             str     x0, [fp, #0x68]	// [V00 this]
*************** In genEnregisterIncomingStackArgs()
Debug: Closing V00 debug range.

Saved:
      G_M27522_IG01:        ; offs=0x000000, size=0x001C, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc
*************** In genFnEpilog()

__epilog:
gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=0000 {}, gcRegByrefSetCur=0000 {}
Frame type 1. #outsz=0; #framesz=112; localloc? false
    calleeSaveSpOffset=112, calleeSaveSpDelta=0
IN006c:             ldp     fp, lr, [sp], #0x70
IN006d:             ret     lr
Saved:
      G_M27522_IG03:        ; offs=0x000190, size=0x0008, bbWeight=1, epilog, nogc, extend
0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs
*************** After prolog / epilog generation
G_M27522_IG01:        ; func=00, offs=0x000000, size=0x001C, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
G_M27522_IG02:        ; offs=0x00001C, size=0x0190, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref
G_M27522_IG03:        ; offs=0x0001AC, size=0x0008, bbWeight=1, epilog, nogc, extend
*************** In emitJumpDistBind()
Emitter Jump List:
  total jump count: 0

*************** Finishing PHASE Generate code

*************** Starting PHASE Emit code

Hot  code size = 0x1B4 bytes
Cold code size = 0x0 bytes
reserveUnwindInfo(isFunclet=false, isColdCode=false, unwindSize=0xc)
*************** In emitEndCodeGen()
Converting emitMaxStackDepth from bytes (0) to elements (0)

***************************************************************************
Instructions as they come out of the scheduler


G_M27522_IG01:        ; offs=0x000000, size=0x001C, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG
IN0065: 000000      stp     fp, lr, [sp, #-0x70]!
IN0066: 000004      mov     fp, sp
IN0067: 000008      str     xzr, [fp, #0x50]	// [V01 loc0]
IN0068: 00000C      str     xzr, [fp, #0x58]	// [V01 loc0+0x08]
IN0069: 000010      str     xzr, [fp, #0x40]	// [V02 loc1]
IN006a: 000014      str     xzr, [fp, #0x48]	// [V02 loc1+0x08]
IN006b: 000018      str     x0, [fp, #0x68]	// [V00 this]
						;; size=28 bbWeight=1 PerfScore 6.50
G_M27522_IG02:        ; offs=0x00001C, size=0x0190, bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref
IN0001: 00001C      movz    x0, #0x58C8
IN0002: 000020      movk    x0, #0xEB17 LSL #16
IN0003: 000024      movk    x0, #574 LSL #32
IN0004: 000028      movz    x1, #0x4528      // code for TestLibrary.TestFramework:BeginScenario(System.String)
IN0005: 00002C      movk    x1, #0xC211 LSL #16
IN0006: 000030      movk    x1, #0x7FFA LSL #32
IN0007: 000034      ldr     x1, [x1]
; Call at 0038 [stk=0], GCvars=none, gcrefRegs=0000 {}, byrefRegs=0000 {}
IN0008: 000038      blr     x1
IN0009: 00003C      ptrue   p0.s
IN000a: 000040      mov     z16.s, p0/z, #1
IN000b: 000044      str     q16, [fp, #0x50]	// [V01 loc0]
IN000c: 000048      ldr     x0, [fp, #0x68]	// [V00 this]
                             ; gcrRegs +[x0]
IN000d: 00004C      ldrsb   wzr, [x0]
IN000e: 000050      ldr     x0, [fp, #0x68]	// [V00 this]
IN000f: 000054      add     x0, x0, #80
                             ; gcrRegs -[x0]
                             ; byrRegs +[x0]
IN0010: 000058      movz    x1, #0xF648      // code for JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
IN0011: 00005C      movk    x1, #0xC1DE LSL #16
IN0012: 000060      movk    x1, #0x7FFA LSL #32
IN0013: 000064      ldr     x1, [x1]
; Call at 0068 [stk=0], GCvars=none, gcrefRegs=0000 {}, byrefRegs=0000 {}
IN0014: 000068      blr     x1
                             ; byrRegs -[x0]
IN0015: 00006C      ldr     q16, [fp, #0x50]	// [V01 loc0]
IN0016: 000070      ptrue   p0.s
IN0017: 000074      cmpne   p0.s, p0/z, z16.s, #0
IN0018: 000078      ld1w    { z16.s }, p0/z, [x0]
IN0019: 00007C      str     q16, [fp, #0x30]	// [V04 tmp1]
IN001a: 000080      ldr     x0, [fp, #0x68]	// [V00 this]
                             ; gcrRegs +[x0]
IN001b: 000084      ldrsb   wzr, [x0]
IN001c: 000088      ldr     x0, [fp, #0x68]	// [V00 this]
IN001d: 00008C      add     x0, x0, #80
                             ; gcrRegs -[x0]
                             ; byrRegs +[x0]
IN001e: 000090      movz    x1, #0xF660      // code for JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
IN001f: 000094      movk    x1, #0xC1DE LSL #16
IN0020: 000098      movk    x1, #0x7FFA LSL #32
IN0021: 00009C      ldr     x1, [x1]
; Call at 00A0 [stk=0], GCvars=none, gcrefRegs=0000 {}, byrefRegs=0000 {}
IN0022: 0000A0      blr     x1
                             ; byrRegs -[x0]
IN0023: 0000A4      ldr     q16, [fp, #0x50]	// [V01 loc0]
IN0024: 0000A8      ptrue   p0.s
IN0025: 0000AC      cmpne   p0.s, p0/z, z16.s, #0
IN0026: 0000B0      ld1w    { z16.s }, p0/z, [x0]
IN0027: 0000B4      ptrue   p0.s
IN0028: 0000B8      cmpne   p0.s, p0/z, z16.s, #0
IN0029: 0000BC      ldr     q16, [fp, #0x30]	// [V04 tmp1]
IN002a: 0000C0      ptrue   p1.s
IN002b: 0000C4      cmpne   p1.s, p1/z, z16.s, #0
IN002c: 0000C8      ptrue   p2.s
IN002d: 0000CC      brkn    p0.b, p2/z, p1.b, p0.b
IN002e: 0000D0      mov     z16.s, p0/z, #1
IN002f: 0000D4      str     q16, [fp, #0x40]	// [V02 loc1]
IN0030: 0000D8      ldr     x0, [fp, #0x68]	// [V00 this]
                             ; gcrRegs +[x0]
IN0031: 0000DC      ldrsb   wzr, [x0]
IN0032: 0000E0      ldr     x0, [fp, #0x68]	// [V00 this]
IN0033: 0000E4      add     x0, x0, #80
                             ; gcrRegs -[x0]
                             ; byrRegs +[x0]
IN0034: 0000E8      movz    x1, #0xF678      // code for JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
IN0035: 0000EC      movk    x1, #0xC1DE LSL #16
IN0036: 0000F0      movk    x1, #0x7FFA LSL #32
IN0037: 0000F4      ldr     x1, [x1]
; Call at 00F8 [stk=0], GCvars=none, gcrefRegs=0000 {}, byrefRegs=0000 {}
IN0038: 0000F8      blr     x1
                             ; byrRegs -[x0]
IN0039: 0000FC      ldr     q16, [fp, #0x40]	// [V02 loc1]
IN003a: 000100      str     q16, [x0]
IN003b: 000104      ldr     x0, [fp, #0x68]	// [V00 this]
                             ; gcrRegs +[x0]
IN003c: 000108      ldrsb   wzr, [x0]
IN003d: 00010C      ldr     x0, [fp, #0x68]	// [V00 this]
IN003e: 000110      add     x0, x0, #80
                             ; gcrRegs -[x0]
                             ; byrRegs +[x0]
IN003f: 000114      movz    x1, #0xF648      // code for JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
IN0040: 000118      movk    x1, #0xC1DE LSL #16
IN0041: 00011C      movk    x1, #0x7FFA LSL #32
IN0042: 000120      ldr     x1, [x1]
; Call at 0124 [stk=0], GCvars=none, gcrefRegs=0000 {}, byrefRegs=0000 {}
IN0043: 000124      blr     x1
                             ; byrRegs -[x0]
IN0044: 000128      str     x0, [fp, #0x28]	// [V05 tmp2]
IN0045: 00012C      ldr     x0, [fp, #0x68]	// [V00 this]
                             ; gcrRegs +[x0]
IN0046: 000130      ldrsb   wzr, [x0]
IN0047: 000134      ldr     x0, [fp, #0x68]	// [V00 this]
IN0048: 000138      add     x0, x0, #80
                             ; gcrRegs -[x0]
                             ; byrRegs +[x0]
IN0049: 00013C      movz    x1, #0xF660      // code for JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
IN004a: 000140      movk    x1, #0xC1DE LSL #16
IN004b: 000144      movk    x1, #0x7FFA LSL #32
IN004c: 000148      ldr     x1, [x1]
; Call at 014C [stk=0], GCvars=none, gcrefRegs=0000 {}, byrefRegs=0000 {}
IN004d: 00014C      blr     x1
                             ; byrRegs -[x0]
IN004e: 000150      str     x0, [fp, #0x20]	// [V06 tmp3]
IN004f: 000154      ldr     x0, [fp, #0x68]	// [V00 this]
                             ; gcrRegs +[x0]
IN0050: 000158      ldrsb   wzr, [x0]
IN0051: 00015C      ldr     x0, [fp, #0x68]	// [V00 this]
IN0052: 000160      add     x0, x0, #80
                             ; gcrRegs -[x0]
                             ; byrRegs +[x0]
IN0053: 000164      movz    x1, #0xF678      // code for JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
IN0054: 000168      movk    x1, #0xC1DE LSL #16
IN0055: 00016C      movk    x1, #0x7FFA LSL #32
IN0056: 000170      ldr     x1, [x1]
; Call at 0174 [stk=0], GCvars=none, gcrefRegs=0000 {}, byrefRegs=0000 {}
IN0057: 000174      blr     x1
                             ; byrRegs -[x0]
IN0058: 000178      str     x0, [fp, #0x18]	// [V07 tmp4]
IN0059: 00017C      ldr     x3, [fp, #0x18]	// [V07 tmp4]
IN005a: 000180      ldr     x1, [fp, #0x28]	// [V05 tmp2]
IN005b: 000184      ldr     x2, [fp, #0x20]	// [V06 tmp3]
IN005c: 000188      ldr     x0, [fp, #0x68]	// [V00 this]
                             ; gcrRegs +[x0]
IN005d: 00018C      movz    x4, #0x58C8
IN005e: 000190      movk    x4, #0xEB17 LSL #16
IN005f: 000194      movk    x4, #574 LSL #32
IN0060: 000198      movz    x5, #0xF8B8      // code for JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:ValidateResult(ulong,ulong,ulong,System.String):this
IN0061: 00019C      movk    x5, #0xC1DE LSL #16
IN0062: 0001A0      movk    x5, #0x7FFA LSL #32
IN0063: 0001A4      ldr     x5, [x5]
; Call at 01A8 [stk=0], GCvars=none, gcrefRegs=0000 {}, byrefRegs=0000 {}
IN0064: 0001A8      blr     x5
                             ; gcrRegs -[x0]
						;; size=400 bbWeight=1 PerfScore 160.00
G_M27522_IG03:        ; offs=0x0001AC, size=0x0008, bbWeight=1, epilog, nogc, extend
IN006c: 0001AC      ldp     fp, lr, [sp], #0x70
IN006d: 0001B0      ret     lr
						;; size=8 bbWeight=1 PerfScore 2.00

Allocated method code size =  436 , actual size =  436, unused size =    0

; Total bytes of code 436, prolog size 24, PerfScore 168.50, instruction count 109, allocated bytes for code 436 (MethodHash=8627947d) for method JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:RunBasicScenario_Load():this (Tier0)
; ============================================================

*************** After end code gen, before unwindEmit()
G_M27522_IG01:        ; func=00, offs=0x000000, size=0x001C, bbWeight=1, PerfScore 6.50, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, nogc <-- Prolog IG

IN0065: 000000      stp     fp, lr, [sp, #-0x70]!
IN0066: 000004      mov     fp, sp
IN0067: 000008      str     xzr, [fp, #0x50]	// [V01 loc0]
IN0068: 00000C      str     xzr, [fp, #0x58]	// [V01 loc0+0x08]
IN0069: 000010      str     xzr, [fp, #0x40]	// [V02 loc1]
IN006a: 000014      str     xzr, [fp, #0x48]	// [V02 loc1+0x08]
IN006b: 000018      str     x0, [fp, #0x68]	// [V00 this]

G_M27522_IG02:        ; offs=0x00001C, size=0x0190, bbWeight=1, PerfScore 160.00, gcrefRegs=0000 {}, byrefRegs=0000 {}, BB01 [0000], byref

IN0001: 00001C      movz    x0, #0x58C8
IN0002: 000020      movk    x0, #0xEB17 LSL #16
IN0003: 000024      movk    x0, #574 LSL #32
IN0004: 000028      movz    x1, #0x4528      // code for TestLibrary.TestFramework:BeginScenario(System.String)
IN0005: 00002C      movk    x1, #0xC211 LSL #16
IN0006: 000030      movk    x1, #0x7FFA LSL #32
IN0007: 000034      ldr     x1, [x1]
IN0008: 000038      blr     x1
IN0009: 00003C      ptrue   p0.s
IN000a: 000040      mov     z16.s, p0/z, #1
IN000b: 000044      str     q16, [fp, #0x50]	// [V01 loc0]
IN000c: 000048      ldr     x0, [fp, #0x68]	// [V00 this]
IN000d: 00004C      ldrsb   wzr, [x0]
IN000e: 000050      ldr     x0, [fp, #0x68]	// [V00 this]
IN000f: 000054      add     x0, x0, #80
IN0010: 000058      movz    x1, #0xF648      // code for JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
IN0011: 00005C      movk    x1, #0xC1DE LSL #16
IN0012: 000060      movk    x1, #0x7FFA LSL #32
IN0013: 000064      ldr     x1, [x1]
IN0014: 000068      blr     x1
IN0015: 00006C      ldr     q16, [fp, #0x50]	// [V01 loc0]
IN0016: 000070      ptrue   p0.s
IN0017: 000074      cmpne   p0.s, p0/z, z16.s, #0
IN0018: 000078      ld1w    { z16.s }, p0/z, [x0]
IN0019: 00007C      str     q16, [fp, #0x30]	// [V04 tmp1]
IN001a: 000080      ldr     x0, [fp, #0x68]	// [V00 this]
IN001b: 000084      ldrsb   wzr, [x0]
IN001c: 000088      ldr     x0, [fp, #0x68]	// [V00 this]
IN001d: 00008C      add     x0, x0, #80
IN001e: 000090      movz    x1, #0xF660      // code for JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
IN001f: 000094      movk    x1, #0xC1DE LSL #16
IN0020: 000098      movk    x1, #0x7FFA LSL #32
IN0021: 00009C      ldr     x1, [x1]
IN0022: 0000A0      blr     x1
IN0023: 0000A4      ldr     q16, [fp, #0x50]	// [V01 loc0]
IN0024: 0000A8      ptrue   p0.s
IN0025: 0000AC      cmpne   p0.s, p0/z, z16.s, #0
IN0026: 0000B0      ld1w    { z16.s }, p0/z, [x0]
IN0027: 0000B4      ptrue   p0.s
IN0028: 0000B8      cmpne   p0.s, p0/z, z16.s, #0
IN0029: 0000BC      ldr     q16, [fp, #0x30]	// [V04 tmp1]
IN002a: 0000C0      ptrue   p1.s
IN002b: 0000C4      cmpne   p1.s, p1/z, z16.s, #0
IN002c: 0000C8      ptrue   p2.s
IN002d: 0000CC      brkn    p0.b, p2/z, p1.b, p0.b
IN002e: 0000D0      mov     z16.s, p0/z, #1
IN002f: 0000D4      str     q16, [fp, #0x40]	// [V02 loc1]
IN0030: 0000D8      ldr     x0, [fp, #0x68]	// [V00 this]
IN0031: 0000DC      ldrsb   wzr, [x0]
IN0032: 0000E0      ldr     x0, [fp, #0x68]	// [V00 this]
IN0033: 0000E4      add     x0, x0, #80
IN0034: 0000E8      movz    x1, #0xF678      // code for JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
IN0035: 0000EC      movk    x1, #0xC1DE LSL #16
IN0036: 0000F0      movk    x1, #0x7FFA LSL #32
IN0037: 0000F4      ldr     x1, [x1]
IN0038: 0000F8      blr     x1
IN0039: 0000FC      ldr     q16, [fp, #0x40]	// [V02 loc1]
IN003a: 000100      str     q16, [x0]
IN003b: 000104      ldr     x0, [fp, #0x68]	// [V00 this]
IN003c: 000108      ldrsb   wzr, [x0]
IN003d: 00010C      ldr     x0, [fp, #0x68]	// [V00 this]
IN003e: 000110      add     x0, x0, #80
IN003f: 000114      movz    x1, #0xF648      // code for JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray1Ptr():ulong:this
IN0040: 000118      movk    x1, #0xC1DE LSL #16
IN0041: 00011C      movk    x1, #0x7FFA LSL #32
IN0042: 000120      ldr     x1, [x1]
IN0043: 000124      blr     x1
IN0044: 000128      str     x0, [fp, #0x28]	// [V05 tmp2]
IN0045: 00012C      ldr     x0, [fp, #0x68]	// [V00 this]
IN0046: 000130      ldrsb   wzr, [x0]
IN0047: 000134      ldr     x0, [fp, #0x68]	// [V00 this]
IN0048: 000138      add     x0, x0, #80
IN0049: 00013C      movz    x1, #0xF660      // code for JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_inArray2Ptr():ulong:this
IN004a: 000140      movk    x1, #0xC1DE LSL #16
IN004b: 000144      movk    x1, #0x7FFA LSL #32
IN004c: 000148      ldr     x1, [x1]
IN004d: 00014C      blr     x1
IN004e: 000150      str     x0, [fp, #0x20]	// [V06 tmp3]
IN004f: 000154      ldr     x0, [fp, #0x68]	// [V00 this]
IN0050: 000158      ldrsb   wzr, [x0]
IN0051: 00015C      ldr     x0, [fp, #0x68]	// [V00 this]
IN0052: 000160      add     x0, x0, #80
IN0053: 000164      movz    x1, #0xF678      // code for JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int+DataTable:get_outArrayPtr():ulong:this
IN0054: 000168      movk    x1, #0xC1DE LSL #16
IN0055: 00016C      movk    x1, #0x7FFA LSL #32
IN0056: 000170      ldr     x1, [x1]
IN0057: 000174      blr     x1
IN0058: 000178      str     x0, [fp, #0x18]	// [V07 tmp4]
IN0059: 00017C      ldr     x3, [fp, #0x18]	// [V07 tmp4]
IN005a: 000180      ldr     x1, [fp, #0x28]	// [V05 tmp2]
IN005b: 000184      ldr     x2, [fp, #0x20]	// [V06 tmp3]
IN005c: 000188      ldr     x0, [fp, #0x68]	// [V00 this]
IN005d: 00018C      movz    x4, #0x58C8
IN005e: 000190      movk    x4, #0xEB17 LSL #16
IN005f: 000194      movk    x4, #574 LSL #32
IN0060: 000198      movz    x5, #0xF8B8      // code for JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:ValidateResult(ulong,ulong,ulong,System.String):this
IN0061: 00019C      movk    x5, #0xC1DE LSL #16
IN0062: 0001A0      movk    x5, #0x7FFA LSL #32
IN0063: 0001A4      ldr     x5, [x5]
IN0064: 0001A8      blr     x5

G_M27522_IG03:        ; offs=0x0001AC, size=0x0008, bbWeight=1, PerfScore 2.00, epilog, nogc, extend

IN006c: 0001AC      ldp     fp, lr, [sp], #0x70
IN006d: 0001B0      ret     lr


*************** Finishing PHASE Emit code

*************** Starting PHASE Emit GC+EH tables
Unwind Info:
  >> Start offset   : 0x000000 (not in unwind data)
  >>   End offset   : 0x0001b4 (not in unwind data)
  Code Words        : 1
  Epilog Count      : 1
  E bit             : 0
  X bit             : 0
  Vers              : 0
  Function Length   : 109 (0x0006d) Actual length = 436 (0x0001b4)
  ---- Epilog scopes ----
  ---- Scope 0
  Epilog Start Offset        : 107 (0x0006b) Actual offset = 428 (0x0001ac) Offset from main function begin = 428 (0x0001ac)
  Epilog Start Index         : 1 (0x01)
  ---- Unwind codes ----
    E1          set_fp; mov fp, sp
    ---- Epilog start at index 1 ----
    8D          save_fplr_x #13 (0x0D); stp fp, lr, [sp, #-112]!
    E4          end
    E4          end

allocUnwindInfo(pHotCode=0x00007FFAC1E27A18, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x1b4, unwindSize=0xc, pUnwindBlock=0x0000023EEDC5B04A, funKind=0 (main function))
*************** In genIPmappingGen()
IP mapping count : 8
IL offs PROLOG : 0x00000000 ( STACK_EMPTY )
IL offs 0x0000 : 0x0000001C ( STACK_EMPTY )
IL offs 0x000A : 0x0000003C ( STACK_EMPTY )
IL offs 0x0012 : 0x00000048 ( STACK_EMPTY )
IL offs 0x003A : 0x000000D8 ( STACK_EMPTY )
IL offs 0x004B : 0x00000104 ( STACK_EMPTY )
IL offs 0x0077 : 0x000001AC ( STACK_EMPTY )
IL offs EPILOG : 0x000001AC ( STACK_EMPTY )

*************** In genSetScopeInfo()
VarLocInfo count is 4
; Variable debug info: 4 live ranges, 3 vars for method JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:RunBasicScenario_Load():this
(V00 this) : From 00000000h to 0000001Ch, in x0
(V00 this) : From 0000001Ch to 000001ACh, in fp[104] (1 slot)
(V01 loc0) : From 0000001Ch to 000001ACh, in fp[80] (1 slot)
(V02 loc1) : From 0000001Ch to 000001ACh, in fp[64] (1 slot)
*************** In gcInfoBlockHdrSave()
Set code length to 436.
Set ReturnKind to Scalar.
Set stack base register to fp.
Set Outgoing stack arg area size to 0.
Stack slot id for offset 104 (0x68) (frame) (untracked) = 0.
Defining 8 call sites:
    Offset 0x38, size 4.
    Offset 0x68, size 4.
    Offset 0xa0, size 4.
    Offset 0xf8, size 4.
    Offset 0x124, size 4.
    Offset 0x14c, size 4.
    Offset 0x174, size 4.
    Offset 0x1a8, size 4.

*************** Finishing PHASE Emit GC+EH tables
Method code size: 436

Allocations for JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:RunBasicScenario_Load():this (MethodHash=8627947d)
count:        983, size:      99060, max =       7808
allocateMemory:     131072, nraUsed:     102360

Alloc'd bytes by kind:
                  kind |       size |     pct
  ---------------------+------------+--------
                   ABI |          0 |   0.00%
         AssertionProp |          0 |   0.00%
               ASTNode |      17848 |  18.02%
              InstDesc |      13304 |  13.43%
              ImpStack |        384 |   0.39%
            BasicBlock |        640 |   0.65%
              CallArgs |       1248 |   1.26%
              FlowEdge |          0 |   0.00%
      DepthFirstSearch |         32 |   0.03%
                 Loops |          0 |   0.00%
     TreeStatementList |          0 |   0.00%
               SiScope |          0 |   0.00%
       DominatorMemory |          0 |   0.00%
                  LSRA |       9480 |   9.57%
         LSRA_Interval |       7392 |   7.46%
      LSRA_RefPosition |      16400 |  16.56%
          Reachability |          0 |   0.00%
                   SSA |          0 |   0.00%
           ValueNumber |          0 |   0.00%
              LvaTable |       1688 |   1.70%
            UnwindInfo |         32 |   0.03%
                hashBv |         40 |   0.04%
                bitset |        272 |   0.27%
          FixedBitVect |         40 |   0.04%
               Generic |        958 |   0.97%
   LocalAddressVisitor |        384 |   0.39%
         FieldSeqStore |        144 |   0.15%
          MemorySsaMap |          0 |   0.00%
          MemoryPhiArg |          0 |   0.00%
                   CSE |          0 |   0.00%
                    GC |       1800 |   1.82%
       CorTailCallInfo |          0 |   0.00%
              Inlining |        248 |   0.25%
            ArrayStack |        128 |   0.13%
             DebugInfo |        504 |   0.51%
             DebugOnly |      22419 |  22.63%
               Codegen |       2560 |   2.58%
               LoopOpt |          0 |   0.00%
             LoopClone |          0 |   0.00%
            LoopUnroll |          0 |   0.00%
             LoopHoist |          0 |   0.00%
            LoopIVOpts |          0 |   0.00%
               Unknown |         59 |   0.06%
            RangeCheck |          0 |   0.00%
              CopyProp |          0 |   0.00%
             Promotion |        120 |   0.12%
           SideEffects |          0 |   0.00%
       ObjectAllocator |          0 |   0.00%
    VariableLiveRanges |        808 |   0.82%
           ClassLayout |        128 |   0.13%
       TailMergeThrows |          0 |   0.00%
             EarlyProp |          0 |   0.00%
              ZeroInit |          0 |   0.00%
                   Pgo |          0 |   0.00%

Final metrics:
PhysicallyPromotedFields                  : 0
LoopsFoundDuringOpts                      : 0
LoopsCloned                               : 0
LoopsUnrolled                             : 0
LoopAlignmentCandidates                   : 0
LoopsAligned                              : 0
LoopsIVWidened                            : 0
WidenedIVs                                : 0
LoopsMadeDownwardsCounted                 : 0
LoopsStrengthReduced                      : 0
VarsInSsa                                 : 0
HoistedExpressions                        : 0
RedundantBranchesEliminated               : 0
JumpThreadingsPerformed                   : 0
CseCount                                  : 0
BasicBlocksAtCodegen                      : 1
PerfScore                                 : 168.500000
BytesAllocated                            : 102360
ImporterBranchFold                        : 0
ImporterSwitchFold                        : 0
DevirtualizedCall                         : 0
DevirtualizedCallUnboxedEntry             : 0
DevirtualizedCallRemovedBox               : 0
GDV                                       : 0
ClassGDV                                  : 0
MethodGDV                                 : 0
MultiGuessGDV                             : 0
ChainedGDV                                : 0
InlinerBranchFold                         : 0
InlineAttempt                             : 0
InlineCount                               : 0
ProfileConsistentBeforeInline             : 0
ProfileConsistentAfterInline              : 0
ProfileSynthesizedBlendedOrRepaired       : 0
ProfileInconsistentInitially              : 0
ProfileInconsistentResetLeave             : 0
ProfileInconsistentImporterBranchFold     : 0
ProfileInconsistentImporterSwitchFold     : 0
ProfileInconsistentChainedGDV             : 0
ProfileInconsistentScratchBB              : 0
ProfileInconsistentInlinerBranchFold      : 0
ProfileInconsistentInlineeScale           : 0
ProfileInconsistentInlinee                : 0
ProfileInconsistentNoReturnInlinee        : 0
ProfileInconsistentMayThrowInlinee        : 0
NewRefClassHelperCalls                    : 0
StackAllocatedRefClasses                  : 0
NewBoxedValueClassHelperCalls             : 0
StackAllocatedBoxedValueClasses           : 0

****** DONE compiling JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_CreateBreakPropagateMask_int:RunBasicScenario_Load():this
Beginning scenario: RunBasicScenario_Load
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunClassFldScenario
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructFldScenario
Beginning scenario: ConditionalSelect_Op1_mask - operation in TrueValue
Beginning scenario: ConditionalSelect_Op1_zero - operation in TrueValue
Beginning scenario: ConditionalSelect_Op1_all - operation in TrueValue
Beginning scenario: ConditionalSelect_Op1_mask - operation in FalseValue
Beginning scenario: ConditionalSelect_Op1_zero - operation in FalseValue
Beginning scenario: ConditionalSelect_Op1_all - operation in FalseValue
Beginning scenario: ConditionalSelect_Op2_mask - operation in TrueValue
Beginning scenario: ConditionalSelect_Op2_zero - operation in TrueValue
Beginning scenario: ConditionalSelect_Op2_all - operation in TrueValue
Beginning scenario: ConditionalSelect_Op2_mask - operation in FalseValue
Beginning scenario: ConditionalSelect_Op2_zero - operation in FalseValue
Beginning scenario: ConditionalSelect_Op2_all - operation in FalseValue
Beginning scenario: ConditionalSelect_FalseOp_mask - operation in TrueValue
Beginning scenario: ConditionalSelect_FalseOp_zero - operation in TrueValue
Beginning scenario: ConditionalSelect_FalseOp_all - operation in TrueValue
Beginning scenario: ConditionalSelect_FalseOp_mask - operation in FalseValue
Beginning scenario: ConditionalSelect_FalseOp_zero - operation in FalseValue
Beginning scenario: ConditionalSelect_FalseOp_all - operation in FalseValue
Beginning scenario: ConditionalSelect_ZeroOp_mask - operation in TrueValue
Beginning scenario: ConditionalSelect_ZeroOp_zero - operation in TrueValue
Beginning scenario: ConditionalSelect_ZeroOp_all - operation in TrueValue
Beginning scenario: ConditionalSelect_ZeroOp_mask - operation in FalseValue
Beginning scenario: ConditionalSelect_ZeroOp_zero - operation in FalseValue
Beginning scenario: ConditionalSelect_ZeroOp_all - operation in FalseValue
16:08:30.155 Passed test: _Sve_ro::JIT.HardwareIntrinsics.Arm._Sve.Program.Sve_CreateBreakPropagateMask_int()