From fdc440099505a45f7ca40061324ba9946f4318f3 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 8 Feb 2021 09:09:23 -0800 Subject: [PATCH 1/3] Fix indentation --- src/main/resources/testchipip/csrc/SimDRAM.cc | 2 +- src/main/resources/testchipip/vsrc/SimDRAM.v | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/resources/testchipip/csrc/SimDRAM.cc b/src/main/resources/testchipip/csrc/SimDRAM.cc index e38fffcb..c3f00491 100644 --- a/src/main/resources/testchipip/csrc/SimDRAM.cc +++ b/src/main/resources/testchipip/csrc/SimDRAM.cc @@ -15,7 +15,7 @@ extern "C" void *memory_init( long long int word_size, long long int line_size, long long int id_bits, - long long int clock_hz + long long int clock_hz ) { mm_t *mm; diff --git a/src/main/resources/testchipip/vsrc/SimDRAM.v b/src/main/resources/testchipip/vsrc/SimDRAM.v index f8eb133b..2a4dcf5e 100644 --- a/src/main/resources/testchipip/vsrc/SimDRAM.v +++ b/src/main/resources/testchipip/vsrc/SimDRAM.v @@ -51,7 +51,7 @@ module SimDRAM #( MEM_SIZE = 1000 * 1000 * 1000, LINE_SIZE = 64, WORD_SIZE = DATA_BITS/8, - CLOCK_HZ = 100000, + CLOCK_HZ = 100000, STRB_BITS=DATA_BITS/8)( input clock, input reset, From 5c853afe24c216dd805f71fe58b51590c2fb7ae1 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 8 Feb 2021 09:10:08 -0800 Subject: [PATCH 2/3] Bump Chipyard.hash --- CHIPYARD.hash | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CHIPYARD.hash b/CHIPYARD.hash index 7c244581..43fe5650 100644 --- a/CHIPYARD.hash +++ b/CHIPYARD.hash @@ -1 +1 @@ -6b0d57d60690cc223013ea228b687b519b716c50 +235b1e5dfd33b4a980a80463aec72ea0bd7a8648 \ No newline at end of file From 7812138db1950c8fbdf45baccbcbb4a4cf6eceb1 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Wed, 10 Feb 2021 12:23:32 -0800 Subject: [PATCH 3/3] Make ClockMutexMux respect depth parameter --- src/main/scala/ClockUtil.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/ClockUtil.scala b/src/main/scala/ClockUtil.scala index 7435554d..d002894a 100644 --- a/src/main/scala/ClockUtil.scala +++ b/src/main/scala/ClockUtil.scala @@ -90,7 +90,7 @@ class ClockMutexMux(val n: Int, depth: Int, genClockGate: () => ClockGate) exten val andClocks = io.clocksIn.map(x => ClockSignalNor2(ClockInverter(x), io.resetAsync)) - val syncs = andClocks.map { c => withClockAndReset(c, io.resetAsync) { Module(new AsyncResetSynchronizerShiftReg(1, 3, 0)) } } + val syncs = andClocks.map { c => withClockAndReset(c, io.resetAsync) { Module(new AsyncResetSynchronizerShiftReg(1, sync = depth, init = 0)) } } val gaters = andClocks.map { c => val g = Module(genClockGate()) g.io.in := c