From 3973048eab18e78d8b2611a8c3f6d0556819af27 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Thu, 5 Nov 2020 16:30:53 +0000 Subject: [PATCH 1/9] Change the SBT assembly merge strategy so that: * only specifically identified artifacts use non-default strategies * fallthrough uses default strategies (that will error) * adds a custom strategy that prefers a non-rocketchip artifact (notRocketMergeStrategy) * needed for chipard/generators/utilities/src/main/resources/csrc/emulator.cc so that the ChipYard version is used instead of the one from RC * adds (useRocketMergeStrategy) that prefers the RC artifact * we want to use vsrc/SimDTM.v from rocketchip, not riscv-sodor Needed for firesim/firesim#651 --- build.sbt | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 62 insertions(+), 3 deletions(-) diff --git a/build.sbt b/build.sbt index f44eeb66b8..d66a542e5b 100644 --- a/build.sbt +++ b/build.sbt @@ -4,14 +4,73 @@ import Tests._ // implicit one lazy val chipyardRoot = Project("chipyardRoot", file(".")) +def filenames(tempDir: File, fs: Seq[File]): Seq[String] = +for(f <- fs) yield { + sbtassembly.AssemblyUtils.sourceOfFileForMerge(tempDir, f) match { + case (path, base, subDirPath, false) => subDirPath + case (jar, base, subJarPath, true) => jar + ":" + subJarPath + } +} + +// custom sbtassemblly.MergeStrategy +// removes merge candidates that have 'rocketchip' in the name of their JAR +// hopefully leaving only a single candidate to be chosen as the member of +// our assembly JAR. If there's still multiple candidates, error. +val notRocketMergeStrategy = new sbtassembly.MergeStrategy { + val name = "notRocket" + def apply(tempDir: File, path: String, files: Seq[File]) = { + val filtered = files collect { f => + sbtassembly.AssemblyUtils.sourceOfFileForMerge(tempDir, f) match { + case (jar, _, _, true) if !jar.toString.contains("rocketchip") => f + } + } + if (filtered.size == 1) Right(Seq(filtered.head -> path)) + else Left("still have multiple files after removing rocketchip for same target path:" + + filenames(tempDir, filtered).mkString("\n", "\n", "") + ) + } +} + +// custom sbtassemblly.MergeStrategy +// keeps merge candidates that have 'rocketchip' in the name of their JAR +// hopefully leaving only a single candidate to be chosen as the member of +// our assembly JAR. If there's still multiple candidates, error. +val useRocketMergeStrategy = new sbtassembly.MergeStrategy { + val name = "useRocket" + def apply(tempDir: File, path: String, files: Seq[File]) = { + val filtered = files collect { f => + sbtassembly.AssemblyUtils.sourceOfFileForMerge(tempDir, f) match { + case (jar, _, _, true) if jar.toString.contains("rocketchip") => f + } + } + if (filtered.size == 1) Right(Seq(filtered.head -> path)) + else Left("multiple candidates have rocketchip in their jar name for target:" + + filenames(tempDir, filtered).mkString("\n", "\n", "") + ) + } +} + lazy val commonSettings = Seq( organization := "edu.berkeley.cs", version := "1.3", scalaVersion := "2.12.10", test in assembly := {}, - assemblyMergeStrategy in assembly := { _ match { - case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard - case _ => MergeStrategy.first}}, + assemblyMergeStrategy in assembly := { + case PathList("META-INF", "services", xs @ _*) => MergeStrategy.concat + // Discard Metadata, it's irrelevant + case PathList("META-INF", xs @ _*) => MergeStrategy.discard + // When any of our dependencies are different versions than those of firrtl.jar, there will be conflicts + // When this occurs, pick last one which is stuff in .ivy2 (ie. not firrtl.jar) + case PathList(xs @ _*) if xs.last.endsWith(".class") || xs.last.endsWith(".properties") => MergeStrategy.last + // Just take the last matching joda/time/tz/data resource files + case PathList("org", "joda", "time", "tz", "data", xs @ _*) => MergeStrategy.last + // Use the file that doesn't come from rocketchip because we've overridden it + case PathList(xs @ _*) if xs.last.equals("emulator.cc") => notRocketMergeStrategy + case PathList("vsrc", "SimDTM.v") => useRocketMergeStrategy + case x => + val oldStrategy = (assemblyMergeStrategy in assembly).value + oldStrategy(x) + }, scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"), addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.1" cross CrossVersion.full), unmanagedBase := (chipyardRoot / unmanagedBase).value, From e8c03d021aec799acd582f543712e37a42994282 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Tue, 10 Nov 2020 22:00:03 +0000 Subject: [PATCH 2/9] Use new RC TargetDirKey to source bootrom files from --td --- .../src/main/scala/ConfigFragments.scala | 3 ++- .../firechip/src/main/scala/TargetConfigs.scala | 16 +--------------- .../utilities/src/main/scala/Simulator.scala | 12 ++++++------ 3 files changed, 9 insertions(+), 22 deletions(-) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index a36285ebeb..a887bc1c6d 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -15,6 +15,7 @@ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams import freechips.rocketchip.tilelink.{HasTLBusParams} import freechips.rocketchip.util.{AsyncResetReg, Symmetric} import freechips.rocketchip.prci._ +import freechips.rocketchip.stage.phases.TargetDirKey import testchipip._ import tracegen.{TraceGenSystem} @@ -36,7 +37,7 @@ import chipyard._ // ----------------------- class WithBootROM extends Config((site, here, up) => { - case BootROMLocated(x) => up(BootROMLocated(x), site).map(_.copy(contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img")) + case BootROMLocated(x) => up(BootROMLocated(x), site).map(_.copy(contentFileName = s"${site(TargetDirKey)}/bootrom.rv${site(XLen)}.img")) }) // DOC include start: gpio config fragment diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 43fea874a9..9c2110c16e 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -4,6 +4,7 @@ import java.io.File import chisel3._ import chisel3.util.{log2Up} +import chipyard.config.WithBootROM import freechips.rocketchip.config.{Parameters, Config} import freechips.rocketchip.groundtest.TraceGenParams import freechips.rocketchip.tile._ @@ -23,19 +24,6 @@ import testchipip.WithRingSystemBus import firesim.bridges._ import firesim.configs._ -class WithBootROM extends Config((site, here, up) => { - case BootROMLocated(x) => { - val chipyardBootROM = new File(s"./generators/testchipip/bootrom/bootrom.rv${site(XLen)}.img") - val firesimBootROM = new File(s"./target-rtl/chipyard/generators/testchipip/bootrom/bootrom.rv${site(XLen)}.img") - - val bootROMPath = if (chipyardBootROM.exists()) { - chipyardBootROM.getAbsolutePath() - } else { - firesimBootROM.getAbsolutePath() - } - up(BootROMLocated(x), site).map(_.copy(contentFileName = bootROMPath)) - } -}) // Disables clock-gating; doesn't play nice with our FAME-1 pass class WithoutClockGating extends Config((site, here, up) => { @@ -65,8 +53,6 @@ class WithFireSimDesignTweaks extends Config( new WithDefaultMemModel ++ // Required*: Uses FireSim ClockBridge and PeekPokeBridge to drive the system with a single clock/reset new WithFireSimSimpleClocks ++ - // Required*: When using FireSim-as-top to provide a correct path to the target bootrom source - new WithBootROM ++ // Required: Existing FAME-1 transform cannot handle black-box clock gates new WithoutClockGating ++ // Required*: Removes thousands of assertions that would be synthesized (* pending PriorityMux bugfix) diff --git a/generators/utilities/src/main/scala/Simulator.scala b/generators/utilities/src/main/scala/Simulator.scala index fa157a3652..26fb87445a 100644 --- a/generators/utilities/src/main/scala/Simulator.scala +++ b/generators/utilities/src/main/scala/Simulator.scala @@ -122,15 +122,15 @@ object GenerateSimFiles extends App with HasGenerateSimConfig { case None => Seq() }) - def writeBootrom(): Unit = { - firrtl.FileUtils.makeDirectory("./bootrom/") - writeResource("/testchipip/bootrom/bootrom.rv64.img", "./bootrom/") - writeResource("/testchipip/bootrom/bootrom.rv32.img", "./bootrom/") - writeResource("/bootrom/bootrom.img", "./bootrom/") + def writeBootrom(cfg: GenerateSimConfig): Unit = { + firrtl.FileUtils.makeDirectory(cfg.targetDir) + writeResource("/testchipip/bootrom/bootrom.rv64.img", cfg.targetDir) + writeResource("/testchipip/bootrom/bootrom.rv32.img", cfg.targetDir) + writeResource("/bootrom/bootrom.img", cfg.targetDir) } def writeFiles(cfg: GenerateSimConfig): Unit = { - writeBootrom() + writeBootrom(cfg) firrtl.FileUtils.makeDirectory(cfg.targetDir) val files = resources(cfg.simulator).map { writeResource(_, cfg.targetDir) } writeDotF(files.map(addOption(_, cfg)), cfg) From 20180c34190823d1d876a9ba6fbe36e1f5e197f3 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 30 Apr 2021 12:12:37 +0000 Subject: [PATCH 3/9] quiet warning about not finding fd common.mk looks for fd but falls back to a slower option using find. when it isn't found, don't print that it isn't found to the output because it is okay for it not to be found. --- common.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common.mk b/common.mk index 89e998bdaf..c18e332727 100644 --- a/common.mk +++ b/common.mk @@ -60,7 +60,7 @@ include $(base_dir)/tools/dromajo/dromajo.mk ######################################################################################### # Returns a list of files in directory $1 with file extension $2. # If available, use 'fd' to find the list of files, which is faster than 'find'. -ifeq ($(shell which fd),) +ifeq ($(shell which fd 2>/dev/null),) lookup_srcs = $(shell find -L $(1)/ -name target -prune -o -iname "*.$(2)" -print 2> /dev/null) else lookup_srcs = $(shell fd -L ".*\.$(2)" $(1)) From a13c59419dbecf71b4e9cec284eddf92c687f557 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 30 Apr 2021 14:44:47 +0000 Subject: [PATCH 4/9] chipyard variables.mk needs to know run_main too for FireSim chipyard as top, it gets run_scala_main and run_main from chipyard's variables.mk --- variables.mk | 1 + 1 file changed, 1 insertion(+) diff --git a/variables.mk b/variables.mk index 2843e53e54..60dd29259e 100644 --- a/variables.mk +++ b/variables.mk @@ -170,6 +170,7 @@ SBT_NON_THIN ?= $(subst $(SBT_CLIENT_FLAG),,$(SBT)) define run_scala_main cd $(base_dir) && $(SBT) ";project $(1); runMain $(2) $(3)" endef +run_main = cd $(base_dir) && java $(JAVA_ARGS) -cp $(FAT_JAR) $(2) $(3) FIRRTL_LOGLEVEL ?= error From 7f6096fe8975012e62a7cc22ef133117536a458f Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 30 Apr 2021 14:48:53 +0000 Subject: [PATCH 5/9] add message to assertion in Generator --legacy-configs option It was confusing when I hit it. A little help without having to go sift through the scala to find the assertion goes a long way. --- .../chipyard/src/main/scala/stage/ChipyardAnnotations.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala b/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala index b130003177..6169d1bd6c 100644 --- a/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala +++ b/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala @@ -13,7 +13,7 @@ private[stage] object UnderscoreDelimitedConfigsAnnotation extends HasShellOptio longOption = "legacy-configs", toAnnotationSeq = a => { val split = a.split(':') - assert(split.length == 2) + assert(split.length == 2, s"'${a}' split by ':' doesn't yield two things") val packageName = split.head val configs = split.last.split("_") Seq(new ConfigsAnnotation(configs map { config => if (config contains ".") s"${config}" else s"${packageName}.${config}" } )) From ad8fedb0265daad354b6c63fd6055b4dc877cb8c Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 30 Apr 2021 21:33:55 +0000 Subject: [PATCH 6/9] prefix $(info) with # so that it doesn't break FireSim gen-replace-rtl-script --- common.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common.mk b/common.mk index c18e332727..bdef7cc004 100644 --- a/common.mk +++ b/common.mk @@ -6,7 +6,7 @@ SHELL=/bin/bash ifndef RISCV $(error RISCV is unset. You must set RISCV yourself, or through the Chipyard auto-generated env file) else -$(info Running with RISCV=$(RISCV)) +$(info #Running with RISCV=$(RISCV)) endif ######################################################################################### From be498d4d8e04c06c260cc37bf36c3134f72b1c02 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Tue, 4 May 2021 14:14:16 +0000 Subject: [PATCH 7/9] rm bootrom dir from .gitignore Requested in https://github.com/ucb-bar/chipyard/pull/872/files#r625522168 --- .gitignore | 1 - 1 file changed, 1 deletion(-) diff --git a/.gitignore b/.gitignore index 257d2c581d..bd20c39e17 100644 --- a/.gitignore +++ b/.gitignore @@ -1,4 +1,3 @@ -bootrom/* docs/warnings.txt /Makefrag.pkgs target From 090eb1aeb6ad098dd63b19b842004b968f6cc108 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Tue, 4 May 2021 14:18:34 +0000 Subject: [PATCH 8/9] remove run_main from variables.mk not needed in Chipyard, only FireSim --- variables.mk | 1 - 1 file changed, 1 deletion(-) diff --git a/variables.mk b/variables.mk index 60dd29259e..2843e53e54 100644 --- a/variables.mk +++ b/variables.mk @@ -170,7 +170,6 @@ SBT_NON_THIN ?= $(subst $(SBT_CLIENT_FLAG),,$(SBT)) define run_scala_main cd $(base_dir) && $(SBT) ";project $(1); runMain $(2) $(3)" endef -run_main = cd $(base_dir) && java $(JAVA_ARGS) -cp $(FAT_JAR) $(2) $(3) FIRRTL_LOGLEVEL ?= error From dafacf630d5047a6b3257dca560b9c37da6195e7 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Wed, 5 May 2021 23:58:44 +0000 Subject: [PATCH 9/9] bump firesim to latest dev + firesim/firesim#651 --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 72a52523e1..ec22bba70e 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 72a52523e18443d9ef9a1e2664cbc71a45fc0c57 +Subproject commit ec22bba70eea3e84a2ca924dc72463ca3976ef58