From c061ea0ac971a5cba7da6023b65e74f48f589580 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 30 Mar 2021 01:45:34 -0700 Subject: [PATCH 1/2] Bump testchipip | Add custom boot pin --- generators/chipyard/src/main/scala/DigitalTop.scala | 2 ++ generators/chipyard/src/main/scala/HarnessBinders.scala | 6 ++++++ generators/chipyard/src/main/scala/IOBinders.scala | 7 +++++++ .../chipyard/src/main/scala/config/AbstractConfig.scala | 2 ++ generators/testchipip | 2 +- 5 files changed, 18 insertions(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index 7fd682d2b8..3407b4da2d 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -13,6 +13,8 @@ import freechips.rocketchip.devices.tilelink._ // DOC include start: DigitalTop class DigitalTop(implicit p: Parameters) extends ChipyardSystem + with testchipip.CanHavePeripheryCustomBootPin // Enables optional custom boot pin + with testchipip.HasPeripheryBootAddrReg // Use programmable boot address register with testchipip.CanHaveTraceIO // Enables optionally adding trace IO with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala index da497a54a8..c1ec2bdafb 100644 --- a/generators/chipyard/src/main/scala/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/HarnessBinders.scala @@ -321,3 +321,9 @@ class WithSimDromajoBridge extends ComposeHarnessBinder({ ports.map { p => p.traces.map(tileTrace => SimDromajoBridge(tileTrace)(system.p)) } } }) + +class WithTieOffCustomBootPin extends OverrideHarnessBinder({ + (system: CanHavePeripheryCustomBootPin, th: HasHarnessSignalReferences, ports: Seq[Bool]) => { + ports.foreach(_ := false.B) + } +}) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 5d15383480..dd74e960f8 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -372,6 +372,13 @@ class WithTraceIOPunchthrough extends OverrideIOBinder({ } }) +class WithCustomBootPin extends OverrideIOBinder({ + (system: CanHavePeripheryCustomBootPin) => system.custom_boot_pin.map({ p => + val sys = system.asInstanceOf[BaseSubsystem] + val (port, cells) = IOCell.generateIOFromSignal(p.getWrappedValue, "custom_boot", sys.p(IOCellKey), abstractResetAsAsync = true) + (Seq(port), cells) + }).getOrElse((Nil, Nil)) +}) class WithDontTouchPorts extends OverrideIOBinder({ (system: DontTouch) => system.dontTouchPorts(); (Nil, Nil) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index da84bd0501..6660d159ec 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -21,6 +21,7 @@ class AbstractConfig extends Config( new chipyard.harness.WithSimAXIMMIO ++ // add SimAXIMem for axi4 mmio port, if enabled new chipyard.harness.WithTieOffInterrupts ++ // tie-off interrupt ports, if present new chipyard.harness.WithTieOffL2FBusAXI ++ // tie-off external AXI4 master, if present + new chipyard.harness.WithTieOffCustomBootPin ++ // The IOBinders instantiate ChipTop IOs to match desired digital IOs // IOCells are generated for "Chip-like" IOs, while simulation-only IOs are directly punched through @@ -37,6 +38,7 @@ class AbstractConfig extends Config( new chipyard.iobinders.WithSPIIOCells ++ new chipyard.iobinders.WithTraceIOPunchthrough ++ new chipyard.iobinders.WithExtInterruptIOCells ++ + new chipyard.iobinders.WithCustomBootPin ++ new testchipip.WithDefaultSerialTL ++ // use serialized tilelink port to external serialadapter/harnessRAM new chipyard.config.WithBootROM ++ // use default bootrom diff --git a/generators/testchipip b/generators/testchipip index fd7760e286..a973fdd67f 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit fd7760e2862661bf6277acfeeb42644797e876d0 +Subproject commit a973fdd67f650555fdf64e2d904eba9a0af691a3 From 709c6bb36573c350a90568d1102ae9879ab23019 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 31 Mar 2021 09:19:29 -0700 Subject: [PATCH 2/2] Bump testchipip --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index a973fdd67f..c50a0e2e32 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit a973fdd67f650555fdf64e2d904eba9a0af691a3 +Subproject commit c50a0e2e32d71f4f956c8a616a5ec2f7e31792fb