From 6a42c64d3ab84d96d8577f0c109661640152d167 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 12 May 2023 14:06:44 -0700 Subject: [PATCH 1/9] Bump to latest rocket-chip --- fpga/fpga-shells | 2 +- generators/boom | 2 +- .../chipyard/src/main/scala/Cospike.scala | 19 ++++++++++--------- .../chipyard/src/main/scala/SpikeTile.scala | 1 + .../main/scala/clocking/ClockBinders.scala | 6 +++--- .../main/scala/clocking/TileClockGater.scala | 2 +- .../main/scala/clocking/TileResetSetter.scala | 2 +- .../src/main/scala/example/FlatChipTop.scala | 8 ++++---- .../chipyard/src/main/scala/example/GCD.scala | 6 +++--- .../src/main/scala/example/InitZero.scala | 2 +- .../src/main/scala/example/TutorialTile.scala | 1 + .../scala/example/dsptools/GenericFIR.scala | 2 +- .../dsptools/StreamingPassthrough.scala | 2 +- generators/cva6 | 2 +- generators/fft-generator | 2 +- generators/ibex | 2 +- generators/icenet | 2 +- generators/nvdla | 2 +- generators/riscv-sodor | 2 +- generators/rocket-chip | 2 +- generators/sha3 | 2 +- generators/testchipip | 2 +- sims/firesim | 2 +- 23 files changed, 39 insertions(+), 36 deletions(-) diff --git a/fpga/fpga-shells b/fpga/fpga-shells index 9f4c6ac571..d650f81c07 160000 --- a/fpga/fpga-shells +++ b/fpga/fpga-shells @@ -1 +1 @@ -Subproject commit 9f4c6ac5719b03ded61022dc3767e750872d0535 +Subproject commit d650f81c0728f3108719d37396c2a651a7463520 diff --git a/generators/boom b/generators/boom index 679f358755..f732ceb602 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 679f358755c57524f18cf46b72fc3fc1ac67f127 +Subproject commit f732ceb602bcccd4adb6a5f7137c7c0bea08be9d diff --git a/generators/chipyard/src/main/scala/Cospike.scala b/generators/chipyard/src/main/scala/Cospike.scala index cee2341336..de04b032f4 100644 --- a/generators/chipyard/src/main/scala/Cospike.scala +++ b/generators/chipyard/src/main/scala/Cospike.scala @@ -72,17 +72,18 @@ object SpikeCosim }) cosim.io.hartid := hartid.U for (i <- 0 until trace.numInsns) { - cosim.io.trace(i).valid := trace.insns(i).valid + val insn = trace.trace.insns(i) + cosim.io.trace(i).valid := insn.valid val signed = Wire(SInt(64.W)) - signed := trace.insns(i).iaddr.asSInt + signed := insn.iaddr.asSInt cosim.io.trace(i).iaddr := signed.asUInt - cosim.io.trace(i).insn := trace.insns(i).insn - cosim.io.trace(i).exception := trace.insns(i).exception - cosim.io.trace(i).interrupt := trace.insns(i).interrupt - cosim.io.trace(i).cause := trace.insns(i).cause - cosim.io.trace(i).has_wdata := trace.insns(i).wdata.isDefined.B - cosim.io.trace(i).wdata := trace.insns(i).wdata.getOrElse(0.U) - cosim.io.trace(i).priv := trace.insns(i).priv + cosim.io.trace(i).insn := insn.insn + cosim.io.trace(i).exception := insn.exception + cosim.io.trace(i).interrupt := insn.interrupt + cosim.io.trace(i).cause := insn.cause + cosim.io.trace(i).has_wdata := insn.wdata.isDefined.B + cosim.io.trace(i).wdata := insn.wdata.getOrElse(0.U) + cosim.io.trace(i).priv := insn.priv } } } diff --git a/generators/chipyard/src/main/scala/SpikeTile.scala b/generators/chipyard/src/main/scala/SpikeTile.scala index c6ec13aea8..fc822c2272 100644 --- a/generators/chipyard/src/main/scala/SpikeTile.scala +++ b/generators/chipyard/src/main/scala/SpikeTile.scala @@ -62,6 +62,7 @@ case class SpikeCoreParams() extends CoreParams { val useBitManipCrypto = false val useCryptoNIST = false val useCryptoSM = false + val useConditionalZero = false override def vLen = 128 override def vMemDataBits = 128 diff --git a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala index 5618f58271..2ecef30c35 100644 --- a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala +++ b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala @@ -38,9 +38,9 @@ class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({ val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes)) } val pllCtrl = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl (baseAddress + 0x40000, tlbus.beatBytes)) } - tlbus.toVariableWidthSlave(Some("clock-div-ctrl")) { clockDivider.tlNode := TLBuffer() } - tlbus.toVariableWidthSlave(Some("clock-sel-ctrl")) { clockSelector.tlNode := TLBuffer() } - tlbus.toVariableWidthSlave(Some("pll-ctrl")) { pllCtrl.tlNode := TLBuffer() } + tlbus.coupleTo("clock-div-ctrl") { clockDivider.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ } + tlbus.coupleTo("clock-sel-ctrl") { clockSelector.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ } + tlbus.coupleTo("pll-ctrl") { pllCtrl.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ } system.allClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode diff --git a/generators/chipyard/src/main/scala/clocking/TileClockGater.scala b/generators/chipyard/src/main/scala/clocking/TileClockGater.scala index 23d525a65d..0c4e8b1194 100644 --- a/generators/chipyard/src/main/scala/clocking/TileClockGater.scala +++ b/generators/chipyard/src/main/scala/clocking/TileClockGater.scala @@ -49,7 +49,7 @@ class TileClockGater(address: BigInt, beatBytes: Int)(implicit p: Parameters, va object TileClockGater { def apply(address: BigInt, tlbus: TLBusWrapper)(implicit p: Parameters, v: ValName) = { val gater = LazyModule(new TileClockGater(address, tlbus.beatBytes)) - tlbus.toVariableWidthSlave(Some("clock-gater")) { gater.tlNode := TLBuffer() } + tlbus.coupleTo("clock-gater") { gater.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ } gater.clockNode } } diff --git a/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala b/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala index 9ea4bfd5bc..60bfe34379 100644 --- a/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala +++ b/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala @@ -67,7 +67,7 @@ class TileResetSetter(address: BigInt, beatBytes: Int, tileNames: Seq[String], i object TileResetSetter { def apply(address: BigInt, tlbus: TLBusWrapper, tileNames: Seq[String], initResetHarts: Seq[Int])(implicit p: Parameters, v: ValName) = { val setter = LazyModule(new TileResetSetter(address, tlbus.beatBytes, tileNames, initResetHarts)) - tlbus.toVariableWidthSlave(Some("tile-reset-setter")) { setter.tlNode := TLBuffer() } + tlbus.coupleTo("tile-reset-setter") { setter.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ } setter.clockNode } } diff --git a/generators/chipyard/src/main/scala/example/FlatChipTop.scala b/generators/chipyard/src/main/scala/example/FlatChipTop.scala index c10baab454..b960251d94 100644 --- a/generators/chipyard/src/main/scala/example/FlatChipTop.scala +++ b/generators/chipyard/src/main/scala/example/FlatChipTop.scala @@ -7,7 +7,7 @@ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.prci._ import freechips.rocketchip.util._ import freechips.rocketchip.devices.debug.{ExportDebug, JtagDTMKey, Debug} -import freechips.rocketchip.tilelink.{TLBuffer} +import freechips.rocketchip.tilelink.{TLBuffer, TLFragmenter} import chipyard.{BuildSystem, DigitalTop} import chipyard.clocking._ import chipyard.iobinders.{IOCellKey, JTAGChipIO} @@ -33,9 +33,9 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule { val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes)) } val pllCtrl = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl (baseAddress + 0x40000, tlbus.beatBytes)) } - tlbus.toVariableWidthSlave(Some("clock-div-ctrl")) { clockDivider.tlNode := TLBuffer() } - tlbus.toVariableWidthSlave(Some("clock-sel-ctrl")) { clockSelector.tlNode := TLBuffer() } - tlbus.toVariableWidthSlave(Some("pll-ctrl")) { pllCtrl.tlNode := TLBuffer() } + tlbus.coupleTo("clock-div-ctrl") { clockDivider.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ } + tlbus.coupleTo("clock-sel-ctrl") { clockSelector.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ } + tlbus.coupleTo("pll-ctrl") { pllCtrl.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ } system.allClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode diff --git a/generators/chipyard/src/main/scala/example/GCD.scala b/generators/chipyard/src/main/scala/example/GCD.scala index bf05ba9c9e..5e6c5d67cd 100644 --- a/generators/chipyard/src/main/scala/example/GCD.scala +++ b/generators/chipyard/src/main/scala/example/GCD.scala @@ -165,17 +165,17 @@ trait CanHavePeripheryGCD { this: BaseSubsystem => case Some(params) => { if (params.useAXI4) { val gcd = LazyModule(new GCDAXI4(params, pbus.beatBytes)(p)) - pbus.toSlave(Some(portName)) { + pbus.coupleTo(portName) { gcd.node := AXI4Buffer () := TLToAXI4 () := // toVariableWidthSlave doesn't use holdFirstDeny, which TLToAXI4() needsx - TLFragmenter(pbus.beatBytes, pbus.blockBytes, holdFirstDeny = true) + TLFragmenter(pbus.beatBytes, pbus.blockBytes, holdFirstDeny = true) := _ } Some(gcd) } else { val gcd = LazyModule(new GCDTL(params, pbus.beatBytes)(p)) - pbus.toVariableWidthSlave(Some(portName)) { gcd.node } + pbus.coupleTo(portName) { gcd.node := TLFragmenter(pbus.beatBytes, pbus.blockBytes) := _ } Some(gcd) } } diff --git a/generators/chipyard/src/main/scala/example/InitZero.scala b/generators/chipyard/src/main/scala/example/InitZero.scala index bb6ecd72a7..78237eca77 100644 --- a/generators/chipyard/src/main/scala/example/InitZero.scala +++ b/generators/chipyard/src/main/scala/example/InitZero.scala @@ -62,7 +62,7 @@ trait CanHavePeripheryInitZero { this: BaseSubsystem => p(InitZeroKey) .map { k => val initZero = LazyModule(new InitZero()(p)) - fbus.fromPort(Some("init-zero"))() := initZero.node + fbus.coupleFrom("init-zero") { _ := initZero.node } } } diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala index 1a9114b9b4..38c8577ad6 100644 --- a/generators/chipyard/src/main/scala/example/TutorialTile.scala +++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala @@ -67,6 +67,7 @@ case class MyCoreParams( val useCryptoNIST: Boolean = false val useCryptoSM: Boolean = false val traceHasWdata: Boolean = false + val useConditionalZero = false } // DOC include start: CanAttachTile diff --git a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala index 15dfb99246..3e315e654c 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala @@ -203,7 +203,7 @@ trait CanHavePeripheryStreamingFIR extends BaseSubsystem { genOut = FixedPoint(8.W, 3.BP), coeffs = Seq(1.F(0.BP), 2.F(0.BP), 3.F(0.BP)), params = params)) - pbus.toVariableWidthSlave(Some("streamingFIR")) { streamingFIR.mem.get := TLFIFOFixer() } + pbus.coupleTo("streamingFIR") { streamingFIR.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes) := _ } Some(streamingFIR) } case None => None diff --git a/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala index 2846277cc9..45e05fc253 100644 --- a/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala +++ b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala @@ -132,7 +132,7 @@ trait CanHavePeripheryStreamingPassthrough { this: BaseSubsystem => val passthrough = p(StreamingPassthroughKey) match { case Some(params) => { val streamingPassthroughChain = LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W))) - pbus.toVariableWidthSlave(Some("streamingPassthrough")) { streamingPassthroughChain.mem.get := TLFIFOFixer() } + pbus.coupleTo("streamingPassthrough") { streamingPassthroughChain.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes) := _ } Some(streamingPassthroughChain) } case None => None diff --git a/generators/cva6 b/generators/cva6 index 0011494bb7..5bb6d6a7ae 160000 --- a/generators/cva6 +++ b/generators/cva6 @@ -1 +1 @@ -Subproject commit 0011494bb70d2327ab4d6b0258f5073f137927ee +Subproject commit 5bb6d6a7ae0a0e17e253996386823a5b540da28c diff --git a/generators/fft-generator b/generators/fft-generator index be8ab768bd..f598d0c359 160000 --- a/generators/fft-generator +++ b/generators/fft-generator @@ -1 +1 @@ -Subproject commit be8ab768bd15824c69531df632478e4429078b94 +Subproject commit f598d0c359c896e7853c8ef01c39ebecdd48b344 diff --git a/generators/ibex b/generators/ibex index 916fb7a6ff..66ec6e56ed 160000 --- a/generators/ibex +++ b/generators/ibex @@ -1 +1 @@ -Subproject commit 916fb7a6ff4a65f989279bcc082676a565beee0c +Subproject commit 66ec6e56ed69df4e4af5383128cf21adf88b08fc diff --git a/generators/icenet b/generators/icenet index ce1ec55c1f..68b4c7f30f 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit ce1ec55c1fd9c4339e7c0eec3a82d86041fa5d20 +Subproject commit 68b4c7f30f0119fe5cfab7ea99fb6927a563e112 diff --git a/generators/nvdla b/generators/nvdla index 7130a5c0f7..730fad4360 160000 --- a/generators/nvdla +++ b/generators/nvdla @@ -1 +1 @@ -Subproject commit 7130a5c0f7016cd177ec9cf908a18edd668660d1 +Subproject commit 730fad4360e67b14b1a4656ac58aaa40cfd4fe6b diff --git a/generators/riscv-sodor b/generators/riscv-sodor index c051956d3b..b1b70b6584 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit c051956d3be3269c4ed9fcbb6afe920a6f54fd32 +Subproject commit b1b70b65848d56a381043a80666afe3d79ef5a67 diff --git a/generators/rocket-chip b/generators/rocket-chip index 25e2c63567..78c43fe7f6 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 25e2c63567689ebe1fc5e60fdfe3375a8dba071c +Subproject commit 78c43fe7f617f9352b05ea32316387778a8a2e19 diff --git a/generators/sha3 b/generators/sha3 index 1fa5ef8ae5..b19b7c76fc 160000 --- a/generators/sha3 +++ b/generators/sha3 @@ -1 +1 @@ -Subproject commit 1fa5ef8ae5b67126d709193896e75dba50c5fd28 +Subproject commit b19b7c76fc865598b6a9806c8ef799064fc496ab diff --git a/generators/testchipip b/generators/testchipip index 518a36afc9..06e3492610 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 518a36afc9b1a64d7007689824a258affd4daef3 +Subproject commit 06e3492610499dd9a6473466273383ea234ae517 diff --git a/sims/firesim b/sims/firesim index 966e09907c..b000772990 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 966e09907cde52f0ce68eb654bf6020b5b97a6c3 +Subproject commit b0007729905bb3be4125440924ecc97bed9ecf88 From 300a4b364227d9720c902e9c2b0aebd88833d4d9 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 17 May 2023 17:08:47 -0700 Subject: [PATCH 2/9] Add rocketchip unit-tests to regressions --- .github/scripts/defaults.sh | 6 +++- .github/scripts/run-tests.sh | 22 +++++++++++-- .github/workflows/chipyard-run-tests.yml | 39 ++++++++++++++++++++++++ generators/rocket-chip | 2 +- variables.mk | 14 ++++++++- 5 files changed, 77 insertions(+), 6 deletions(-) diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh index d9dd5f968c..1f0310fed5 100755 --- a/.github/scripts/defaults.sh +++ b/.github/scripts/defaults.sh @@ -33,7 +33,7 @@ grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboom chipyard-spif grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels" grouping["group-constellation"]="chipyard-constellation" grouping["group-tracegen"]="tracegen tracegen-boom" -grouping["group-other"]="icenet testchipip constellation" +grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar" grouping["group-fpga"]="arty vcu118 vc707" # key value store to get the build strings @@ -69,6 +69,10 @@ mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests" mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests" mapping["icenet"]="SUB_PROJECT=icenet" mapping["testchipip"]="SUB_PROJECT=testchipip" +mapping["rocketchip-amba"]="SUB_PROJECT=rocketchip CONFIG=AMBAUnitTestConfig" +mapping["rocketchip-tlsimple"]="SUB_PROJECT=rocketchip CONFIG=TLSimpleUnitTestConfig" +mapping["rocketchip-tlwidth"]="SUB_PROJECT=rocketchip CONFIG=TLWidthUnitTestConfig" +mapping["rocketchip-tlxbar"]="SUB_PROJECT=rocketchip CONFIG=TLXbarUnitTestConfig" mapping["arty"]="SUB_PROJECT=arty verilog" mapping["vcu118"]="SUB_PROJECT=vcu118 verilog" diff --git a/.github/scripts/run-tests.sh b/.github/scripts/run-tests.sh index 5ed6aab4cd..798bad0d60 100755 --- a/.github/scripts/run-tests.sh +++ b/.github/scripts/run-tests.sh @@ -28,6 +28,10 @@ run_tracegen () { make tracegen -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ $@ } +run_none () { + make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ run-binary-fast BINARY=none $@ +} + case $1 in chipyard-rocket) run_bmark ${mapping[$1]} @@ -123,13 +127,25 @@ case $1 in make run-binary-hex BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} ;; icenet) - make run-binary-fast BINARY=none -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} + run_none ${mapping[$1]} ;; testchipip) - make run-binary-fast BINARY=none -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} + run_none ${mapping[$1]} ;; constellation) - make run-binary-fast BINARY=none -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} + run_none ${mapping[$1]} + ;; + rocketchip-amba) + run_none ${mapping[$1]} + ;; + rocketchip-tlsimple) + run_none ${mapping[$1]} + ;; + rocketchip-tlwidth) + run_none ${mapping[$1]} + ;; + rocketchip-tlxbar) + run_none ${mapping[$1]} ;; *) echo "No set of tests for $1. Did you spell it right?" diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml index d357637c43..231315be82 100644 --- a/.github/workflows/chipyard-run-tests.yml +++ b/.github/workflows/chipyard-run-tests.yml @@ -857,6 +857,44 @@ jobs: group-key: "group-other" project-key: "testchipip" + rocketchip-run-tests: + name: rocketchip-run-tests + needs: prepare-chipyard-other + runs-on: self-hosted + steps: + - name: Delete old checkout + run: | + ls -alh . + rm -rf ${{ github.workspace }}/* || true + rm -rf ${{ github.workspace }}/.* || true + ls -alh . + - name: Checkout + uses: actions/checkout@v3 + - name: Git workaround + uses: ./.github/actions/git-workaround + - name: Create conda env + uses: ./.github/actions/create-conda-env + - name: Run amba tests + uses: ./.github/actions/run-tests + with: + group-key: "group-other" + project-key: "rocketchip-amba" + - name: Run tlsimple tests + uses: ./.github/actions/run-tests + with: + group-key: "group-other" + project-key: "rocketchip-tlsimple" + - name: Run tlwidth tests + uses: ./.github/actions/run-tests + with: + group-key: "group-other" + project-key: "rocketchip-tlwidth" + - name: Run tlxbar tests + uses: ./.github/actions/run-tests + with: + group-key: "group-other" + project-key: "rocketchip-tlxbar" + constellation-run-tests: name: constellation-run-tests needs: prepare-chipyard-other @@ -980,6 +1018,7 @@ jobs: tracegen-run-tests, icenet-run-tests, testchipip-run-tests, + rocketchip-run-tests, constellation-run-tests, prepare-chipyard-fpga, # firesim-run-tests, fireboom-run-tests] diff --git a/generators/rocket-chip b/generators/rocket-chip index 78c43fe7f6..47f7b71447 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 78c43fe7f617f9352b05ea32316387778a8a2e19 +Subproject commit 47f7b7144727f0340d511d35b9f6c7a91b2a276f diff --git a/variables.mk b/variables.mk index 89e66cd92d..dc4669af12 100644 --- a/variables.mk +++ b/variables.mk @@ -89,7 +89,7 @@ ifeq ($(SUB_PROJECT),hwacha) TB ?= TestDriver TOP ?= ExampleRocketSystem endif -# For TestChipIP developers +# For TestChipIP developers running unit-tests ifeq ($(SUB_PROJECT),testchipip) SBT_PROJECT ?= chipyard MODEL ?= TestHarness @@ -101,6 +101,18 @@ ifeq ($(SUB_PROJECT),testchipip) TB ?= TestDriver TOP ?= UnitTestSuite endif +# For rocketchip developers running unit-tests +ifeq ($(SUB_PROJECT),rocketchip) + SBT_PROJECT ?= chipyard + MODEL ?= TestHarness + VLOG_MODEL ?= $(MODEL) + MODEL_PACKAGE ?= chipyard.unittest + CONFIG ?= TLSimpleUnitTestConfig + CONFIG_PACKAGE ?= freechips.rocketchip.unittest + GENERATOR_PACKAGE ?= chipyard + TB ?= TestDriver + TOP ?= UnitTestSuite +endif # For IceNet developers ifeq ($(SUB_PROJECT),icenet) SBT_PROJECT ?= chipyard From 07ce417caf8094242ef1c468194a40d3e9582a7c Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 24 May 2023 09:54:35 -0700 Subject: [PATCH 3/9] Disable rocketchip TL- tests since the segfault in verilator --- .github/workflows/chipyard-run-tests.yml | 31 ++++++++++++------------ 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml index 231315be82..fecf7976cc 100644 --- a/.github/workflows/chipyard-run-tests.yml +++ b/.github/workflows/chipyard-run-tests.yml @@ -879,21 +879,22 @@ jobs: with: group-key: "group-other" project-key: "rocketchip-amba" - - name: Run tlsimple tests - uses: ./.github/actions/run-tests - with: - group-key: "group-other" - project-key: "rocketchip-tlsimple" - - name: Run tlwidth tests - uses: ./.github/actions/run-tests - with: - group-key: "group-other" - project-key: "rocketchip-tlwidth" - - name: Run tlxbar tests - uses: ./.github/actions/run-tests - with: - group-key: "group-other" - project-key: "rocketchip-tlxbar" + # Below tests segfault with verilator, work fine in VCS + # - name: Run tlsimple tests + # uses: ./.github/actions/run-tests + # with: + # group-key: "group-other" + # project-key: "rocketchip-tlsimple" + # - name: Run tlwidth tests + # uses: ./.github/actions/run-tests + # with: + # group-key: "group-other" + # project-key: "rocketchip-tlwidth" + # - name: Run tlxbar tests + # uses: ./.github/actions/run-tests + # with: + # group-key: "group-other" + # project-key: "rocketchip-tlxbar" constellation-run-tests: name: constellation-run-tests From adcb04636d799791fed1b69aedc92800502c1a2a Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 24 May 2023 22:17:29 -0700 Subject: [PATCH 4/9] Bump cva6 --- generators/cva6 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/cva6 b/generators/cva6 index 5bb6d6a7ae..46323fcd74 160000 --- a/generators/cva6 +++ b/generators/cva6 @@ -1 +1 @@ -Subproject commit 5bb6d6a7ae0a0e17e253996386823a5b540da28c +Subproject commit 46323fcd7407544c751b353f52e356eb8f33e9d1 From de54b18e8dbd827d8ea68b8bacc46d3e0dc795ea Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 25 May 2023 00:29:18 -0700 Subject: [PATCH 5/9] Update repo-clean.sh --- scripts/repo-clean.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/repo-clean.sh b/scripts/repo-clean.sh index 0ecdbb2741..1ad39cae4d 100755 --- a/scripts/repo-clean.sh +++ b/scripts/repo-clean.sh @@ -26,7 +26,7 @@ rm -rf $RDIR/toolchains/esp-tools/riscv-tests/build.log popd ) ( - pushd $RDIR/generators/cva6/src/main/resources/vsrc + pushd $RDIR/generators/cva6/src/main/resources/vsrc/cva6 if [ -d cva6 ] then git submodule deinit -f cva6 From 26a6f62ca75c863ce4573e3a24ee149172078e55 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 25 May 2023 00:43:12 -0700 Subject: [PATCH 6/9] Update repo-clean.sh --- scripts/repo-clean.sh | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/scripts/repo-clean.sh b/scripts/repo-clean.sh index 1ad39cae4d..d6231621c9 100755 --- a/scripts/repo-clean.sh +++ b/scripts/repo-clean.sh @@ -26,10 +26,13 @@ rm -rf $RDIR/toolchains/esp-tools/riscv-tests/build.log popd ) ( - pushd $RDIR/generators/cva6/src/main/resources/vsrc/cva6 - if [ -d cva6 ] + if [ -d $RDIR/generators/cva6/src/main/resources/vsrc/cva6 ] then - git submodule deinit -f cva6 + pushd $RDIR/generators/cva6/src/main/resources/vsrc/cva6 + if [ -d cva6 ] + then + git submodule deinit -f cva6 + fi + popd fi - popd ) From f73951ac7fee7293abae7bc0376dcea9c284f743 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 26 May 2023 11:56:58 -0700 Subject: [PATCH 7/9] Add TestChipConfigTweaks to model 2/1 tile/uncore division --- .../firechip/src/main/scala/TargetConfigs.scala | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index d2f8b994c1..070e3aa913 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -164,6 +164,22 @@ class WithFireSimHighPerfConfigTweaks extends Config( new WithFireSimDesignTweaks ) +// Tweak more representative of testchip configs +class WithFireSimTestChipConfigTweaks extends Config( + // Frequency specifications + new chipyard.config.WithTileFrequency(1000.0) ++ // Realistic tile frequency for a test chip + new chipyard.config.WithSystemBusFrequency(500.0) ++ // Realistic system bus frequency + new chipyard.config.WithMemoryBusFrequency(1000.0) ++ // Needs to be 1000 MHz to model DDR performance accurately + new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Match the sbus and pbus frequency + // Crossing specifications + new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS + new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS + new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore + new boom.common.WithRationalBoomTiles ++ // Add rational crossings between BoomTile and uncore + new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS + new WithFireSimDesignTweaks +) + /******************************************************************************* * Full TARGET_CONFIG configurations. These set parameters of the target being * simulated. From 3f06dbc280982401f23c39b2fd9ab40eae20da98 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 26 May 2023 17:50:55 -0700 Subject: [PATCH 8/9] Fix clock group combiner behavior for rational-tile clocks --- .../src/main/scala/clocking/ClockGroupCombiner.scala | 6 +++--- .../chipyard/src/main/scala/config/AbstractConfig.scala | 2 +- generators/chipyard/src/main/scala/config/ChipConfigs.scala | 2 +- .../chipyard/src/main/scala/config/RocketConfigs.scala | 4 ++-- .../chipyard/src/main/scala/config/TracegenConfigs.scala | 2 +- generators/firechip/src/main/scala/TargetConfigs.scala | 1 + generators/sifive-blocks | 2 +- 7 files changed, 10 insertions(+), 9 deletions(-) diff --git a/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala b/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala index ff6c52e977..e52368049b 100644 --- a/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala +++ b/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala @@ -23,9 +23,9 @@ object ClockGroupCombiner { case object ClockGroupCombinerKey extends Field[Seq[(String, ClockSinkParameters => Boolean)]](Nil) // All clock groups with a name containing any substring in names will be combined into a single clock group -class WithClockGroupsCombinedByName(groups: (String, Seq[String])*) extends Config((site, here, up) => { - case ClockGroupCombinerKey => groups.map { case (grouped_name, matched_names) => - (grouped_name, (m: ClockSinkParameters) => matched_names.map(n => m.name.get.contains(n)).reduce(_||_)) +class WithClockGroupsCombinedByName(groups: (String, Seq[String], Seq[String])*) extends Config((site, here, up) => { + case ClockGroupCombinerKey => groups.map { case (grouped_name, matched_names, unmatched_names) => + (grouped_name, (m: ClockSinkParameters) => matched_names.exists(n => m.name.get.contains(n)) && !unmatched_names.exists(n => m.name.get.contains(n))) } }) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 48f10cd96c..c17f4f1854 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -44,7 +44,7 @@ class AbstractConfig extends Config( // By default, punch out IOs to the Harness new chipyard.clocking.WithPassthroughClockGenerator ++ - new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "implicit"))) ++ + new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "implicit"), Seq("tile"))) ++ new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Default 500 MHz pbus new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Default 500 MHz mbus diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala index 1d717eae65..4d1fbf7216 100644 --- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala @@ -32,7 +32,7 @@ class ChipLikeQuadRocketConfig extends Config( new chipyard.clocking.WithPLLSelectorDividerClockGenerator ++ // Use a PLL-based clock selector/divider generator structure // Create the uncore clock group - new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("implicit", "sbus", "mbus", "cbus", "system_bus", "fbus", "pbus"))) ++ + new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("implicit", "sbus", "mbus", "cbus", "system_bus", "fbus", "pbus"), Nil)) ++ new chipyard.config.AbstractConfig) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index af6bfc1d20..21b630cc66 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -86,8 +86,8 @@ class MulticlockRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // Frequency specifications new chipyard.config.WithTileFrequency(1000.0) ++ // Matches the maximum frequency of U540 - new chipyard.clocking.WithClockGroupsCombinedByName(("uncore" , Seq("sbus", "cbus", "implicit")), - ("periphery", Seq("pbus", "fbus"))) ++ + new chipyard.clocking.WithClockGroupsCombinedByName(("uncore" , Seq("sbus", "cbus", "implicit"), Nil), + ("periphery", Seq("pbus", "fbus"), Nil)) ++ new chipyard.config.WithSystemBusFrequency(500.0) ++ // Matches the maximum frequency of U540 new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Matches the maximum frequency of U540 new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Matches the maximum frequency of U540 diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala index 20286fd672..ab00ad24cc 100644 --- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala @@ -11,7 +11,7 @@ class AbstractTraceGenConfig extends Config( new chipyard.iobinders.WithAXI4MemPunchthrough ++ new chipyard.iobinders.WithTraceGenSuccessPunchthrough ++ new chipyard.clocking.WithPassthroughClockGenerator ++ - new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "implicit"))) ++ + new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "implicit"), Nil)) ++ new chipyard.config.WithTracegenSystem ++ new chipyard.config.WithNoSubsystemDrivenClocks ++ new chipyard.config.WithMemoryBusFrequency(1000.0) ++ diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 070e3aa913..b6d6766e69 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -171,6 +171,7 @@ class WithFireSimTestChipConfigTweaks extends Config( new chipyard.config.WithSystemBusFrequency(500.0) ++ // Realistic system bus frequency new chipyard.config.WithMemoryBusFrequency(1000.0) ++ // Needs to be 1000 MHz to model DDR performance accurately new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Match the sbus and pbus frequency + new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "pbus", "fbus", "cbus", "implicit"), Seq("tile"))) ++ // Crossing specifications new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS diff --git a/generators/sifive-blocks b/generators/sifive-blocks index 534d3b74a0..abf129a33b 160000 --- a/generators/sifive-blocks +++ b/generators/sifive-blocks @@ -1 +1 @@ -Subproject commit 534d3b74a0f22e67198aa361ae987042ee56dead +Subproject commit abf129a33bf3d73dbc017f34862038b6e722b8ed From 2f2cb1ac8b9bea32b29094fa51e917879d3e9671 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 27 May 2023 11:16:18 -0700 Subject: [PATCH 9/9] Fix firesim clockgen to auto-generated the reference pll clock if not requested --- generators/firechip/src/main/scala/FireSim.scala | 12 +++++++++--- .../firechip/src/main/scala/TargetConfigs.scala | 4 ++++ 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index be016e6a01..c20abca1fd 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -38,17 +38,23 @@ class FireSimClockBridgeInstantiator extends HarnessClockInstantiator { var instantiatedClocks = LinkedHashMap[Int, (Clock, Seq[String])]() // connect wires to clock source - for ((name, (freq, clock)) <- clockMap) { - val freqMHz = (freq / (1000 * 1000)).toInt + def findOrInstantiate(freqMHz: Int, name: String): Clock = { if (!instantiatedClocks.contains(freqMHz)) { val clock = Wire(Clock()) instantiatedClocks(freqMHz) = (clock, Seq(name)) } else { instantiatedClocks(freqMHz) = (instantiatedClocks(freqMHz)._1, instantiatedClocks(freqMHz)._2 :+ name) } - clock := instantiatedClocks(freqMHz)._1 + instantiatedClocks(freqMHz)._1 + } + for ((name, (freq, clock)) <- clockMap) { + val freqMHz = (freq / (1000 * 1000)).toInt + clock := findOrInstantiate(freqMHz, name) } + // The undivided reference clock as calculated by pllConfig must be instantiated + findOrInstantiate(pllConfig.referenceFreqMHz.toInt, "reference") + val ratClocks = instantiatedClocks.map { case (freqMHz, (clock, names)) => (RationalClock(names.mkString(","), 1, pllConfig.referenceFreqMHz.toInt / freqMHz), clock) }.toSeq diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index b6d6766e69..c27abd5047 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -103,11 +103,15 @@ class WithFireSimDesignTweaks extends Config( // Tweaks to modify target clock frequencies / crossings to legacy firesim defaults class WithFireSimHighPerfClocking extends Config( + // Create clock group for uncore that does not include mbus + new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "pbus", "fbus", "cbus", "implicit"), Nil)) ++ // Optional: This sets the default frequency for all buses in the system to 3.2 GHz // (since unspecified bus frequencies will use the pbus frequency) // This frequency selection matches FireSim's legacy selection and is required // to support 200Gb NIC performance. You may select a smaller value. new chipyard.config.WithPeripheryBusFrequency(3200.0) ++ + new chipyard.config.WithSystemBusFrequency(3200.0) ++ + new chipyard.config.WithFrontBusFrequency(3200.0) ++ // Optional: These three configs put the DRAM memory system in it's own clock domain. // Removing the first config will result in the FASED timing model running // at the pbus freq (above, 3.2 GHz), which is outside the range of valid DDR3 speedgrades.