Clock and Reset IOCells

[KPrabs106]

Impact: rtl

Tell us about your environment:
Chipyard Version: 1.4.0

What is the current behavior?
IO Cells generated for clock and reset do not use IOCellKey, resulting in GenericDigitalInIOCell

What is the expected behavior?
Clock and reset IO cell generation should be using IOCellKey

Other information

I might have misunderstood how to use IOCellKey, but I think the following changes are needed:

chipyard/generators/chipyard/src/main/scala/Clocks.scala

Line 28 in e3d23f1

val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(async_reset_wire, "reset",

should be
val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(async_reset_wire, "reset", p(IOCellKey),
and

chipyard/generators/chipyard/src/main/scala/Clocks.scala

Line 97 in e3d23f1

val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock")

should be
val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey))

[jerryz123]

Thanks for catching this. Can you open a PR against dev to fix it?

[jerryz123]

Fixed, thanks for the PR