From 6145b1df4062e4cabe56fc55be71510f2c366cb7 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 25 Feb 2021 21:25:03 -0800 Subject: [PATCH] Use "tile" instead of "core" to assign freq's --- generators/chipyard/src/main/scala/ConfigFragments.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 667e514896..3f18604f57 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -193,7 +193,7 @@ class WithTLBackingMemory extends Config((site, here, up) => { case ExtTLMem => up(ExtMem, site) // enable TL backing memory }) -class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("core", fMHz) +class WithTileFrequency(fMHz: Double) extends ClockNameContainsAssignment("tile", fMHz) class WithPeripheryBusFrequencyAsDefault extends Config((site, here, up) => { case DefaultClockFrequencyKey => (site(PeripheryBusKey).dtsFrequency.get / (1000 * 1000)).toDouble