diff --git a/docs/VLSI/Basic-Flow.rst b/docs/VLSI/Basic-Flow.rst
index 27178a5422..20d36de1fd 100644
--- a/docs/VLSI/Basic-Flow.rst
+++ b/docs/VLSI/Basic-Flow.rst
@@ -63,17 +63,19 @@ We will do so by calling ``make buildfile`` with appropriate Chipyard configurat
 As in the rest of the Chipyard flows, we specify our SoC configuration using the ``CONFIG`` make variable. 
 However, unlike the rest of the Chipyard flows, in the case of physical design we might be interested in working in a hierarchical fashion and therefore we would like to work on a single module.
 Therefore, we can also specify a ``VLSI_TOP`` make variable with the same of a specific Verilog module (which should also match the name of the equivalent Chisel module) which we would like to work on.
-The makefile will automatically call tools such as Barstools and the MacroCopmiler (:ref:`Tools/Barstools:barstools`) in order to make the generated Verilog more VLSI friendly. 
-By default, the MacroCopmiler will attempt to map memories into the SRAM options within the Hammer technology plugin. However, if you are wokring with a new process technology are prefer to work with flipflop arrays, you can configure the MacroCompiler using the ``MACROCOMPILER_MODE`` make variable. For example, the ASAP7 process technology does not have associated SRAMs, and therefore the ASAP7 Hammer tutorial (:ref:`tutorial`) uses the ``MACROCOMPILER_MODE='--mode synflops'`` option (Note that synthesizing a design with only flipflops is very slow and will often may not meet constraints).
+The makefile will automatically call tools such as Barstools and the MacroCompiler (:ref:`Tools/Barstools:barstools`) in order to make the generated Verilog more VLSI friendly. 
+By default, the MacroCompiler will attempt to map memories into the SRAM options within the Hammer technology plugin. However, if you are working with a new process technology and prefer to work with flip-flop arrays, you can configure the MacroCompiler using the ``MACROCOMPILER_MODE`` make variable. For example, if your technology plugin does not have an SRAM compiler ready, you can use the ``MACROCOMPILER_MODE='--mode synflops'`` option (Note that synthesizing a design with only flipflops is very slow and will often may not meet constraints).
 
 We call the ``make buildfile`` command while also specifying the name of the process technology we are working with (same ``tech_name`` for the configuration files and plugin name) and the configuration files we created. Note, in the ASAP7 tutorial ((:ref:`tutorial`)) these configuration files are merged into a single file called ``example-asap7.yml``.
 
 Hence, if we want to monolithically place and route the entire SoC, the relevant command would be
+
 .. code-block:: shell
 
     make buildfile CONFIG=<chipyard_config_name> tech_name=<tech_name> INPUT_CONFS="example-design.yml example-tools.yml example-tech.yml"
 
-In a more typical scenario of working on a single module, for example the Gemmini accelerator within the GemminiRocketConfig Chipyard SoC configuration, the relevant command would be
+In a more typical scenario of working on a single module, for example the Gemmini accelerator within the GemminiRocketConfig Chipyard SoC configuration, the relevant command would be:
+
 .. code-block:: shell
 
     make buildfile CONFIG=GemminiRocketConfig VLSI_TOP=Gemmini tech_name=tsmintel3 INPUT_CONFS="example-design.yml example-tools.yml example-tech.yml"
@@ -89,12 +91,14 @@ Synthesis
 In order to run synthesis, we run ``make syn`` with the matching Make variables. 
 Post-synthesis logs and collateral will be saved in ``build/<config-name>/syn-rundir``. The raw QoR data (area, timing, gate counts, etc.) will be found in ``build/<config-name>/syn-rundir/reports``.
 
-Hence, if we want to monolithically synthesize the entire SoC, the relevant command would be
+Hence, if we want to monolithically synthesize the entire SoC, the relevant command would be:
+
 .. code-block:: shell
 
     make syn CONFIG=<chipyard_config_name> tech_name=<tech_name> INPUT_CONFS="example-design.yml example-tools.yml example-tech.yml"
 
-In a more typical scenario of working on a single module, for example the Gemmini accelerator within the GemminiRocketConfig Chipyard SoC configuration, the relevant command would be
+In a more typical scenario of working on a single module, for example the Gemmini accelerator within the GemminiRocketConfig Chipyard SoC configuration, the relevant command would be:
+
 .. code-block:: shell
 
     make syn CONFIG=GemminiRocketConfig VLSI_TOP=Gemmini tech_name=tsmintel3 INPUT_CONFS="example-design.yml example-tools.yml example-tech.yml"
@@ -108,7 +112,8 @@ In order to run place-and-route, we run ``make par`` with the matching Make vari
 Post-PnR logs and collateral will be saved in ``build/<config-name>/par-rundir``. Specifically, the resulting GDSII file will be in that directory with the suffix ``*.gds``. and timing reports can be found in ``build/<config-name>/par-rundir/timingReports``.
 Place-and-route is requires more design details in contrast to synthesis. For example, place-and-route requires some basic floorplanning constraints. The default ``example-design.yml`` configuration file template allows the tool (specifically, the Cadence Innovus tool) to use it's automatic floorplanning capability within the top level of the design (``ChipTop``). However, if we choose to place-and-route a specific block which is not the SoC top level, we need to change the top-level path name to match the ``VLSI_TOP`` make parameter we are using.
 
-Hence, if we want to monolitically place-and-route the entire SoC with the default tech plug-in parameters for power-straps and corners, the relevant command would be
+Hence, if we want to monolitically place-and-route the entire SoC with the default tech plug-in parameters for power-straps and corners, the relevant command would be:
+
 .. code-block:: shell
 
     make par CONFIG=<chipyard_config_name> tech_name=<tech_name> INPUT_CONFS="example-design.yml example-tools.yml example-tech.yml"
@@ -130,7 +135,8 @@ In a more typical scenario of working on a single module, for example the Gemmin
         top: 0
         bottom: 0
 
-The relevant ``make`` command would then be
+The relevant ``make`` command would then be:
+
 .. code-block:: shell
 
     make par CONFIG=GemminiRocketConfig VLSI_TOP=Gemmini tech_name=tsmintel3 INPUT_CONFS="example-design.yml example-tools.yml example-tech.yml"
diff --git a/docs/VLSI/Hammer.rst b/docs/VLSI/Hammer.rst
index ddfc071b48..df803b1db2 100644
--- a/docs/VLSI/Hammer.rst
+++ b/docs/VLSI/Hammer.rst
@@ -43,6 +43,8 @@ The types of tools (by Hammer names) supported currently include:
 * drc
 * lvs
 * sram_generator
+* sim
+* power
 * pcb
 
 Several configuration variables are needed to configure your tool plugin of choice.
diff --git a/docs/VLSI/Tutorial.rst b/docs/VLSI/Tutorial.rst
index 5a227d52f1..38eee0b507 100644
--- a/docs/VLSI/Tutorial.rst
+++ b/docs/VLSI/Tutorial.rst
@@ -9,7 +9,7 @@ Project Structure
 
 This example gives a suggested file structure and build system. The ``vlsi/`` folder will eventually contain the following files and folders:
 
-* Makefile
+* Makefile, sim.mk, power.mk
 
   * Integration of Hammer's build system into Chipyard and abstracts away some Hammer commands.
 
@@ -26,17 +26,13 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo
 
   * Entry point to Hammer. Contains example placeholders for hooks.
 
-* example.v
-
-  * Verilog wrapper around the accelerator and dummy hard macro.
-
-* example-asap7.yml
+* example-asap7.yml, example-tools.yml
 
   * Hammer IR for this tutorial.
 
-* extra_libraries
+* example-design.yml, example-nangate45.yml, example-tech.yml
 
-  * Contains collateral for the dummy hard macro.
+  * Hammer IR not used for this tutorial but provided as templates.
 
 * generated-src
 
@@ -46,6 +42,10 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo
 
   * Core, tool, tech repositories.
 
+* view_gds.py
+
+  * A convenience script to view a layout using gdspy. Note that this will be very slow for large layouts (e.g. a Rocket core)!
+
 Prerequisites
 -------------
 
@@ -54,7 +54,7 @@ Prerequisites
 * Genus, Innovus, and Calibre licenses
 * For ASAP7 specifically:
 
-  * Download the `ASAP7 PDK v1p5 <http://asap.asu.edu/asap/>`__ tarball to a directory of choice but do not extract it. The tech plugin is configured to extract the PDK into a cache directory for you.
+  * Download the `ASAP7 PDK v1p5 <http://asap.asu.edu/asap/>`__ tarball to a directory of choice but do not extract it. The tech plugin is configured to extract the PDK into a cache directory for you. Note: v1p5 of the PDK is not publicly available, and you will need to contact the developers for it. The v1p7 version that is `publicly released <https://github.com/The-OpenROAD-Project/asap7>`__ currently has several critical issues which prevent it from being fully integrated into the Hammer flow.
   * If you have additional ASAP7 hard macros, their LEF & GDS need to be 4x upscaled @ 4000 DBU precision. They may live outside ``extra_libraries`` at your discretion.
   * Innovus version must be >= 15.2 or <= 18.1 (ISRs excluded).
 
@@ -78,17 +78,13 @@ Pull the Hammer environment into the shell:
 
 Building the Design
 --------------------
-To elaborate the ``Sha3RocketConfig`` (Rocket Chip w/ the accelerator) and set up all prerequisites for the build system to push just the accelerator + hard macro through the flow:
+To elaborate the ``TinyRocketConfig`` and set up all prerequisites for the build system to push the design and SRAM macros through the flow:
 
 .. code-block:: shell
 
-    make buildfile MACROCOMPILER_MODE='--mode synflops' CONFIG=Sha3RocketConfig VLSI_TOP=Sha3AccelwBB
-
-The ``MACROCOMPILER_MODE='--mode synflops'`` is needed because the ASAP7 process does not yet have a memory compiler, so flip-flop arrays are used instead. This will dramatically increase the synthesis runtime if your design has a lot of memory state (e.g. large caches). This change is automatically inferred by the makefile but is included here for completeness.
+    make buildfile CONFIG=TinyRocketConfig
 
-The ``CONFIG=Sha3RocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a Rocket Chip with the Sha3Accel module.
-
-The ``VLSI_TOP=Sha3AccelwBB`` indicates that we are only interested in physical design of the accelerator block. If this variable is not set, the entire SoC will be pushed through physical design. Note that you should not set the ``TOP`` variable because it is used during Chisel elaboration.
+The ``CONFIG=TinyRocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a stripped-down Rocket Chip in the interest of minimizing tool runtime.
 
 For the curious, ``make buildfile`` generates a set of Make targets in ``build/hammer.d``. It needs to be re-run if environment variables are changed. It is recommended that you edit these variables directly in the Makefile rather than exporting them to your shell environment.
 
@@ -105,13 +101,13 @@ example.yml
 ^^^^^^^^^^^
 This contains the Hammer configuration for this example project. Example clock constraints, power straps definitions, placement constraints, and pin constraints are given. Additional configuration for the extra libraries and tools are at the bottom.
 
-First, set ``technology.asap7.tarball_dir`` to the absolute path of where the downloaded the ASAP7 PDK tarball lives.
+First, set ``technology.asap7.tarball_dir`` to the absolute path to the directory where the downloaded the ASAP7 PDK tarball lives.
 
 Synthesis
 ^^^^^^^^^
 .. code-block:: shell
 
-    make syn
+    make syn CONFIG=TinyRocketConfig
 
 Post-synthesis logs and collateral are in ``build/syn-rundir``. The raw QoR data is available at ``build/syn-rundir/reports``, and methods to extract this information for design space exploration are a WIP.
 
@@ -119,7 +115,7 @@ Place-and-Route
 ^^^^^^^^^^^^^^^
 .. code-block:: shell
 
-    make par
+    make par CONFIG=TinyRocketConfig
 
 After completion, the final database can be opened in an interactive Innovus session via ``./build/par-rundir/generated-scripts/open_chip``.
 
@@ -131,7 +127,7 @@ Timing reports are found in ``build/par-rundir/timingReports``. They are gzipped
 
 .. code-block:: shell
 
-    python3 view_gds.py build/par-rundir/Sha3AccelwBB.gds
+    python3 view_gds.py build/chipyard.TestHarness.TinyRocketConfig/par-rundir/ChipTop.gds
 
 By default, this script only shows the M2 thru M4 routing. Layers can be toggled in the layout viewer's side pane and ``view_gds.py`` has a mapping of layer numbers to layer names.
 
@@ -141,9 +137,36 @@ To run DRC & LVS, and view the results in Calibre:
 
 .. code-block:: shell
 
-    make drc
+    make drc CONFIG=TinyRocketConfig
     ./build/drc-rundir/generated-scripts/view-drc
-    make lvs
+    make lvs CONFIG=TinyRocketConfig
     ./build/lvs-rundir/generated-scripts/view-lvs
 
 Some DRC errors are expected from this PDK, as explained in the `ASAP7 plugin readme <https://github.com/ucb-bar/hammer/tree/master/src/hammer-vlsi/technology/asap7>`__.
+Furthermore, the dummy SRAMs that are provided in this tutorial and PDK do not have any geometry inside, so will certainly cause DRC and LVS errors.
+
+Simulation
+^^^^^^^^^^
+Simulation with VCS is supported, and can be run at the RTL- or gate-level (post-synthesis and P&R). The simulation infrastructure as included here is intended for running RISC-V binaries on a Chipyard config. For example, for an RTL-level simulation:
+
+.. code-block:: shell
+
+    make sim-rtl CONFIG=TinyRocketConfig BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple
+
+Post-synthesis and post-P&R simulations use the ``sim-syn`` and ``sim-par`` targets, respectively.
+
+There are also ``-debug`` and ``-debug-timing``, which will instruct VCS to write a SAIF + VPD and do timing-annotated simulations, respectively. See the ``sim.mk`` file for all available targets.
+
+Note that for the ASAP7 example, gate-level simulations will currently timeout.
+
+Power/Rail Analysis
+^^^^^^^^^^^^^^^^^^^
+Post-P&R power and rail (IR drop) analysis is supported with Voltus:
+
+.. code-block:: shell
+
+    make power-par CONFIG=TinyRocketConfig
+
+If you append the ``BINARY`` variable to the command, it will use the activity file generated from a ``sim-<syn/par>-debug`` run and report dynamic power & IR drop from the toggles encoded in the waveform.
+
+Note that for ASAP7, to bypass gate-level simulation, you will need to run the power tool manually (see the generated commands in the generated ``hammer.d`` buildfile). Static and active (vectorless) power & IR drop will be reported.
diff --git a/vlsi/Makefile b/vlsi/Makefile
index 182f7a950d..6ff0e735ff 100644
--- a/vlsi/Makefile
+++ b/vlsi/Makefile
@@ -26,33 +26,33 @@ SMEMS_COMP         ?= $(tech_dir)/sram-compiler.json
 SMEMS_CACHE        ?= $(tech_dir)/sram-cache.json
 SMEMS_HAMMER       ?= $(build_dir)/$(long_name).mems.hammer.json
 
-ifeq ($(tech_name),asap7)
-	MACROCOMPILER_MODE ?= --mode synflops
-else ifdef USE_SRAM_COMPILER
+ifdef USE_SRAM_COMPILER
 	MACROCOMPILER_MODE ?= -l $(SMEMS_COMP) --use-compiler -hir $(SMEMS_HAMMER) --mode strict
 else
 	MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) --mode strict
 endif	
 
 ENV_YML            ?= $(vlsi_dir)/env.yml
-INPUT_CONFS        ?= $(if $(filter $(tech_name),nangate45),\
+INPUT_CONFS        ?= example-tools.yml \
+                      $(if $(filter $(tech_name),nangate45),\
                         example-nangate45.yml,\
                         example-asap7.yml)
 HAMMER_EXEC        ?= ./example-vlsi
 VLSI_TOP           ?= $(TOP)
 VLSI_HARNESS_DUT_NAME ?= chiptop
-VLSI_OBJ_DIR       ?= $(vlsi_dir)/build
+# If overriding, this should be relative to $(vlsi_dir)
+VLSI_OBJ_DIR       ?= build
 ifneq ($(CUSTOM_VLOG),)
-	OBJ_DIR          ?= $(VLSI_OBJ_DIR)/custom-$(VLSI_TOP)
+	OBJ_DIR          ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/custom-$(VLSI_TOP)
 else
-	OBJ_DIR          ?= $(VLSI_OBJ_DIR)/$(long_name)-$(VLSI_TOP)
+	OBJ_DIR          ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(long_name)-$(VLSI_TOP)
 endif
 
 #########################################################################################
 # general rules
 #########################################################################################
 ALL_RTL = $(TOP_FILE) $(TOP_SMEMS_FILE)
-extra_v_includes = $(build_dir)/EICG_wrapper.v $(vlsi_dir)/example.v
+extra_v_includes = $(build_dir)/EICG_wrapper.v
 ifneq ($(CUSTOM_VLOG), )
 	VLSI_RTL = $(CUSTOM_VLOG)
 	VLSI_BB = /dev/null
@@ -100,6 +100,19 @@ $(SRAM_CONF): $(SRAM_GENERATOR_CONF)
 # simulation input configuration
 #########################################################################################
 include $(base_dir)/vcs.mk
+
+SIM_FILE_REQS += \
+	$(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v
+
+# copy files but ignore *.h files in *.f since vcs has +incdir+$(build_dir)
+$(sim_files): $(SIM_FILE_REQS) | $(build_dir)
+	cp -f $^ $(build_dir)
+	$(foreach file,\
+		$^,\
+		$(if $(filter %.h,$(file)),\
+			,\
+			echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;))
+
 SIM_CONF = $(OBJ_DIR)/sim-inputs.yml
 SIM_DEBUG_CONF = $(OBJ_DIR)/sim-debug-inputs.yml
 SIM_TIMING_CONF = $(OBJ_DIR)/sim-timing-inputs.yml
@@ -149,6 +162,7 @@ endif
 
 $(SIM_DEBUG_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files)
 	mkdir -p $(dir $@)
+	mkdir -p $(output_dir)
 	echo "sim.inputs:" > $@
 	echo "  defines: ['DEBUG']" >> $@
 	echo "  defines_meta: 'append'" >> $@
@@ -157,6 +171,9 @@ $(SIM_DEBUG_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_commo
 	  echo '    - "'$$x'"' >> $@; \
 	done
 	echo "  execution_flags_meta: 'append'" >> $@
+	echo "  saif.mode: 'time'" >> $@
+	echo "  saif.start_time: '0ns'" >> $@
+	echo "  saif.end_time: '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@
 	echo "sim.outputs.waveforms: ['$(sim_out_name).vpd']" >> $@
 
 $(SIM_TIMING_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files)
@@ -192,7 +209,7 @@ endif
 SYN_CONF = $(OBJ_DIR)/inputs.yml
 GENERATED_CONFS = $(SYN_CONF)
 ifeq ($(CUSTOM_VLOG), )
-	GENERATED_CONFS += $(if $(filter $(tech_name), asap7), , $(SRAM_CONF))
+	GENERATED_CONFS += $(SRAM_CONF)
 endif
 
 $(SYN_CONF): $(VLSI_RTL) $(VLSI_BB)
diff --git a/vlsi/example-asap7.yml b/vlsi/example-asap7.yml
index c8e4a72b85..446203f4ca 100644
--- a/vlsi/example-asap7.yml
+++ b/vlsi/example-asap7.yml
@@ -40,39 +40,72 @@ par.generate_power_straps_options:
     track_spacing: 0
     track_spacing_M3: 1 # to avoid M2 shorts at higher density
     track_start: 10
-    power_utilization: 0.05
+    power_utilization: 0.2
     power_utilization_M8: 1.0
     power_utilization_M9: 1.0
 
 # Placement Constraints
 # For ASAP7, all numbers must be 4x larger than final GDS
 vlsi.inputs.placement_constraints:
-  - path: "Sha3AccelwBB"
+  - path: "ChipTop"
     type: toplevel
     x: 0
     y: 0
-    width: 300
-    height: 300
+    width: 800
+    height: 500
     margins:
       left: 0
       right: 0
       top: 0
       bottom: 0
-  - path: "Sha3AccelwBB/dco"
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
+    type: hardmacro
+    x: 550
+    y: 25
+    orientation: "r0"
+    top_layer: "M4"
+    master: "SRAM1RW4096x8"
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_1"
+    type: hardmacro
+    x: 550
+    y: 270
+    orientation: "r0"
+    top_layer: "M4"
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_2"
+    type: hardmacro
+    x: 675 
+    y: 25
+    orientation: "r0"
+    top_layer: "M4"
+    master: "SRAM1RW4096x8"
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_3"
+    type: hardmacro
+    x: 675
+    y: 270
+    orientation: "r0"
+    top_layer: "M4"
+    master: "SRAM1RW4096x8"
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/tag_array/tag_array_ext/mem_0_0"
+    type: hardmacro
+    x: 125
+    y: 150
+    orientation: "my"
+    top_layer: "M4"
+    master: "SRAM1RW64x21"
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_0_0"
     type: hardmacro
-    x: 108
-    y: 108
-    width: 128
-    height: 128
-    orientation: r0
-    top_layer: M9
-  - path: "Sha3AccelwBB/place_obs_bottom"
-    type: obstruction
-    obs_types: ["place"]
     x: 0
-    y: 0
-    width: 300
-    height: 1.08 # 1 core site tall, necessary to avoid shorts
+    y: 25
+    orientation: "my"
+    top_layer: "M4"
+    master: "SRAM1RW1024x32"
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_0"
+    type: hardmacro
+    x: 0
+    y: 260
+    orientation: "my"
+    top_layer: "M4"
+    master: "SRAM1RW1024x37"
 
 # Pin placement constraints
 vlsi.inputs.pin_mode: generated
@@ -81,64 +114,37 @@ vlsi.inputs.pin.assignments: [
   {pins: "*", layers: ["M5", "M7"], side: "bottom"}
 ]
 
-# Paths to extra libraries
-vlsi.technology.extra_libraries_meta: ["append", "deepsubst"]
-vlsi.technology.extra_libraries:
-  - library:
-      nldm liberty file_deepsubst_meta: "local"
-      nldm liberty file: "extra_libraries/example/ExampleDCO_PVT_0P63V_100C.lib"
-      lef file_deepsubst_meta: "local"
-      lef file: "extra_libraries/example/ExampleDCO.lef"
-      gds file_deepsubst_meta: "local"
-      gds file: "extra_libraries/example/ExampleDCO.gds"
-      corner:
-        nmos: "slow"
-        pmos: "slow"
-        temperature: "100 C"
-      supplies:
-        VDD: "0.63 V"
-        GND: "0 V"
-  - library:
-      nldm liberty file_deepsubst_meta: "local"
-      nldm liberty file: "extra_libraries/example/ExampleDCO_PVT_0P77V_0C.lib"
-      lef file_deepsubst_meta: "local"
-      lef file: "extra_libraries/example/ExampleDCO.lef"
-      gds file_deepsubst_meta: "local"
-      gds file: "extra_libraries/example/ExampleDCO.gds"
-      corner:
-        nmos: "fast"
-        pmos: "fast"
-        temperature: "0 C"
-      supplies:
-        VDD: "0.77 V"
-        GND: "0 V"
-
-# Because the DCO is a dummy layout, we treat it as a physical-only cell
-par.inputs.physical_only_cells_mode: append
-par.inputs.physical_only_cells_list:
-  - ExampleDCO
-
 # SRAM Compiler compiler options
 vlsi.core.sram_generator_tool: "sram_compiler"
 # You should specify a location for the SRAM generator in the tech plugin
-vlsi.core.sram_generator_tool_path: []
+vlsi.core.sram_generator_tool_path: ["hammer/src/hammer-vlsi/technology/asap7"]
 vlsi.core.sram_generator_tool_path_meta: "append"
 
 # Tool options. Replace with your tool plugin of choice.
-# Genus options
-vlsi.core.synthesis_tool: "genus"
-vlsi.core.synthesis_tool_path: ["hammer-cadence-plugins/synthesis"]
-vlsi.core.synthesis_tool_path_meta: "append"
-synthesis.genus.version: "1813"
-# Innovus options
-vlsi.core.par_tool: "innovus"
-vlsi.core.par_tool_path: ["hammer-cadence-plugins/par"]
-vlsi.core.par_tool_path_meta: "append"
-par.innovus.version: "181"
-par.innovus.design_flow_effort: "standard"
-par.inputs.gds_merge: true
-# Calibre options
-vlsi.core.drc_tool: "calibre"
-vlsi.core.drc_tool_path: ["hammer-mentor-plugins/drc"]
-vlsi.core.lvs_tool: "calibre"
-vlsi.core.lvs_tool_path: ["hammer-mentor-plugins/lvs"]
+# VCS options
+#vlsi.core.sim_tool: "vcs"
+#vlsi.core.sim_tool_path: ["hammer-synopsys-plugins/sim"]
+#vlsi.core.sim_tool_path_meta: "append"
+#sim.vcs.version: "P-2019.06"
+## Genus options
+#vlsi.core.synthesis_tool: "genus"
+#vlsi.core.synthesis_tool_path: ["hammer-cadence-plugins/synthesis"]
+#vlsi.core.synthesis_tool_path_meta: "append"
+#synthesis.genus.version: "1813"
+## Innovus options
+#vlsi.core.par_tool: "innovus"
+#vlsi.core.par_tool_path: ["hammer-cadence-plugins/par"]
+#vlsi.core.par_tool_path_meta: "append"
+#par.innovus.version: "191"
+#par.innovus.design_flow_effort: "standard"
+#par.inputs.gds_merge: true
+## Voltus options
+#vlsi.core.power_tool: "voltus"
+#vlsi.core.power_tool_path: ["hammer-cadence-plugins/power"]
+#vlsi.core.power_tool_path_meta: "append"
+#power.voltus.version: "191"
+## Calibre options
+#vlsi.core.drc_tool: "calibre"
+#vlsi.core.drc_tool_path: ["hammer-mentor-plugins/drc"]
+#vlsi.core.lvs_tool: "calibre"
+#vlsi.core.lvs_tool_path: ["hammer-mentor-plugins/lvs"]
diff --git a/vlsi/example-tools.yml b/vlsi/example-tools.yml
index 338481ec5e..aad8afe52d 100644
--- a/vlsi/example-tools.yml
+++ b/vlsi/example-tools.yml
@@ -26,7 +26,7 @@ vlsi.core.lvs_tool_path: ["hammer-mentor-plugins/lvs"]
 vlsi.core.sim_tool: "vcs"
 vlsi.core.sim_tool_path: ["hammer-synopsys-plugins/sim"]
 sim.vcs.version: "P-2019.06-SP2-5"
-# # Voltus options
+# Voltus options
 vlsi.core.power_tool: "voltus"
 vlsi.core.power_tool_path: ["hammer-cadence-plugins/power"]
 vlsi.core.power_tool_path_meta: "append"
diff --git a/vlsi/example.v b/vlsi/example.v
deleted file mode 100644
index dbc7bec50b..0000000000
--- a/vlsi/example.v
+++ /dev/null
@@ -1,65 +0,0 @@
-// Sha3Accel w/ a blackbox (a dummy DCO) included inside
-
-module Sha3AccelwBB( // @[:example.TestHarness.Sha3RocketConfig.fir@135905.2]
-  input         clock, // @[:example.TestHarness.Sha3RocketConfig.fir@135906.4]
-  input         reset, // @[:example.TestHarness.Sha3RocketConfig.fir@135907.4]
-  output        io_cmd_ready, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
-  input         io_cmd_valid, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
-  input  [6:0]  io_cmd_bits_inst_funct, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
-  input  [63:0] io_cmd_bits_rs1, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
-  input  [63:0] io_cmd_bits_rs2, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
-  input         io_mem_req_ready, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
-  output        io_mem_req_valid, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
-  output [39:0] io_mem_req_bits_addr, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
-  output [7:0]  io_mem_req_bits_tag, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
-  output [4:0]  io_mem_req_bits_cmd, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
-  output [63:0] io_mem_req_bits_data, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
-  input         io_mem_resp_valid, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
-  input  [7:0]  io_mem_resp_bits_tag, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
-  input  [63:0] io_mem_resp_bits_data, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
-  output        io_busy, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
-  input  [13:0] col_sel_b,
-  input  [15:0] row_sel_b,
-  input  [7:0]  code_regulator,
-  input         dither,
-  input         sleep_b,
-  output        dco_clock
-);
-  Sha3Accel sha3 (
-    .clock(clock),
-    .reset(reset),
-    .io_cmd_ready(io_cmd_ready),
-    .io_cmd_valid(io_cmd_valid),
-    .io_cmd_bits_inst_funct(io_cmd_bits_inst_funct),
-    .io_cmd_bits_rs1(io_cmd_bits_rs1),
-    .io_cmd_bits_rs2(io_cmd_bits_rs2),
-    .io_mem_req_ready(io_mem_req_ready),
-    .io_mem_req_valid(io_mem_req_valid),
-    .io_mem_req_bits_addr(io_mem_req_bits_addr),
-    .io_mem_req_bits_tag(io_mem_req_bits_tag),
-    .io_mem_req_bits_cmd(io_mem_req_bits_cmd),
-    .io_mem_req_bits_data(io_mem_req_bits_data),
-    .io_mem_resp_valid(io_mem_resp_valid),
-    .io_mem_resp_bits_tag(io_mem_resp_bits_tag),
-    .io_mem_resp_bits_data(io_mem_resp_bits_data),
-    .io_busy(io_busy)
-  );
-  ExampleDCO dco (
-    .col_sel_b(col_sel_b),
-    .row_sel_b(row_sel_b),
-    .code_regulator(code_regulator),
-    .dither(dither),
-    .sleep_b(sleep_b),
-    .clock(dco_clock)
-  );
-endmodule
-
-module ExampleDCO (
-  input  [13:0] col_sel_b,
-  input  [15:0] row_sel_b,
-  input  [7:0]  code_regulator,
-  input         dither,
-  input         sleep_b,
-  output        clock
-);
-endmodule
diff --git a/vlsi/extra_libraries/example/ExampleDCO.gds b/vlsi/extra_libraries/example/ExampleDCO.gds
deleted file mode 100644
index 4864e115aa..0000000000
Binary files a/vlsi/extra_libraries/example/ExampleDCO.gds and /dev/null differ
diff --git a/vlsi/extra_libraries/example/ExampleDCO.lef b/vlsi/extra_libraries/example/ExampleDCO.lef
deleted file mode 100644
index 89e81a9d57..0000000000
--- a/vlsi/extra_libraries/example/ExampleDCO.lef
+++ /dev/null
@@ -1,377 +0,0 @@
-VERSION 5.6 ;
-BUSBITCHARS "[]" ;
-DIVIDERCHAR "/" ;
-
-MACRO ExampleDCO
-  CLASS BLOCK ;
-  ORIGIN 0 0 ;
-  FOREIGN ExampleDCO 0 0 ;
-  SIZE 123.936 BY 125.536 ;
-  SYMMETRY X Y ;
-  PIN VDD
-    DIRECTION INOUT ;
-    USE POWER ;
-    PORT 
-      LAYER M5 ;
-        RECT 3.024 121.536 3.8 125.536 ;
-    END 
-  END VDD
-  PIN VSS
-    DIRECTION INOUT ;
-    USE GROUND ;
-    PORT 
-      LAYER M5 ;
-        RECT 1.728 121.536 2.5 125.536 ;
-    END 
-  END VSS
-  PIN dither
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 0.384 1.2 0.768 ;
-    END 
-  END dither
-  PIN row_sel_b[0]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 1.536 1.2 1.92 ;
-    END 
-  END row_sel_b[0]
-  PIN row_sel_b[1]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 2.688 1.2 3.072 ;
-    END 
-  END row_sel_b[1]
-  PIN row_sel_b[2]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 3.84 1.2 4.224 ;
-    END 
-  END row_sel_b[2]
-  PIN row_sel_b[3]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 4.992 1.2 5.376 ;
-    END 
-  END row_sel_b[3]
-  PIN row_sel_b[4]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 6.144 1.2 6.528 ;
-    END 
-  END row_sel_b[4]
-  PIN row_sel_b[5]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 7.296 1.2 7.68 ;
-    END 
-  END row_sel_b[5]
-  PIN row_sel_b[6]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 8.448 1.2 8.832 ;
-    END 
-  END row_sel_b[6]
-  PIN row_sel_b[7]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 9.6 1.2 9.984 ;
-    END 
-  END row_sel_b[7]
-  PIN row_sel_b[8]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 10.752 1.2 11.136 ;
-    END 
-  END row_sel_b[8]
-  PIN row_sel_b[9]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 11.904 1.2 12.288 ;
-    END 
-  END row_sel_b[9]
-  PIN row_sel_b[10]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 13.056 1.2 13.44 ;
-    END 
-  END row_sel_b[10]
-  PIN row_sel_b[11]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 14.208 1.2 14.592 ;
-    END 
-  END row_sel_b[11]
-  PIN row_sel_b[12]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 15.36 1.2 15.744 ;
-    END 
-  END row_sel_b[12]
-  PIN row_sel_b[13]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 16.512 1.2 16.896 ;
-    END 
-  END row_sel_b[13]
-  PIN row_sel_b[14]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 17.664 1.2 18.048 ;
-    END 
-  END row_sel_b[14]
-  PIN row_sel_b[15]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 18.816 1.2 19.2 ;
-    END 
-  END row_sel_b[15]
-  PIN col_sel_b[0]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 19.968 1.2 20.352 ;
-    END 
-  END col_sel_b[0]
-  PIN col_sel_b[1]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 21.12 1.2 21.504 ;
-    END 
-  END col_sel_b[1]
-  PIN col_sel_b[2]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 22.272 1.2 22.656 ;
-    END 
-  END col_sel_b[2]
-  PIN col_sel_b[3]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 23.424 1.2 23.808 ;
-    END 
-  END col_sel_b[3]
-  PIN col_sel_b[4]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 24.576 1.2 24.96 ;
-    END 
-  END col_sel_b[4]
-  PIN col_sel_b[5]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 25.728 1.2 26.112 ;
-    END 
-  END col_sel_b[5]
-  PIN col_sel_b[6]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 26.88 1.2 27.264 ;
-    END 
-  END col_sel_b[6]
-  PIN col_sel_b[7]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 28.032 1.2 28.416 ;
-    END 
-  END col_sel_b[7]
-  PIN col_sel_b[8]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 29.184 1.2 29.568 ;
-    END 
-  END col_sel_b[8]
-  PIN col_sel_b[9]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 30.336 1.2 30.72 ;
-    END 
-  END col_sel_b[9]
-  PIN col_sel_b[10]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 31.488 1.2 31.872 ;
-    END 
-  END col_sel_b[10]
-  PIN col_sel_b[11]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 32.64 1.2 33.024 ;
-    END 
-  END col_sel_b[11]
-  PIN col_sel_b[12]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 33.792 1.2 34.176 ;
-    END 
-  END col_sel_b[12]
-  PIN col_sel_b[13]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 34.944 1.2 35.328 ;
-    END 
-  END col_sel_b[13]
-  PIN code_regulator[0]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 36.096 1.2 36.48 ;
-    END 
-  END code_regulator[0]
-  PIN code_regulator[1]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 37.248 1.2 37.632 ;
-    END 
-  END code_regulator[1]
-  PIN code_regulator[2]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 38.4 1.2 38.784 ;
-    END 
-  END code_regulator[2]
-  PIN code_regulator[3]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 39.552 1.2 39.936 ;
-    END 
-  END code_regulator[3]
-  PIN code_regulator[4]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 40.704 1.2 41.088 ;
-    END 
-  END code_regulator[4]
-  PIN code_regulator[5]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 41.856 1.2 42.24 ;
-    END 
-  END code_regulator[5]
-  PIN code_regulator[6]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 43.008 1.2 43.392 ;
-    END 
-  END code_regulator[6]
-  PIN code_regulator[7]
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 44.16 1.2 44.544 ;
-    END 
-  END code_regulator[7]
-  PIN sleep_b
-    DIRECTION INPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 0.0 45.312 1.2 45.696 ;
-    END 
-  END sleep_b
-  PIN clock
-    DIRECTION OUTPUT ;
-    USE SIGNAL ;
-    PORT 
-      LAYER M4 ;
-        RECT 122.736 0.384 123.936 0.768 ;
-    END 
-  END clock
-  OBS 
-    LAYER M1 ;
-      RECT 1.2 0.0 122.736 121.536 ;
-    LAYER M2 ;
-      RECT 1.2 0.0 122.736 121.536 ;
-    LAYER M3 ;
-      RECT 1.2 0.0 122.736 121.536 ;
-    LAYER M4 ;
-      RECT 1.2 0.0 122.736 121.536 ;
-    LAYER M5 ;
-      RECT 1.2 0.0 122.736 121.536 ;
-    LAYER M6 ;
-      RECT 1.2 0.0 122.736 121.536 ;
-    LAYER M7 ;
-      RECT 1.2 0.0 122.736 121.536 ;
-    LAYER M8 ;
-      RECT 1.2 0.0 122.736 121.536 ;
-    LAYER M9 ;
-      RECT 1.2 0.0 122.736 121.536 ;
-  END 
-END ExampleDCO
-
-END LIBRARY
diff --git a/vlsi/extra_libraries/example/ExampleDCO_PVT_0P63V_100C.lib b/vlsi/extra_libraries/example/ExampleDCO_PVT_0P63V_100C.lib
deleted file mode 100644
index 53d981eb76..0000000000
--- a/vlsi/extra_libraries/example/ExampleDCO_PVT_0P63V_100C.lib
+++ /dev/null
@@ -1,142 +0,0 @@
-library (ExampleDCO_PVT_0P63V_100C) {
-    technology (cmos);
-    date : "Mon Sep  2 16:01:59 2019";
-    comment : "Generated by dotlibber.py";
-    revision : 0;
-    delay_model : table_lookup;
-    simulation : true;
-    capacitive_load_unit (1,pf);
-    voltage_unit : "1V";
-    current_unit : "1mA";
-    time_unit : "1ns";
-    pulling_resistance_unit : "1kohm";
-    nom_process : 1;
-    nom_temperature : 100;
-    nom_voltage : 0.630000;
-    voltage_map(VDD, 0.630000);
-    voltage_map(VSS, 0.000000);
-    operating_conditions("PVT_0P63V_100C") {
-        process : 1;
-        temperature : 100;
-        voltage : 0.630000;
-    }
-    default_operating_conditions : PVT_0P63V_100C;
-    lu_table_template (constraint_template_3x3) {
-        variable_1 : related_pin_transition;
-        variable_2 : constrained_pin_transition;
-        index_1 ("0.0002, 0.0004, 0.0006");
-        index_2 ("0.0002, 0.0004, 0.0006");
-    }
-    lu_table_template (delay_template_8x8) {
-        variable_1 : input_net_transition;
-        variable_2 : total_output_net_capacitance;
-        index_1 ("0.0001, 0.0002, 0.0003, 0.0004, 0.0005, 0.0006, 0.0007, 0.0008");
-        index_2 ("0.0011, 0.0022, 0.0033, 0.0044, 0.0055, 0.0066, 0.0077, 0.0088");
-    }
-
-
-    type (bus_13_to_0) {
-        base_type : array ;
-        data_type : bit ;
-        bit_width : 14 ;
-        bit_from : 13 ;
-        bit_to : 0 ;
-        downto : true ;
-    }
-
-
-    type (bus_15_to_0) {
-        base_type : array ;
-        data_type : bit ;
-        bit_width : 16 ;
-        bit_from : 15 ;
-        bit_to : 0 ;
-        downto : true ;
-    }
-
-
-    type (bus_7_to_0) {
-        base_type : array ;
-        data_type : bit ;
-        bit_width : 8 ;
-        bit_from : 7 ;
-        bit_to : 0 ;
-        downto : true ;
-    }
-    cell (ExampleDCO) {
-        dont_use : true;
-        dont_touch : true;
-        is_macro_cell : true;
-
-        pg_pin (VDD) {
-            pg_type : primary_power;
-            voltage_name : VDD;
-        }
-
-        pg_pin (VSS) {
-            pg_type : primary_ground;
-            voltage_name : VSS;
-        }
-
-        pin (clock) {
-            direction : output;
-            clock : true;
-            max_capacitance : 0.02;
-            related_power_pin : VDD;
-            related_ground_pin : VSS;
-        }
-
-        bus ( col_sel_b ) {
-            bus_type : bus_13_to_0;
-            direction : input;
-            capacitance : 0.006;
-            max_transition : 0.04;
-
-            pin ( col_sel_b[13:0] ) {
-                related_power_pin : VDD;
-                related_ground_pin : VSS;
-            }
-        }
-
-        bus ( row_sel_b ) {
-            bus_type : bus_15_to_0;
-            direction : input;
-            capacitance : 0.006;
-            max_transition : 0.04;
-
-            pin ( row_sel_b[15:0] ) {
-                related_power_pin : VDD;
-                related_ground_pin : VSS;
-            }
-        }
-
-        bus ( code_regulator ) {
-            bus_type : bus_7_to_0;
-            direction : input;
-            capacitance : 0.006;
-            max_transition : 0.04;
-
-            pin ( code_regulator[7:0] ) {
-                related_power_pin : VDD;
-                related_ground_pin : VSS;
-            }
-        }
-
-        pin (dither) {
-            direction : input;
-            capacitance : 0.006;
-            max_transition : 0.04;
-            related_power_pin : VDD;
-            related_ground_pin : VSS;
-        }
-
-        pin (sleep_b) {
-            direction : input;
-            capacitance : 0.006;
-            max_transition : 0.04;
-            related_power_pin : VDD;
-            related_ground_pin : VSS;
-        }
-    }
-
-}
diff --git a/vlsi/extra_libraries/example/ExampleDCO_PVT_0P77V_0C.lib b/vlsi/extra_libraries/example/ExampleDCO_PVT_0P77V_0C.lib
deleted file mode 100644
index 374b1899a9..0000000000
--- a/vlsi/extra_libraries/example/ExampleDCO_PVT_0P77V_0C.lib
+++ /dev/null
@@ -1,142 +0,0 @@
-library (ExampleDCO_PVT_0P77V_0C) {
-    technology (cmos);
-    date : "Mon Sep  2 16:01:59 2019";
-    comment : "Generated by dotlibber.py";
-    revision : 0;
-    delay_model : table_lookup;
-    simulation : true;
-    capacitive_load_unit (1,pf);
-    voltage_unit : "1V";
-    current_unit : "1mA";
-    time_unit : "1ns";
-    pulling_resistance_unit : "1kohm";
-    nom_process : 1;
-    nom_temperature : 0;
-    nom_voltage : 0.770000;
-    voltage_map(VDD, 0.770000);
-    voltage_map(VSS, 0.000000);
-    operating_conditions("PVT_0P77V_0C") {
-        process : 1;
-        temperature : 0;
-        voltage : 0.770000;
-    }
-    default_operating_conditions : PVT_0P77V_0C;
-    lu_table_template (constraint_template_3x3) {
-        variable_1 : related_pin_transition;
-        variable_2 : constrained_pin_transition;
-        index_1 ("0.0001, 0.0002, 0.0003");
-        index_2 ("0.0001, 0.0002, 0.0003");
-    }
-    lu_table_template (delay_template_8x8) {
-        variable_1 : input_net_transition;
-        variable_2 : total_output_net_capacitance;
-        index_1 ("0.0003, 0.0004, 0.0005, 0.0006, 0.0007, 0.0008, 0.0009, 0.001");
-        index_2 ("0.0011, 0.0022, 0.0033, 0.0044, 0.0055, 0.0066, 0.0077, 0.0088");
-    }
-
-
-    type (bus_13_to_0) {
-        base_type : array ;
-        data_type : bit ;
-        bit_width : 14 ;
-        bit_from : 13 ;
-        bit_to : 0 ;
-        downto : true ;
-    }
-
-
-    type (bus_15_to_0) {
-        base_type : array ;
-        data_type : bit ;
-        bit_width : 16 ;
-        bit_from : 15 ;
-        bit_to : 0 ;
-        downto : true ;
-    }
-
-
-    type (bus_7_to_0) {
-        base_type : array ;
-        data_type : bit ;
-        bit_width : 8 ;
-        bit_from : 7 ;
-        bit_to : 0 ;
-        downto : true ;
-    }
-    cell (ExampleDCO) {
-        dont_use : true;
-        dont_touch : true;
-        is_macro_cell : true;
-
-        pg_pin (VDD) {
-            pg_type : primary_power;
-            voltage_name : VDD;
-        }
-
-        pg_pin (VSS) {
-            pg_type : primary_ground;
-            voltage_name : VSS;
-        }
-
-        pin (clock) {
-            direction : output;
-            clock : true;
-            max_capacitance : 0.02;
-            related_power_pin : VDD;
-            related_ground_pin : VSS;
-        }
-
-        bus ( col_sel_b ) {
-            bus_type : bus_13_to_0;
-            direction : input;
-            capacitance : 0.006;
-            max_transition : 0.04;
-
-            pin ( col_sel_b[13:0] ) {
-                related_power_pin : VDD;
-                related_ground_pin : VSS;
-            }
-        }
-
-        bus ( row_sel_b ) {
-            bus_type : bus_15_to_0;
-            direction : input;
-            capacitance : 0.006;
-            max_transition : 0.04;
-
-            pin ( row_sel_b[15:0] ) {
-                related_power_pin : VDD;
-                related_ground_pin : VSS;
-            }
-        }
-
-        bus ( code_regulator ) {
-            bus_type : bus_7_to_0;
-            direction : input;
-            capacitance : 0.006;
-            max_transition : 0.04;
-
-            pin ( code_regulator[7:0] ) {
-                related_power_pin : VDD;
-                related_ground_pin : VSS;
-            }
-        }
-
-        pin (dither) {
-            direction : input;
-            capacitance : 0.006;
-            max_transition : 0.04;
-            related_power_pin : VDD;
-            related_ground_pin : VSS;
-        }
-
-        pin (sleep_b) {
-            direction : input;
-            capacitance : 0.006;
-            max_transition : 0.04;
-            related_power_pin : VDD;
-            related_ground_pin : VSS;
-        }
-    }
-
-}
diff --git a/vlsi/hammer b/vlsi/hammer
index 8fd1486499..353af21da3 160000
--- a/vlsi/hammer
+++ b/vlsi/hammer
@@ -1 +1 @@
-Subproject commit 8fd1486499b875d56f09b060f03a62775f0a6aa7
+Subproject commit 353af21da3fe6f0c2e054ac513b5db583031b962
diff --git a/vlsi/hammer-cadence-plugins b/vlsi/hammer-cadence-plugins
index 3e5b046be1..191026ed35 160000
--- a/vlsi/hammer-cadence-plugins
+++ b/vlsi/hammer-cadence-plugins
@@ -1 +1 @@
-Subproject commit 3e5b046be13fb3fd4e00402acfbfd295a5da0a68
+Subproject commit 191026ed35fd86ba471d81a130f898db2928c7f4
diff --git a/vlsi/hammer-synopsys-plugins b/vlsi/hammer-synopsys-plugins
index f8a7922220..5825e6dc4b 160000
--- a/vlsi/hammer-synopsys-plugins
+++ b/vlsi/hammer-synopsys-plugins
@@ -1 +1 @@
-Subproject commit f8a7922220c70b6905b37ab30bda6c791b594792
+Subproject commit 5825e6dc4b935e0c1ce3030dc7a94bd8d90ee5eb
diff --git a/vlsi/power.mk b/vlsi/power.mk
index 383da5f0dd..ce66606f0c 100644
--- a/vlsi/power.mk
+++ b/vlsi/power.mk
@@ -1,6 +1,10 @@
 .PHONY: $(POWER_CONF)
 power-par: $(POWER_CONF) sim-par
+power-par-$(VLSI_TOP): $(POWER_CONF) sim-par-$(VLSI_TOP)
 power-par: override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF)
+power-par-$(VLSI_TOP): override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF)
 redo-power-par: $(POWER_CONF)
+redo-power-par-$(VLSI_TOP): $(POWER_CONF)
 redo-power-par: override HAMMER_EXTRA_ARGS += -p $(POWER_CONF)
-$(OBJ_DIR)/power-par-rundir/power-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_POWER_EXTRA_ARGS)
+redo-power-par-$(VLSI_TOP): override HAMMER_EXTRA_ARGS += -p $(POWER_CONF)
+$(OBJ_DIR)/power-par-%/power-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_POWER_EXTRA_ARGS)
diff --git a/vlsi/sim.mk b/vlsi/sim.mk
index 92225737c4..5bd02853a2 100644
--- a/vlsi/sim.mk
+++ b/vlsi/sim.mk
@@ -1,48 +1,85 @@
 .PHONY: $(SIM_CONF) $(SIM_DEBUG_CONF) $(SIM_TIMING_CONF)
 # Update hammer top-level sim targets to include our generated sim configs
 redo-sim-rtl: $(SIM_CONF)
+redo-sim-rtl-$(VLSI_TOP): $(SIM_CONF)
 redo-sim-rtl: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF)
+redo-sim-rtl-$(VLSI_TOP): override HAMMER_EXTRA_ARGS += -p $(SIM_CONF)
 redo-sim-rtl: override HAMMER_SIM_RUN_DIR = sim-rtl-rundir
+redo-sim-rtl-$(VLSI_TOP): override HAMMER_SIM_RUN_DIR = sim-rtl-$(VLSI_TOP)
 redo-sim-rtl-debug: $(SIM_DEBUG_CONF) redo-sim-rtl
+redo-sim-rtl-debug-$(VLSI_TOP): $(SIM_DEBUG_CONF) redo-sim-rtl-$(VLSI_TOP)
 redo-sim-rtl-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF)
+redo-sim-rtl-debug-$(VLSI_TOP): override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF)
 
 redo-sim-syn: $(SIM_CONF)
+redo-sim-syn-$(VLSI_TOP): $(SIM_CONF)
 redo-sim-syn: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF)
+redo-sim-syn-$(VLSI_TOP): override HAMMER_EXTRA_ARGS += -p $(SIM_CONF)
 redo-sim-syn: override HAMMER_SIM_RUN_DIR = sim-syn-rundir
+redo-sim-syn-$(VLSI_TOP): override HAMMER_SIM_RUN_DIR = sim-syn-$(VLSI_TOP)
 redo-sim-syn-debug: $(SIM_DEBUG_CONF) redo-sim-syn
+redo-sim-syn-debug-$(VLSI_TOP): $(SIM_DEBUG_CONF) redo-sim-syn-$(VLSI_TOP)
 redo-sim-syn-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF)
+redo-sim-syn-debug-$(VLSI_TOP): override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF)
 redo-sim-syn-timing-debug: $(SIM_TIMING_CONF) redo-sim-syn-debug
+redo-sim-syn-timing-debug-$(VLSI_TOP): $(SIM_TIMING_CONF) redo-sim-syn-debug-$(VLSI_TOP)
 redo-sim-syn-timing-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_TIMING_CONF)
+redo-sim-syn-timing-debug-$(VLSI_TOP): override HAMMER_EXTRA_ARGS += -p $(SIM_TIMING_CONF)
 
 redo-sim-par: $(SIM_CONF)
+redo-sim-par-$(VLSI_TOP): $(SIM_CONF)
 redo-sim-par: override HAMMER_EXTRA_ARGS += -p $(SIM_CONF)
+redo-sim-par-$(VLSI_TOP): override HAMMER_EXTRA_ARGS += -p $(SIM_CONF)
 redo-sim-par: override HAMMER_SIM_RUN_DIR = sim-par-rundir
+redo-sim-par-$(VLSI_TOP): override HAMMER_SIM_RUN_DIR = sim-par-$(VLSI_TOP)
 redo-sim-par-debug: $(SIM_DEBUG_CONF) redo-sim-par
+redo-sim-par-debug-$(VLSI_TOP): $(SIM_DEBUG_CONF) redo-sim-par-$(VLSI_TOP)
 redo-sim-par-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF)
+redo-sim-par-debug-$(VLSI_TOP): override HAMMER_EXTRA_ARGS += -p $(SIM_DEBUG_CONF)
 redo-sim-par-timing-debug: $(SIM_TIMING_CONF) redo-sim-par-debug
+redo-sim-par-timing-debug-$(VLSI_TOP): $(SIM_TIMING_CONF) redo-sim-par-debug-$(VLSI_TOP)
 redo-sim-par-timing-debug: override HAMMER_EXTRA_ARGS += -p $(SIM_TIMING_CONF)
+redo-sim-par-timing-debug-$(VLSI_TOP): override HAMMER_EXTRA_ARGS += -p $(SIM_TIMING_CONF)
 
 sim-rtl: $(SIM_CONF)
+sim-rtl-$(VLSI_TOP): $(SIM_CONF)
 sim-rtl: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF)
+sim-rtl-$(VLSI_TOP): override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF)
 sim-rtl: override HAMMER_SIM_RUN_DIR = sim-rtl-rundir
+sim-rtl-$(VLSI_TOP): override HAMMER_SIM_RUN_DIR = sim-rtl-$(VLSI_TOP)
 sim-rtl-debug: $(SIM_DEBUG_CONF) sim-rtl
+sim-rtl-debug-$(VLSI_TOP): $(SIM_DEBUG_CONF) sim-rtl-$(VLSI_TOP)
 sim-rtl-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF)
-$(OBJ_DIR)/sim-rtl-rundir/sim-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_SIM_EXTRA_ARGS)
+sim-rtl-debug-$(VLSI_TOP): override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF)
 
 sim-syn: $(SIM_CONF)
+sim-syn-$(VLSI_TOP): $(SIM_CONF)
 sim-syn: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF)
+sim-syn-$(VLSI_TOP): override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF)
 sim-syn: override HAMMER_SIM_RUN_DIR = sim-syn-rundir
+sim-syn-$(VLSI_TOP): override HAMMER_SIM_RUN_DIR = sim-syn-$(VLSI_TOP)
 sim-syn-debug: $(SIM_DEBUG_CONF) sim-syn
+sim-syn-debug-$(VLSI_TOP): $(SIM_DEBUG_CONF) sim-syn-$(VLSI_TOP)
 sim-syn-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF)
+sim-syn-debug-$(VLSI_TOP): override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF)
 sim-syn-timing-debug: $(SIM_TIMING_CONF) sim-syn-debug
+sim-syn-timing-debug-$(VLSI_TOP): $(SIM_TIMING_CONF) sim-syn-debug-$(VLSI_TOP)
 sim-syn-timing-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_TIMING_CONF)
-$(OBJ_DIR)/sim-syn-rundir/sim-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_SIM_EXTRA_ARGS)
+sim-syn-timing-debug-$(VLSI_TOP): override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_TIMING_CONF)
 
 sim-par: $(SIM_CONF)
+sim-par-$(VLSI_TOP): $(SIM_CONF)
 sim-par: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF)
+sim-par-$(VLSI_TOP): override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_CONF)
 sim-par: override HAMMER_SIM_RUN_DIR = sim-par-rundir
+sim-par-$(VLSI_TOP): override HAMMER_SIM_RUN_DIR = sim-par-$(VLSI_TOP)
 sim-par-debug: $(SIM_DEBUG_CONF) sim-par
+sim-par-debug-$(VLSI_TOP): $(SIM_DEBUG_CONF) sim-par-$(VLSI_TOP)
 sim-par-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF)
+sim-par-debug-$(VLSI_TOP): override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_DEBUG_CONF)
 sim-par-timing-debug: $(SIM_TIMING_CONF) sim-par-debug
+sim-par-timing-debug-$(VLSI_TOP): $(SIM_TIMING_CONF) sim-par-debug-$(VLSI_TOP)
 sim-par-timing-debug: override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_TIMING_CONF)
-$(OBJ_DIR)/sim-par-rundir/sim-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_SIM_EXTRA_ARGS)
+sim-par-timing-debug-$(VLSI_TOP): override HAMMER_SIM_EXTRA_ARGS += -p $(SIM_TIMING_CONF)
+
+$(OBJ_DIR)/sim-%/sim-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_SIM_EXTRA_ARGS)