From 45676751f4f8ca06375e1f235db8ead41d5600b9 Mon Sep 17 00:00:00 2001
From: Philipp van Kempen <philipp.van-kempen@tum.de>
Date: Sun, 17 Nov 2024 15:06:14 +0100
Subject: [PATCH] introduce explicit spike_rv32 and spike_rv64 targets

---
 mlonmcu/target/_target.py        |  4 ++++
 mlonmcu/target/riscv/__init__.py |  4 +++-
 mlonmcu/target/riscv/spike.py    | 31 +++++++++++++++++++++++++++++++
 3 files changed, 38 insertions(+), 1 deletion(-)

diff --git a/mlonmcu/target/_target.py b/mlonmcu/target/_target.py
index 95d364022..ccce50a5f 100644
--- a/mlonmcu/target/_target.py
+++ b/mlonmcu/target/_target.py
@@ -16,6 +16,8 @@
 from .riscv import (
     EtissPulpinoTarget,
     SpikeTarget,
+    SpikeRV32Target,
+    SpikeRV64Target,
     OVPSimTarget,
     COREVOVPSimTarget,
     RiscvQemuTarget,
@@ -56,6 +58,8 @@ def get_targets():
 register_target("host_x86_ssh", HostX86SSHTarget)
 register_target("corstone300", Corstone300Target)
 register_target("spike", SpikeTarget)
+register_target("spike_rv32", SpikeRV32Target)
+register_target("spike_rv64", SpikeRV64Target)
 register_target("ovpsim", OVPSimTarget)
 register_target("corev_ovpsim", COREVOVPSimTarget)
 register_target("riscv_qemu", RiscvQemuTarget)
diff --git a/mlonmcu/target/riscv/__init__.py b/mlonmcu/target/riscv/__init__.py
index 4b50c2f1d..c53900476 100644
--- a/mlonmcu/target/riscv/__init__.py
+++ b/mlonmcu/target/riscv/__init__.py
@@ -1,6 +1,6 @@
 from .etiss_pulpino import EtissPulpinoTarget
 from .etiss import EtissTarget, EtissRV32Target, EtissRV64Target
-from .spike import SpikeTarget
+from .spike import SpikeTarget, SpikeRV32Target, SpikeRV64Target
 from .ovpsim import OVPSimTarget
 from .corev_ovpsim import COREVOVPSimTarget
 from .riscv_qemu import RiscvQemuTarget
@@ -17,6 +17,8 @@
     "EtissRV32Target",
     "EtissRV64Target",
     "SpikeTarget",
+    "SpikeRV32Target",
+    "SpikeRV64Target",
     "OVPSimTarget",
     "COREVOVPSimTarget",
     "RiscvQemuTarget",
diff --git a/mlonmcu/target/riscv/spike.py b/mlonmcu/target/riscv/spike.py
index 27e16a5cd..7572b1454 100644
--- a/mlonmcu/target/riscv/spike.py
+++ b/mlonmcu/target/riscv/spike.py
@@ -222,6 +222,37 @@ def get_backend_config(self, backend, optimized_layouts=False, optimized_schedul
                     )
         return ret
 
+    def get_target_system(self):
+        return "spike"
+
+
+class SpikeRV32Target(SpikeTarget):
+    """32-bit version of spike target"""
+
+    DEFAULTS = {
+        **SpikeTarget.DEFAULTS,
+        "xlen": 32,
+        "vlen": 0,  # vectorization=off
+        "elen": 32,
+    }
+
+    def __init__(self, name="spike_rv32", features=None, config=None):
+        super().__init__(name, features=features, config=config)
+
+
+class SpikeRV64Target(SpikeTarget):
+    """64-bit version of spike target"""
+
+    DEFAULTS = {
+        **SpikeTarget.DEFAULTS,
+        "xlen": 64,
+        "vlen": 0,  # vectorization=off
+        "elen": 64,
+    }
+
+    def __init__(self, name="spike_rv64", features=None, config=None):
+        super().__init__(name, features=features, config=config)
+
 
 if __name__ == "__main__":
     cli(target=SpikeTarget)