From 290b0f22c9a6108d0cfdadf6ca76c2bef06b81bb Mon Sep 17 00:00:00 2001 From: Philipp van Kempen Date: Thu, 14 Jul 2022 15:57:15 +0200 Subject: [PATCH] etiss_pulpino: write ini options for mstatus_fs, mstatus_vs, vlen and elen (unimplemented) --- mlonmcu/target/etiss_pulpino.py | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/mlonmcu/target/etiss_pulpino.py b/mlonmcu/target/etiss_pulpino.py index 39ac7b57b..25416c6ca 100644 --- a/mlonmcu/target/etiss_pulpino.py +++ b/mlonmcu/target/etiss_pulpino.py @@ -53,8 +53,11 @@ class EtissPulpinoTarget(RISCVTarget): "etissvp.ram_start": 0x800000, "etissvp.ram_size": 0x4000000, # 64 MB "etissvp.cycle_time_ps": 31250, # 32 MHz + "enable_fpu": True, # WIP "enable_vext": False, "enable_pext": False, + "vlen": 0, # vectorization=off + "elen": 32, "jit": None, } REQUIRED = RISCVTarget.REQUIRED + ["etiss.src_dir", "etiss.install_dir", "etissvp.script"] @@ -132,6 +135,10 @@ def cpu_arch(self): else: return "RV32IMACFD" + @property + def enable_fpu(self): + return bool(self.config["enable_fpu"]) + @property def enable_vext(self): return bool(self.config["enable_vext"]) @@ -140,6 +147,14 @@ def enable_vext(self): def enable_pext(self): return bool(self.config["enable_pext"]) + @property + def vlen(self): + return int(self.config["vlen"]) + + @property + def elen(self): + return int(self.config["elen"]) + @property def jit(self): return self.config["jit"] @@ -175,6 +190,16 @@ def write_ini(self, path): f.write(f"simple_mem_system.memseg_length_01={hex(self.ram_size)}\n") f.write("\n") f.write(f"arch.cpu_cycle_time_ps={self.cycle_time_ps}\n") + if self.enable_fpu: + # TODO: do not hardcode cpu_arch + # TODO: i.e. use cpu_arch_lower + f.write(f"arch.rv32imacfdpv.mstatus_fs=1") + if self.enable_vext: + f.write(f"arch.rv32imacfdpv.mstatus_vs=1") + if self.vlen > 0: + f.write(f"arch.rv32imacfdpv.vlen={self.vlen}") + # if self.elen > 0: + # f.write(f"arch.rv32imacfdpv.elen={self.elen}") if self.gdbserver_enable: f.write("[Plugin gdbserver]\n")