Parsing error with Verilog task enabling

[YikeZhou]

Given this:

task automatic t1;
  input a;
  output b;
  begin
    a = b;
  end
endtask

module top;
  wire i, j;
  always @(*) begin
    t1(i, j);
  end
endmodule

Run tree-sitter like this:

tree-sitter parse top.v

Got this error:

top.v	1 ms	(ERROR [11, 6] - [11, 7])

According to this part of the output, the list of arguments is incorrectly identified as list_of_variable_decl_assignments.

(ERROR [11, 6] - [11, 7])
(list_of_variable_decl_assignments [11, 7] - [11, 11]
  (variable_decl_assignment [11, 7] - [11, 8]
    (simple_identifier [11, 7] - [11, 8]))
  (variable_decl_assignment [11, 10] - [11, 11]
    (simple_identifier [11, 10] - [11, 11])))
(ERROR [11, 11] - [11, 12]))))))))))))))