From 6db5002ea65170343aa8f43fd44ec2b425cdd746 Mon Sep 17 00:00:00 2001 From: Nikita Karetnikov Date: Tue, 14 May 2019 11:43:55 +0300 Subject: [PATCH 1/2] aarch64: test strb followed by ldrb (immediate) --- tests/native/test_aarch64cpu.py | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/tests/native/test_aarch64cpu.py b/tests/native/test_aarch64cpu.py index 23cb24c33..7363719e4 100644 --- a/tests/native/test_aarch64cpu.py +++ b/tests/native/test_aarch64cpu.py @@ -7593,6 +7593,29 @@ def test_ldrb_reg_sxtx0_32(self): self.assertEqual(self.rf.read('X0'), 0x58) self.assertEqual(self.rf.read('W0'), 0x58) + # LDRB misc. + + # XXX: Add similar tests for other variants. + # XXX: Uses 'reset'. + + @itest_setregs('X0=0x4142434445464749') + @itest_custom( + ['strb w0, [sp]', 'ldrb w1, [sp]'], + multiple_insts=True + ) + def test_strb_ldrb_imm_base32(self): + self.cpu.push_int(0x5152535455565758) + stack = self.cpu.STACK + self._execute() + self.assertEqual(self.cpu.read_int(stack), 0x5152535455565749) + self.assertEqual(self.rf.read('SP'), stack) # no writeback + + stack = self.cpu.STACK + self._execute(reset=False) + self.assertEqual(self.rf.read('X1'), 0x49) + self.assertEqual(self.rf.read('W1'), 0x49) + self.assertEqual(self.rf.read('SP'), stack) # no writeback + # LDRH (immediate). # ldrh w1, [x27] base register (opt. offset omitted): w1 = [x27] From d308f3f28e77a34fe9e580ba861830e7db951174 Mon Sep 17 00:00:00 2001 From: Nikita Karetnikov Date: Tue, 14 May 2019 10:17:31 +0300 Subject: [PATCH 2/2] aarch64: use the right size in '_ldr_str_immediate' Discovered due to 'ldrb w11, [x9]' failing in symbolic mode. --- manticore/native/cpu/aarch64.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/manticore/native/cpu/aarch64.py b/manticore/native/cpu/aarch64.py index 9b67777e2..8331e4cf0 100644 --- a/manticore/native/cpu/aarch64.py +++ b/manticore/native/cpu/aarch64.py @@ -1020,7 +1020,9 @@ def _ldr_str_immediate(cpu, reg_op, mem_op, mimm_op, ldr, size=None, sextend=Fal if ldr: result = cpu.read_int(base + imm, size) if sextend: - result = Operators.SEXTEND(result, size, cpu.address_bit_size) + result = Operators.SEXTEND(result, size, reg_op.size) + else: + result = Operators.ZEXTEND(result, reg_op.size) reg_op.write(result) else: reg = reg_op.read()