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Shouldn't reset do some write cycles? #374

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tom-seddon opened this issue Sep 27, 2024 · 0 comments
Open

Shouldn't reset do some write cycles? #374

tom-seddon opened this issue Sep 27, 2024 · 0 comments
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accuracy issue with emulation accuracy

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@tom-seddon
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It does supposedly share some characteristics with the interrupt mechanism!

But in b2:

G("Reset", "Interrupts", {Ri("pc", "data!", nullptr), Rd("sp--", "pch", nullptr), Rd("sp--", "pcl", nullptr), Rd("sp--", "data", nullptr), Ra("resl", "pcl", nullptr), Ra("resh", "pch", nullptr)});

@tom-seddon tom-seddon added the accuracy issue with emulation accuracy label Sep 27, 2024
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accuracy issue with emulation accuracy
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